Search results for "SAMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid	Parallel SystemC simulation for ESL design using flexible time decoupling.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Joost Hoozemans, Stephan Wong, Zaid Al-Ars	Using VLIW softcore processors for image processing applications.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Nikolaos Ilieskou, Marijn Blom, Lou J. Somers, Michel A. Reniers, Twan Basten	Multi-Domain Virtual Prototyping in a SystemC SIL framework: A heating system case study.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Miguel Bordallo López, Alejandro Nieto, Olli Silvén, Jani Boutellier, David López Vilariño	Reconfigurable computing for future vision-capable devices.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Jan Wagner, Rolf Meyer, Rainer Buchty, Mladen Berekovic	A scriptable, standards-compliant reporting and logging extension for SystemC.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Steven D. Feldman, Pierre LaBorde, Damian Dechev	Tervel: A unification of descriptor-based techniques for non-blocking programming.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Shyamsundar Venkataraman, Rui Santos, Akash Kumar 0001, Jasper Kuijsten	Hardware task migration module for improved fault tolerance and predictability.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Jiri Kadlec	Video chain demonstrator on Xilinx Kintex7 FPGA with EdkDSP floating point accelerators.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Dimitrios Rodopoulos, Simone Corbetta, Giuseppe Massari, Simone Libutti, Francky Catthoor, Yiannakis Sazeides, Chrysostomos Nicopoulos, Antoni Portero, Etienne Cappe, Radim Vavrík, Vít Vondrák, Dimitrios Soudris, Federico Sassi, Agnes Fritsch, William Fornaciari	HARPA: Solutions for dependable performance under physically induced performance variability.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Kiki Wirianto, Amir Zjajo, Carlo Galuzzi, Rene van Leuken 0001	Multi-Domain SystemC model of 128-channel time-multiplexed neural interface front-end.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Davide Gadioli, Gianluca Palermo, Cristina Silvano	Application autotuning to support runtime adaptivity in multicore architectures.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Stefan Schürmans, Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Xiaotao Chen	ESL power estimation using virtual platforms with black box processor models.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Keshav Pingali	Parallel program = operator + schedule + parallel data structure.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Marco Jacobs	Visual processing sparks a new class of processors.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Carlos Álvarez 0001, Eduard Ayguadé, Javier Bueno, Antonio Filgueras, Daniel Jiménez-González, Xavier Martorell, Nacho Navarro, Carlos Segura, Carles Fernández, David Oro, Javier Rodríguez Saeta, Paolo Gai, Antonio Rizzo, Roberto Giorgi	The AXIOM project (Agile, eXtensible, fast I/O Module).	SAMOS	2015	DBLP DOI BibTeX RDF
1	Zhi Chen 0001, Ryoichi Inagaki, Alexandru Nicolau, Alexander V. Veidenbaum	Software fault tolerance for FPUs via vectorization.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Omar Naji, Christian Weis, Matthias Jung 0001, Norbert Wehn, Andreas Hansson 0001	A high-level DRAM timing, power and area exploration tool.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos	A virtual platform for exploring hierarchical interconnection for many-accelerator systems.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Shuo Li 0002	Physical design aware system level synthesis of hardware.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Benedikt Janßen, Fynn Schwiegelshohn, Martijn Koedam, François Duhem, Leonard Masing, Stephan Werner 0002, Christophe Huriaux, Antoine Courtay, Emilie Wheatley, Kees Goossens, Fabrice Lemonnier, Philippe Millet, Jürgen Becker 0001, Olivier Sentieys, Michael Hübner 0001	Designing applications for heterogeneous many-core architectures with the FlexTiles Platform.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Luna Backes, Alejandro Rico, Björn Franke	Experiences in speeding up computer vision applications on mobile computing platforms.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Stavros Tripakis	Bridging the semantic gap between heterogeneous modeling formalisms and FMI.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Nikolaos Zompakis, Kostas Siozios	A framework for reducing the modeling and simulation complexity of Cyberphysical Systems.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Yang Yang 0040, Stavros Tripakis, Alberto L. Sangiovanni-Vincentelli	Efficient distribution of Triggered Synchronous Block Diagrams on asynchronous platforms.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Diana Göhringer, Michael Hübner 0001, Jerónimo Castrillón, Cristina Silvano	ViPES 2015 - Preface.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Nabil Hallou, Erven Rohou, Philippe Clauss, Alain Ketterlin	Dynamic re-vectorization of binary code.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Xinnian Zheng, Pradeep Ravikumar, Lizy K. John, Andreas Gerstlauer	Learning-based analytical cross-platform performance prediction.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Dimitrios Soudris, Luigi Carro (eds.)	2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2015, Samos, Greece, July 19-23, 2015	SAMOS	2015	DBLP BibTeX RDF
1	Dionysios Diamantopoulos, Christoforos Kachris	High-level synthesizable dataflow MapReduce accelerator for FPGA-coupled data centers.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Thomas Papastergiou, Lazaros Papadopoulos, Dimitrios Soudris	Platform-aware dynamic data type refinement methodology for radix tree Data Structures.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Cédric Ben Aoun, Liliana Andrade, Torsten Mähne, François Pêcheux, Marie-Minerve Louërat, Alain Vachoux	Pre-simulation elaboration of heterogeneous systems: The SystemC multi-disciplinary virtual prototyping approach.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Pei Liu 0003, Ahmed Hemani, Kolin Paul	3D-stacked many-core architecture for biological sequence analysis problems.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Marc Reichenbach, Benjamin Pfundt, Dietmar Fey	Framework for parameter analysis of FPGA-based image processing architectures.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma	Parallelism extraction in embedded software for android devices.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Peter Waszecki, Martin Lukasiewycz, Samarjit Chakraborty	Decentralized diagnosis of permanent faults in automotive E/E architectures.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv	Generating ASIPs with reduced number of connections to the register-file.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Leandro Soares Indrusiak, Piotr Dziurzanski	An interval algebra for multiprocessor resource allocation.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Duygu Buyukaydin, Toygar Akgün	GPU implementation of an anisotropic Huber-L1 dense optical flow algorithm using OpenCL.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Diego F. de Souza, Aleksandar Ilic, Nuno Roma, Leonel Sousa	HEVC in-loop filters GPU parallelization in embedded systems.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Dimitrios Soudris, Sotirios Xydis, Christos Baloukas, Anastasia Hadzidimitriou, Ioanna Chouvarda, Kostas Stamatopoulos, Nicos Maglaveras, John Chang, Andreas Raptopoulos, David Manset, Barbara K. Pierscionek, Reem Kayyali, Nada Y. Philip, Tobias Becker, Katerina Vaporidi, Eumorphia Kondili, Dimitrios Georgopoulos, Lesley Ann Sutton, Richard Rosenquist, Lydia Scarfo, Paolo Ghia	AEGLE: A big bio-data analytics framework for integrated health-care services.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Ernst Joachim Houtgast, Vlad Mihai Sima, Koen Bertels, Zaid Al-Ars	An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Joonas Multanen, Timo Viitanen, Henry Linjamaki, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Lauri Koskinen, Jesse Simonsson, Heikki Berg, Kalle Raiskila, Tommi Zetterman	Power optimizations for transport triggered SIMD processors.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Philipp Wehner, Jens Rettkowski, Tobias Kleinschmidt, Diana Göhringer	MPSoCSim: An extended OVP simulator for modeling and evaluation of Network-on-Chip based heterogeneous MPSoCs.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Tom Spink, Harry Wagstaff, Björn Franke, Nigel P. Topham	Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Christoph Gerum, Wolfgang Rosenstiel, Oliver Bringmann 0001	Improving accuracy of source level timing simulation for GPUs using a probabilistic resource model.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Wei Quan, Andy D. Pimentel	Towards self-adaptive MPSoC systems with adaptivity throttling.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Irene Pöllänen, Billy Braithwaite, Keijo Haataja, Tiia Ikonen, Pekka J. Toivanen	Current analysis approaches and performance needs for whole slide image processing in breast cancer diagnostics.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Amir R. B. Behrouzian, Dip Goswami, Twan Basten, Marc Geilen, Hadi Alizadeh Ara	Multi-Constraint multi-processor Resource Allocation.	SAMOS	2015	DBLP DOI BibTeX RDF
1	Shinichi Kato, Minoru Watanabe	Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Sascha Uhrig	Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Roya Choupani, Stephan Wong, Mehmet R. Tolun	Multiple Description Scalable Coding for Video Transmission over Unreliable Networks.	SAMOS	2009	DBLP DOI BibTeX RDF	Scalable Video Coding, Multiple Description Coding, Multimedia Transmission
1	Per Karlström, Dake Liu	NoGAP: A Micro Architecture Construction Framework.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor	Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Alexander Monakov, Arutyun Avetisyan	Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Sander van der Maar, Kees Joost Batenburg, Jan Sijbers	Experiences with Cell-BE and GPU for Tomography.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Yale N. Patt	What Else Is Broken? Can We Fix It?	SAMOS	2009	DBLP DOI BibTeX RDF
1	Bernhard Huber, Roman Obermaisser	A Comparison of NoTA and GENESYS.	SAMOS	2009	DBLP DOI BibTeX RDF	Cross-Domain Architectures, Embedded Systems
1	Frederico Pratas, Leonel Sousa	Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Ronald G. Dreslinski, David Fick, David T. Blaauw, Dennis Sylvester, Trevor N. Mudge	Reconfigurable Multicore Server Processors for Low Power Operation.	SAMOS	2009	DBLP DOI BibTeX RDF	Server Architectures, Low Power, Reconfigurable
1	Carlos S. de La Lama, Pekka Jääskeläinen, Jarmo Takala	Programmable and Scalable Architecture for Graphics Processing Units.	SAMOS	2009	DBLP DOI BibTeX RDF	TTA, GPU, GPGPU, VLIW, OpenGL, GLSL, LLVM
1	Roberto Giorgi, Zdravko Popovic, Nikola Puzovic	Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture.	SAMOS	2009	DBLP DOI BibTeX RDF	DTA, many-core architectures
1	Pieter Bellens, Josep M. Pérez, Rosa M. Badia, Jesús Labarta	Exploiting Locality on the Cell/B.E. through Bypassing.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Roberto Airoldi, Fabio Garzia, Tapani Ahonen, Dragomir Milojevic, Jari Nurmi	Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Christian Schäck, Wolfgang Heenes, Rolf Hoffmann	A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA.	SAMOS	2009	DBLP DOI BibTeX RDF	Global Cellular Automata, FPGA, multiprocessor architecture, omega network
1	Carlo Galuzzi	Introduction to Instruction-Set Customization.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs).	SAMOS	2009	DBLP DOI BibTeX RDF
1	Pavel G. Zaykov, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev	Reconfigurable Multithreading Architectures: A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Koen Bertels, Nikitas J. Dimopoulos, Cristina Silvano, Stephan Wong (eds.)	Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings	SAMOS	2009	DBLP DOI BibTeX RDF
1	Peter Westermann, Hartmut Schröder	Modeling Scalable SIMD DSPs in LISA.	SAMOS	2009	DBLP DOI BibTeX RDF	SIMD DSPs, Scalable Processor Models, LISA
1	Toktam Taghavi, Mark Thompson 0001, Andy D. Pimentel	Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration.	SAMOS	2009	DBLP DOI BibTeX RDF	Computer architecture simulation, coordination, design space exploration, multiple views, linked views, exploratory visualization
1	Cédric Augonnet, Samuel Thibault, Raymond Namyst, Maik Nijhuis	Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Kevin J. M. Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot	Constraint-Driven Identification of Application Specific Instructions in the DURASE System.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Huynh Phung Huynh, Tulika Mitra	Runtime Adaptive Extensible Embedded Processors - A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Dmitry Nadezhkin, Sjoerd Meijer, Todor P. Stefanov, Ed F. Deprettere	Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell.	SAMOS	2009	DBLP DOI BibTeX RDF	distributed FIFO communication, the Cell BE platform, Models of Computation, Kahn Process Networks
1	Richard Membarth, Frank Hannig, Hritam Dutta, Jürgen Teich	Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Walid A. Najjar, Jason R. Villarreal	Reconfigurable Computing in the New Age of Parallelism.	SAMOS	2009	DBLP DOI BibTeX RDF	FPGAs, Reconfigurable computing
1	Ismo Hänninen, Jarmo Takala	Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata.	SAMOS	2009	DBLP DOI BibTeX RDF	nanotechnology, multiplication, arithmetic, QCA
1	Ed F. Deprettere, Ana Lucia Varbanescu	Introduction to Mastering Cell BE and GPU Execution Platforms.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Nainesh Agarwal, Nikitas J. Dimopoulos	Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Ying Xu, Aabhas S. Agarwal, Brian T. Davis	Prediction in Dynamic SDRAM Controller Policies.	SAMOS	2009	DBLP DOI BibTeX RDF	Access Control Policy, Memory Latency, SDRAM
1	Rainer Buchty, Mario Kicherer, David Kramer, Wolfgang Karl	An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé	The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Yahya Jan, Lech Józwiak	CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey.	SAMOS	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
1	Tero Rintaluoma, Timo Reinikka, Joona Rouvinen, Jani Boutellier, Pekka Jääskeläinen, Olli Silvén	Programmable Accelerators for Reconfigurable Video Decoder.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Luigi Carro, Stephan Wong	Introduction to the Future of Reconfigurable Computing and Processor Architectures.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Yale N. Patt	Can They Be Fixed: Some Thoughts After 40 Years in the Business.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Teemu Pitkänen, Vesa-Matti Hartikainen, Nirav Dave, Gopal Raghavan	802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Andy D. Pimentel, Todor P. Stefanov, Hristo Nikolov, Mark Thompson 0001, Simon Polstra, Ed F. Deprettere	Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Chris R. Jesshope, Jean-Marc Philippe, Michiel W. van Tol	An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency.	SAMOS	2008	DBLP DOI BibTeX RDF	concurrency models, resource management, heterogeneous systems, ubiquitous systems, market models
1	William Plishker, Nimish Sane, Mary Kiemb, Shuvra S. Bhattacharyya	Heterogeneous Design in Functional DIF.	SAMOS	2008	DBLP DOI BibTeX RDF	Signal Processing, Heterogeneous, Dataflow
1	Chris R. Jesshope	Introduction to Programming Multicores.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Scott Fischaber, John McAllister, Roger F. Woods	Memory-Centric Hardware Synthesis from Dataflow Models.	SAMOS	2008	DBLP DOI BibTeX RDF	template matching, dataflow, hardware synthesis
1	Alexis Vander Biest, Alienor Richard, Dragomir Milojevic, Frédéric Robert	A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation.	SAMOS	2008	DBLP DOI BibTeX RDF
1	John McAllister	Introduction to System Level Design for Heterogeneous Systems.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Daniel Iancu, Mayan Moudgill, John Glossner, Jarmo Takala	Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set.	SAMOS	2008	DBLP DOI BibTeX RDF
1	James C. Brodman, Basilio B. Fraguela, María Jesús Garzarán, David A. Padua	Design Issues in Parallel Array Languages for Shared Memory.	SAMOS	2008	DBLP DOI BibTeX RDF	parallel programming, shared memory, tiling, data parallelism
1	Kamana Sigdel, Mark Thompson 0001, Andy D. Pimentel, Todor P. Stefanov, Koen Bertels	System-Level Design Space Exploration of Dynamic Reconfigurable Architectures.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Sebastián Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramírez, Mateo Valero	Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications.	SAMOS	2008	DBLP DOI BibTeX RDF
1	Emre Özer 0001, Ronald G. Dreslinski, Trevor N. Mudge, Stuart Biles, Krisztián Flautner	Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor.	SAMOS	2008	DBLP DOI BibTeX RDF	Real-time, Energy Efficiency, Caches, Embedded Processors, SMT
1	Ismo Hänninen, Jarmo Takala	Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology.	SAMOS	2008	DBLP DOI BibTeX RDF	Nanotechnology, arithmetic, digital design

Publications at "SAMOS"( http://dblp.L3S.de/Venues/SAMOS )