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Publications at "SLIP"( http://dblp.L3S.de/Venues/SLIP )

URL (DBLP): http://dblp.uni-trier.de/db/conf/slip

Publication years (Num. hits)
2000 (16) 2001 (19) 2002 (16) 2003 (19) 2004 (17) 2005 (15) 2006 (17) 2007 (16) 2008-2009 (32) 2010 (17) 2011-2012 (28) 2013-2014 (21) 2015-2016 (18) 2017-2019 (18) 2020-2021 (28) 2022-2023 (15)
Publication types (Num. hits)
inproceedings(289) proceedings(23)
Venues (Conferences, Journals, ...)
SLIP(312)
GrowBag graphs for keyword ? (Num. hits/coverage)

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The graphs summarize 350 occurrences of 190 keywords

Results
Found 312 publication records. Showing 312 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Louis Scheffer, Eric Nequist Why interconnect prediction doesn't work. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF constructive estimation, wire load model, interconnect prediction
1Dirk Stroobandt, Herwig Van Marck Efficient representation of interconnection length distributions using generating polynomials. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF interconnect length distributions, enumeration, VLSI CAD, generating polynomials
1Imed Ben Dhaou, Hannu Tenhunen Energy efficient high-speed on-chip signaling in deep-submicron CMOS technology. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Mariagrazia Graziano, Marco Delaurenti, Maurizio Zamboni Power supply design parameters prediction for high performance IC design flows. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Peng Li 0001, Pranab K. Nag, Wojciech Maly Cost based tradeoff analysis of standard cell designs. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF a posteriori wire length estimation, die size estimation, yield and cost prediction
1 The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  BibTeX  RDF
1Denis Deschacht, Grégory Servel, Fabrice Huret, Erick Paleczny, Patrick Kennis Theoretical limits for signal reflections due to inductance for on-chip interconnections. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Srinivas Bodapati, Farid N. Najm Pre-layout estimation of individual wire lengths. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Andrew B. Kahng, Dirk Stroobandt Wiring layer assignments with consistent stage delays. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF via impact, routing, delay, wire length, layer assignment
1Dennis Sylvester Measurement techniques and interconnect estimation. Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF capacitance measurement, interconnect characterization, noise measurement, process variation, interconnect estimation
1Amir H. Farrahi Estimation and removal or routing congestion (discussion session). Search on Bibsonomy SLIP The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
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