| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Sudipa Mandal, Krushna Gaurkar, Pallab Dasgupta, Aritra Hazra |
An RL based Approach for Thermal-Aware Energy Optimized Task Scheduling in Multi-core Processors.  |
VLSID  |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandra Jean, Aneesh Raveendran, A. David Selvakumar, Gagandeep Kaur, Shankar G. Dharani, Shashikala Gunderao Pattanshetty, Vivian Desalphine |
P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Kumari Anjali, Shubham Saha, Anuj Grover |
Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasenjit Saha, Hema Sai Kalluru, Zia Abbas |
Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Souradip Sen, Utkarsh Upadhyaya, Krishna Reddy Kondreddy, Arun Goyal, Sandeep Goyal, Shalabh Gupta |
A Low Jitter Digital Loop CDR Based 8-16 Gbps SerDes in 65 nm CMOS Technology. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Vasudevan Madampu Suryasarman, Santosh Biswas, Aryabartta Sahu |
Automated Low-Cost SBST Optimization Techniques for Processor Testing. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Vipul Singhal 0001, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha P. Chandrakasan |
150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumanta Pyne |
Instruction Controlled In-memory Sorting on Memristor Crossbars. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Arjun Kumar, Akhilesh Rawat, Brajesh Rawat |
Prospects of Two-dimensional Material-based Field-Effect Transistors for Analog/RF Applications. |
VLSID |
2021 |
DBLP DOI BibTeX RDF |
|
| 1 | Piyali Datta, Arpan Chakraborty, Rajat Kumar Pal |
A Design Optimization for Pin-Constrained Paper-based Digital Microfluidic Biochips Integrating Fluid-Control Co-Design Issues. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasad Kulkarni |
Alternative Reduced Hardware MASHI-I-I Digital Delta Sigma Architecture. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian |
CoveRT: A Coverage Reporting Tool for Analog Mixed-Signal Designs. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Srijeeta Maity, Anirban Ghose, Soumyajit Dey, Swarnendu Biswas |
Thermal Load-aware Adaptive Scheduling for Heterogeneous Platforms. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Suk Lee |
Keynote: Technology directions for a bright semiconductor future. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma 0001 |
Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdelrahman Hosny, Andrew B. Kahng |
Tutorial: Open-Source EDA and Machine Learning for IC Design: A Live Update. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan |
Fault Tolerance through Invariant Checking for the Lanczos Eigensolver. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Joydeep Kumar Devnath, Neelam Surana, Joycee Mekie |
A Mathematical Approach Towards Quantization of Floating Point Weights in Low Power Neural Networks. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Satyajit Mohapatra, Nihar Ranjan Mohapatra |
The Design of Ultra Low Power SAR ADC for Implantable Cardioverter Defibrillator (ICD). |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishnendu Guha, Debasri Saha, Amlan Chakrabarti |
A Multi-Agent Co-operative Model to Facilitate Criticality based Reliability for Mixed Critical Task Execution on FPGA based Cloud Environment. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Marco Pasotti |
Power Efficient Sense Amplifier For Emerging Non Volatile Memories. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Nandan Kumar Jha, Rajat Saini, Subhrajit Nag, Sparsh Mittal |
E2GC: Energy-efficient Group Convolution in Deep Neural Networks. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreeni Poolakkal, Nagarjuna Nallam |
Enhancing the Phase-Noise-Figure-of-Merit of a Resonator using Frequency Transformations. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Frédéric Gessler, Philip Brisk, Mirjana Stojilovic |
A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Elham Shamsa, Anil Kanduri, Nima Taherinejad, Alma Pröbstl, Samarjit Chakraborty, Amir M. Rahmani, Pasi Liljeberg |
User-centric Resource Management for Embedded Multi-core Processors. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Anuj Verma, Rahul Shrestha |
A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | K. A. Shahan, J. Sheeba Rani |
FPGA based convolution and memory architecture for Convolutional Neural Network. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Md Toufiq Hasan Anik, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi |
On the Effect of Aging on Digital Sensors. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Yogesh Mahajan, Shashank Obla, Mini K. Namboothiripad, Mandar J. Datar, Niraj N. Sharma, Sachin B. Patkar |
FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Hassaan Saadat, Tuo Li 0001, Haris Javaid, Sri Parameswaran |
A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashutosh Dhar, Mang Yu, Wei Zuo, Xiaohao Wang, Nam Sung Kim, Deming Chen |
Leveraging Dynamic Partial Reconfiguration with Scalable ILP Based Task Scheduling. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Purnendu Bhattaru, Nagendra Krishnapura |
A 36dB Gain Range, 0.5dB Gain Step Variable Gain Amplifier with 10 to 25MHz Bandwidth Third-Order Filter for Portable Ultrasound Systems. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Prudhvi Raj Thota, Kiran Wadagavi, Namani Rakesh, Sumit Bhat, Abirmoya Santra |
A Low Noise, Low Power, Wide Range Programmable Output Reference Buffer for Sensor Applications. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Srijit Dutta, Yaswanth Tavva, Debjyoti Bhattacharjee, Anupam Chattopadhyay |
Efficient Quantum Circuits for Square-Root and Inverse Square-Root. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Sumit Goswami, Veeresh Shetty |
Message from the General Co-Chairs. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | |
33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, VLSID 2020, Bangalore, India, January 4-8, 2020 |
VLSID |
2020 |
DBLP BibTeX RDF |
|
| 1 | David Atienza, Subhasish Mitra, Manan Suri |
Message from the Technical Program Co-Chairs. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahish Shylendra, Sina Haji Alizad, Priyesh Shukla, Amit Ranjan Trivedi |
Non-parametric Statistical Density Function Synthesizer and Monte Carlo Sampler in CMOS. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Marcel Mettler, Daniel Mueller-Gritschneder, Ulf Schlichtmann |
Runtime Monitoring of Inter- and Intra-Thread Requirements on Embedded MPSoCs. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyadarshini Panda, Kaushik Roy 0001 |
Invited Talk: Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Kishore Punniyamurthy, Shomit Das, Andreas Gerstlauer |
Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Binod Kumar 0001, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh |
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Venkatesh Kadlimatti, Prudhvi Raj Thota, Sumit Bhat |
A Novel Methodology of PWM/PFM Mode Transition for Inverting Buck-Boost and Boost Converter for AMOLED Display Applications. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Binod Kumar 0001, Akshay Kumar Jaiswal, V. S. Vineesh, Rushikesh Shinde |
Analyzing Hardware Security Properties of Processors through Model Checking. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Harita Sirugudi, Sharvani Gadgil, Chetan Vudadha |
A Novel Low Power Ternary Multiplier Design using CNFETs. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Aneesh Raveendran, Sandra Jean, J. Mervin, Vivian Desalphine, David Selvakumar |
A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Patil, Sumit Bhat, Abirmoya Santra |
An Accurate, Power and Area Efficient 13.33x Charge Pump with Wide-Range Programmability for Biomedical Sensors. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Yasaswy Kasarabada, Ranga Vemuri |
StateLock: State Transition Based Logic Locking for Sequential Circuits. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Jitumani Sarma, Rakesh Biswas |
VLSI based Adaptive Power Management Architecture for ECG Monitoring in WBAN. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Amir Aminifar, Shabbir Batterywala |
Message from the Tutorial Co-Chairs. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Arjun Singh Chauhan, Vineet Sahula, A. S. Mandal, Abhigyan Dutta |
Intensifying Challenge Obfuscation by Cascading FPGA RO-PUFs for Random Number Generation. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Mounika Kelam, Balaji Yadav Battu, Zia Abbas |
3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishalini R. Laguduva, Shakil Mahmud, Sathyanarayanan N. Aakur, Robert Karam, Srinivas Katkoori |
Dissecting Convolutional Neural Networks for Efficient Implementation on Constrained Platforms. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Vishwani D. Agrawal |
Message from the Steering Committee Chair. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Patil, Anuj Grover, Anuj Parashar |
Design of Sense Amplifier for Wide Voltage Range Operation of Split Supply Memories in 22nm HKMG CMOS Technology. |
VLSID |
2020 |
DBLP DOI BibTeX RDF |
|
| 1 | Yooseong Kim, Mohammad Khayatian, Aviral Shrivastava |
WCET-Aware Stack Frame Management of Embedded Systems Using Scratchpad Memories. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Debdut Biswas, Tarun Kanti Bhattacharyya |
A Model of Spurs for Delta-Sigma Fractional PLLs. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanjay Vidhyadharan, Ramakant Ramakant, Abhay S. Vidhyadharan, A. Krishna Shyam, Mohit P. Hirpara, Surya Shankar Dan |
An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Vipul Jain, Saurabh Kumar Gupta, Vishal Khatri, Gaurab Banerjee |
A 19.3-24.8 GHz Dual-Slope VCO in 65-nm CMOS for Automotive Radar Applications. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Hari Shanker Gupta, Sanjeev Mehta, Maryam Shojaei Baghini, Arup Roy Chowdhury, A. S. Kiran Kumar, Dinesh Kumar Sharma |
Large Dynamic Range Readout Integrated Circuit for Infrared Detectors. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Richa Agrawal, Mike Borowczak, Ranga Vemuri |
A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Manobennath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-Arrays. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Vaibhav Agarwal, Sneh Saurabh |
Realizing Boolean Functions Using Probabilistic Spin Logic (PSL). |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Tripti Nirmalkar, Deepti Kanoujia, Kshitiz Varma |
Low Complexity & Improved Efficiency of Encoded Data Using Peres Gate in BWAR with Testable Feature. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Anant Rungta, Kavindra Kandpal |
IIP3 Improvement in Subthreshold LNAs Using Modified Derivative Superposition Technique for IoT Applications. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya |
A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayan Palchaudhuri, Anindya Sundar Dhar |
VLSI Architectures for Jacobi Symbol Computation. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Piyali Datta, Arpan Chakraborty, Rajat Kumar Pal |
A Capacity-Aware Wash Optimization for Contamination Removal in Programmable Microfluidic Biochip Devices. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jayaraj U. Kidav, N. M. Sivamangai, Perumal M. Pillai, Sreejeesh S. G. |
Design and Physical Implementation of Array Signal Processor ASIC for Sector Imaging Systems. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Kedia, Anupam Sobti, Mukund Rungta, Sarvesh Chandoliya, Akhil Soni, Anil Kumar Meena, Chrystle Myrna Lobo, Richa Verma, M. Balakrishnan, Chetan Arora 0001 |
MAVI: Mobility Assistant for Visually Impaired with Optional Use of Local and Cloud Resources. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Mustafa M. Shihab, Vishwani D. Agrawal |
Energy Efficient Power Distribution on Many-Core SoC. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | |
32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019 |
VLSID |
2019 |
DBLP BibTeX RDF |
|
| 1 | Shukla Banik, Suchismita Roy, Bibhash Sen |
Test Configuration Generation for Different FPGA Architectures for Application Independent Testing. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Rahul Pathak, Raghavendra Kongari, Shankar Joshi |
Low Power Design Technique in Passive Tag to Reduce the EMD Noise for Reliable Communication with Reader. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Somdip Dey, Enrique Zaragoza Guajardo, Basireddy Karunakar Reddy, Xiaohang Wang 0001, Amit Kumar Singh 0002, Klaus D. McDonald-Maier |
EdgeCoolingMode: An Agent Based Thermal Management Mechanism for DVFS Enabled Heterogeneous MPSoCs. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Amr Sayed-Ahmed, Jawad Haj-Yahya, Anupam Chattopadhyay |
SoCINT: Resilient System-on-Chip via Dynamic Intrusion Detection. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Vaishali H. Dhare, Usha Mehta |
A Simple Synthesis Process for Combinational QCA Circuits: QSynthesizer. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ghanshyam Bairwa, Souvik Mandal, Tatavarthy Venkat Nikhil, Bodhisatwa Mazumdar |
Linear Approximation and Differential Attacks on Logic Locking Techniques. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Lalit Dani, Neeraj Mishra, Bulusu Anand |
MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthik Narayanan, Vinayak Honkote, Dibyendu Ghosh, Swamy Baldev |
Energy Efficient Communication with Lossless Data Encoding for Swarm Robot Coordination. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin Kalburgi, Deven Gupta, Sampath Holi, Rohit Shetty, Shripad Annigeri, Shraddha H, Saroja V. Siddamal, Sujata Kotabagi, Nalini C. Iyer |
Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan |
UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Pradeep Kumar Biswal, Santosh Biswas |
A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajeswari Devadoss, Kolin Paul, M. Balakrishnan |
Majority Logic: Prime Implicants and n-Input Majority Term Equivalence. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chang Hung, Nick Iliev, Balajee Vamanan, Amit Ranjan Trivedi |
Self-Organizing Maps-Based Flexible and High-Speed Packet Classification in Software Defined Networking. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Maruthi Gillela, Vaclav Prenosil, Venkat Reddy Ginjala |
Parallelization of Brute-Force Attack on MD5 Hash Algorithm on FPGA. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinti Hazarika, Mohd. Tasleem Khan, Shaik Rafi Ahamed |
Low-Complexity Continuous-Flow Memory-Based FFT Architectures for Real-Valued Signals. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Abirmoya Santra, Qadeer A. Khan |
A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-Forward Compensation. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Maneesh Kumar Pandey, Mohit Goyal, Parul Sharma, Rohit Sharma |
Modeling and Characterization of VBUS Power Discharge for Embedded Superspeed USB Host/Devices. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy |
Multidimensional Grid Aware Address Prediction for GPGPU. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Navin Singhal, M. Santosh, S. C. Bose |
Reconfigurable Digital Logic Gate Based on Neuromorphic Approach. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Aravind Krishnan Varadarajan, Michael Hsiao |
RTL Test Generation on Multi-core and Many-Core Architectures. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiran Gopal, Avanish K |
Delay Skew Reduction in IO Glitch Filter. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Arjun Singh Chauhan, Vineet Sahula, Atanendu S. Mandal |
Novel Randomized & Biased Placement for FPGA Based Robust Random Number Generator with Enhanced Uniqueness. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Japesh Vohra, Hande Vinayak Gopal |
Ultra Low Energy Reduced Switching DAC for SAR ADC. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Koushik Bharadwaj, Ashok Ray, Sushanta Bordoloi, Gaurav Trivedi |
Current Collapse Reduction Technique Using N-Doped Buffer Layer into the Bulk Region of a Gate Injection Transistor. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Shubham Negi, Ashis Maity, Amit Patra, Mrigank Sharad |
Adaptive Fractional Open Circuit Voltage Method for Maximum Power Point Tracking in a Photovoltaic Panel. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Yaswanth Krishna Yadav Danaboina, Pravanjan Samanta, Kamalika Datta, Indrajit Chakrabarti, Indranil Sengupta 0001 |
Design and Implementation of Threshold Logic Functions Using Memristors. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Gupta, Abhinav Kranti |
Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless Transistors. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashish Kumar, Mohammad Aftab Alam, Gangaikondan S. Visweswaran |
A 0.8V V_MIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Repeated-Pulse Wordline Suppression Scheme. |
VLSID |
2019 |
DBLP DOI BibTeX RDF |
|
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