Search results for "adders"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Justin Woelfle, Noureddine Chabini, Rachid Beguenane	Comparing FPGA-Based Adders and Application to the Implementation of a Digital FIR Filter.	CCECE	2023	DBLP DOI BibTeX RDF
16	Hiroyuki Hama, Toshinori Sato	Towards At-the-Edge ECG Signal Processing with Accuracy-tunable Approximate Adders.	GCCE	2023	DBLP DOI BibTeX RDF
16	Hamideh Khajehnasir-Jahromi, Pooya Torkzadeh, Massoud Dousti	Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits.	Frontiers Inf. Technol. Electron. Eng.	2022	DBLP DOI BibTeX RDF
16	Fábio G. R. G. da Silva, Rafael N. M. Oliveira, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001	Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology.	Integr.	2022	DBLP DOI BibTeX RDF
16	Gianluca Giustolisi, Gaetano Palumbo	Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders.	IEEE Access	2022	DBLP DOI BibTeX RDF
16	Jefferson Andres Bravo-Montes, Alonso Martín-Toledano, Alfonso Sánchez-Macián, Oscar Ruano, Francisco Garcia-Herrero	Design and implementation of efficient QCA full-adders using fault-tolerant majority gates.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
16	Francisco Orts, Gloria Ortega López, Ernestas Filatovas, Ester M. Garzón	Implementation of three efficient 4-digit fault-tolerant quantum carry lookahead adders.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
16	Seyed Mahdi Ghadamgahi, Reza Sabbaghi-Nadooshan, Keivan Navi	Novel ternary adders and subtractors in quantum cellular automata.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
16	Alfonso Sánchez-Macián, Alonso Martín-Toledano, Jefferson Andres Bravo-Montes, Francisco Garcia-Herrero, Juan Antonio Maestro	Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale.	IEEE Trans. Emerg. Top. Comput.	2022	DBLP DOI BibTeX RDF
16	M. C. Parameshwara, Naeem Maroof	An Area-Efficient Majority Logic-Based Approximate Adders with Low Delay for Error-Resilient Applications.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
16	Francisco Javier Hernandez Santiago, Honglan Jiang, Hussam Amrouch, Andreas Gerstlauer, Leibo Liu, Jie Han 0001	Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
16	Xingzhi Fu, Qingjiang Li, Weihe Wang, Hui Xu 0010, Yinan Wang, Wei Wang, Hongqi Yu, Zhiwei Li 0008	High-Speed Memristor-Based Ripple Carry Adders in 1T1R Array Structure.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
16	Tanfer Alan, Jörg Henkel	Probability-Driven Evaluation of Lower-Part Approximation Adders.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
16	S. P. Joy Vasantha Rani, J. R. Lourdu Jennifer, P. Sudhanya	Approximate Multipliers Design Using Approximate Adders for Image Processing Applications.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
16	M. Rahimi, M. B. Ghaznavi-Ghoushchi	A novel generic modulo-2 graph with full set taxonomical conversion to parallel prefix adders.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
16	Timothy J. Baker, John P. Hayes	CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design.	ACM Trans. Design Autom. Electr. Syst.	2022	DBLP DOI BibTeX RDF
16	Sarina Nemati, Mostafa Haghi Kashani, Reza Faghih Mirzaee	Comprehensive Survey of Ternary Full Adders: Statistics, Corrections, and Assessments.	CoRR	2022	DBLP DOI BibTeX RDF
16	Ulrich Brenner, Anna Silvanus, Jannik Silvanus	Constructing depth-optimum circuits for adders and And-Or paths.	Discret. Appl. Math.	2022	DBLP DOI BibTeX RDF
16	Rémi Garcia 0002, Anastasia Volkova, Martin Kumm, Alexandre Goldsztejn, Jonas Kühle	Hardware-Aware Design of Multiplierless Second-Order IIR Filters With Minimum Adders.	IEEE Trans. Signal Process.	2022	DBLP DOI BibTeX RDF
16	Vishesh Mishra, Urbi Chatterjee	VMEO: Vector Modeling Errors and Operands for Approximate adders.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
16	Shalini Singh, Pavan Kumar Pothula, Madhav Rao	Design and Evaluation of On-chip DCT accelerators based on Novel Approximate Reverse Carry Propagate Adders.	ISVLSI	2022	DBLP DOI BibTeX RDF
16	Herman Schmit, Matthew Denton	Multi-input Serial Adders for FPGA-like Computational Fabric.	FPGA	2022	DBLP DOI BibTeX RDF
16	Martha Schnieber, Saman Fröhlich, Rolf Drechsler	Polynomial Formal Verification of Approximate Adders.	DSD	2022	DBLP DOI BibTeX RDF
16	Yilin Zhao, Qidi Zhang, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama	Evaluation of Power Analysis Attack Resistance of Masked Adders on FPGA.	ATAIT	2022	DBLP BibTeX RDF
16	Rémi Garcia 0002, Anastasia Volkova, Martin Kumm	Truncated Multiple Constant Multiplication with Minimal Number of Full Adders.	ISCAS	2022	DBLP DOI BibTeX RDF
16	Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad	Logic Locking Designs at Transistor Level for Full Adders.	iSES	2022	DBLP DOI BibTeX RDF
16	Aruru Sai Kumar, U. Siddhesh, N. Sai Kiran, K. Bhavitha	Design of High Speed 8-bit Vedic Multiplier using Brent Kung Adders.	ICCCNT	2022	DBLP DOI BibTeX RDF
16	S. Raghuram, N. Shashank	Approximate Adders for Deep Neural Network Accelerators.	VLSID	2022	DBLP DOI BibTeX RDF
16	Tomoharu Yamauchi, Hao San, Nobuyuki Yoshikawa, Olivia Chen	A Study on the Efficient Design of Adders Using Adiabatic Quantum-Flux-Parametron Circuits.	GCCE	2022	DBLP DOI BibTeX RDF
16	Maytham Allahi Rudposhti, Mojtaba Valinataj	High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic.	Integr.	2021	DBLP DOI BibTeX RDF
16		A novel cognitive Wallace compressor based multi operand adders in CNN architecture for FPGA.	J. Ambient Intell. Humaniz. Comput.	2021	DBLP DOI BibTeX RDF
16	Waqar Ahmad, Berke Ayrancioglu, Ilker Hamzaoglu	Low Error Efficient Approximate Adders for FPGAs.	IEEE Access	2021	DBLP DOI BibTeX RDF
16	Nikos Temenos, Paul P. Sotiriadis	Nonscaling Adders and Subtracters for Stochastic Computing Using Markov Chains.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
16	Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast	Toward novel designs of reversible ternary 6: 2 Compressor using efficient reversible ternary full-adders.	J. Supercomput.	2021	DBLP DOI BibTeX RDF
16	Weiqiang Liu 0001, Tingting Zhang, Emma McLarnon, Máire O'Neill, Paolo Montuschi, Fabrizio Lombardi	Design and Analysis of Majority Logic-Based Approximate Adders and Multipliers.	IEEE Trans. Emerg. Top. Comput.	2021	DBLP DOI BibTeX RDF
16	Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras	Sum Propagate Adders.	IEEE Trans. Emerg. Top. Comput.	2021	DBLP DOI BibTeX RDF
16	R. Jothin, P. Sreelatha, Ahilan Appathurai, M. Peer Mohamed	High-Performance Carry Select Adders.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
16	Celia Dharmaraj, Vinita Vasudevan, Nitin Chandrachoodan	Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders.	IET Comput. Digit. Tech.	2021	DBLP DOI BibTeX RDF
16	Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello	Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
16	Morteza Rezaalipour, Masoud Dehyadegari	Linear-time error calculation for approximate adders.	Comput. Electr. Eng.	2021	DBLP DOI BibTeX RDF
16	Hoda Ghabeli, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa	Variable Latency Carry Speculative Adders with Input-based Dynamic Configuration.	Comput. Electr. Eng.	2021	DBLP DOI BibTeX RDF
16	Seyed-Sajad Ahmadpour, Mohammad Mosleh	Ultra-efficient adders and even parity generators in nano scale.	Comput. Electr. Eng.	2021	DBLP DOI BibTeX RDF
16	Hamidreza Uoosefian, Keivan Navi, Reza Faghih Mirzaee, Mehdi Hosseinzadeh 0001	Two Novel Current-Mode CNFET-Based Full Adders Using ULPD as Voltage Regulator.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
16	M. C. Parameshwara	Approximate Full Adders for Energy Efficient Image Processing Applications.	J. Circuits Syst. Comput.	2021	DBLP DOI BibTeX RDF
16	Gang Chen, Xiaoyu Song, Guowu Yang, Ting Wang, Xiaoqiao Mu, Yongqian Fan	A Formal Proof of PG Recurrence Equations of Parallel Adders.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
16	Mohammad Moradinezhad Maryan, Majid Amini Valashani, Seyed Javad Azhari	An input controlled leakage restrainer transistor-based technique for leakage and short-circuit power reduction of 1-bit hybrid full adders.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
16	Reza Omidi 0001, Sepehr Sharifzadeh	Design of low power approximate floating-point adders.	Int. J. Circuit Theory Appl.	2021	DBLP DOI BibTeX RDF
16	Celia Dharmaraj, Vinita Vasudevan, Nitin Chandrachoodan	Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders.	ACM Trans. Embed. Comput. Syst.	2021	DBLP DOI BibTeX RDF
16	Timothy J. Baker, John P. Hayes	CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design.	CoRR	2021	DBLP BibTeX RDF
16	P. Balasubramanian 0001, Raunaq Nayar, Douglas L. Maskell	Gate-Level Static Approximate Adders.	CoRR	2021	DBLP BibTeX RDF
16	Rémi Garcia 0002, Anastasia Volkova, Martin Kumm, Alexandre Goldsztejn, Jonas Kühle	Hardware-aware Design of Multiplierless Second-Order IIR Filters with Minimum Adders.	CoRR	2021	DBLP BibTeX RDF
16	Daniel Etiemble	Best CNTFET Ternary Adders?	CoRR	2021	DBLP BibTeX RDF
16	Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus	Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing.	CoRR	2021	DBLP BibTeX RDF
16	Avireni Bhargav, Phat Huynh	Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs.	Sensors	2021	DBLP DOI BibTeX RDF
16	Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad	Design and Analysis of Obfuscated Full Adders.	ICM	2021	DBLP DOI BibTeX RDF
16	Ioannis Tsounis, Athanasios Papadimitriou, Mihalis Psarakis	Analyzing the Impact of Approximate Adders on the Reliability of FPGA Accelerators.	ETS	2021	DBLP DOI BibTeX RDF
16	Alireza Mahzoon, Rolf Drechsler	Polynomial Formal Verification of Prefix Adders.	ATS	2021	DBLP DOI BibTeX RDF
16	Yunchul Chung, Manhee Cho, Youngmin Kim	Comparison of Hardware Accelerator of Matrix Multiplication with Approximate Adders.	ICEIC	2021	DBLP DOI BibTeX RDF
16	Giorgos Dimitrakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras	Sum Propagate Adders.	ARITH	2021	DBLP DOI BibTeX RDF
16	Pedro Tauã Lopes Pereira, Guilherme Paim, Guilherme da Costa Ferreira, Eduardo A. C. da Costa, Sérgio Almeida 0001, Sergio Bampi	Exploring Approximate Adders for Power-Efficient Harmonics Elimination Hardware Architectures.	LASCAS	2021	DBLP DOI BibTeX RDF
16	Guilherme da Costa Ferreira, Pedro Tauã Lopes Pereira, Guilherme Paim, Eduardo A. C. da Costa, Sergio Bampi	A Power-Efficient FFT Hardware Architecture Exploiting Approximate Adders.	LASCAS	2021	DBLP DOI BibTeX RDF
16	Junqi Huang, T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi	Commutative Approximate Adders: Analysis and Evaluation.	NANOARCH	2021	DBLP DOI BibTeX RDF
16	Philipp Niemann 0001, Rolf Drechsler	Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic.	ISMVL	2021	DBLP DOI BibTeX RDF
16	Harpreet Kaur, Georgiy Krylov, Seyed Alireza Damghani, Kenneth B. Kent	Heterogeneous Logic Implementation for Adders in VTR.	RSP	2021	DBLP DOI BibTeX RDF
16	Marcio Monteiro, Pedro Aquino Silva, Ismael Seidel, Mateus Grellert, Leonardo Bandeira Soares, José Luís Güntzel, Cristina Meinhardt	Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders.	ISCAS	2021	DBLP DOI BibTeX RDF
16	Mineo Kaneko	Minimum Structural Transformation in Parallel Prefix Adders and its Application to Search-Based Optimization.	ISCAS	2021	DBLP DOI BibTeX RDF
16	Yilin Zhao, Qidi Zhang, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama	Power Side-Channel Analysis for Different Adders on FPGA.	ISOCC	2021	DBLP DOI BibTeX RDF
16	Ireneusz Brzozowski	Software Tool Aiding Analysis and Design of Low-Power Parallel Prefix Adders.	MIXDES	2021	DBLP DOI BibTeX RDF
16	Gerson D. Andrade, Ricardo A. L. Reis, Eduardo A. C. da Costa, Alexandra L. Zimpeck	Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy.	APCCAS	2021	DBLP DOI BibTeX RDF
16	Vijay Kandiah, Ali Murat Gök, Georgios Tziantzioulis, Nikos Hardavellas	ST2 GPU: An Energy-Efficient GPU Design with Spatio-Temporal Shared-Thread Speculative Adders.	DAC	2021	DBLP DOI BibTeX RDF
16	Alireza Mahzoon, Rolf Drechsler	Late Breaking Results: Polynomial Formal Verification of Fast Adders.	DAC	2021	DBLP DOI BibTeX RDF
16	T. Suguna, M. Janaki Rani	Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications.	Int. J. Interact. Mob. Technol.	2020	DBLP DOI BibTeX RDF
16	Mohammadreza Esmali Nojehdeh, Mustafa Altun	Systematic synthesis of approximate adders and multipliers with accurate error calculations.	Integr.	2020	DBLP DOI BibTeX RDF
16	Tuaha Nomani, Mujahid Mohsin, Zahid Pervaiz, Muhammad Shafique 0001	xUAVs: Towards Efficient Approximate Computing for UAVs - Low Power Approximate Adders With Single LUT Delay for FPGA-Based Aerial Imaging Optimization.	IEEE Access	2020	DBLP DOI BibTeX RDF
16	Avishek Sinha Roy, Rajdeep Biswas, Anindya Sundar Dhar	On Fast and Exact Computation of Error Metrics in Approximate LSB Adders.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
16	Roger Endrigo Carvalho Porto, Marcel Moscarelli Corrêa, Jones Goebel, Bruno Zatt, Nuno Roma, Luciano Agostini, Marcelo Schiavon Porto	UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise adders.	J. Real Time Image Process.	2020	DBLP DOI BibTeX RDF
16	Morteza Rezaalipour, Mohammad Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi	AxMAP: Making Approximate Adders Aware of Input Patterns.	IEEE Trans. Computers	2020	DBLP DOI BibTeX RDF
16	Mohammad Mirzaei, Siamak Mohammadi	Process variation-aware approximate full adders for imprecision-tolerant applications.	Comput. Electr. Eng.	2020	DBLP DOI BibTeX RDF
16	R. Jothin, M. Peer Mohamed, C. Vasanthanayaki	High performance compact energy efficient error tolerant adders and multipliers for 16-bit image processing applications.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
16	Thiagarajan Kowsalya	Area and power efficient pipelined hybrid merged adders for customized deep learning framework for FPGA implementation.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
16	Anusha Gorantla, Deepa P	Design of approximate adders and multipliers for error tolerant image processing.	Microprocess. Microsystems	2020	DBLP DOI BibTeX RDF
16	K. Sravani, Rathnamala Rao	Design of high throughput asynchronous FIR filter using gate level pipelined multipliers and adders.	Int. J. Circuit Theory Appl.	2020	DBLP DOI BibTeX RDF
16	Fasih Ud Din Farrukh, Chun Zhang, Yancao Jiang, Zhonghan Zhang, Ziqiang Wang, Zhihua Wang 0001, Hanjun Jiang	Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders.	IEEE Open J. Circuits Syst.	2020	DBLP DOI BibTeX RDF
16	Muhammad Kamran Ayub, Muhammad Abdullah Hanif, Osman Hasan, Muhammad Shafique 0001	PEAL: Probabilistic Error Analysis Methodology for Low-power Approximate Adders.	ACM J. Emerg. Technol. Comput. Syst.	2020	DBLP DOI BibTeX RDF
16	Mohammad Khaleqi Qaleh Jooq, Ali Bozorgmehr, Sattar Mirzakuchaki	A low power and energy efficient 4: 2 precise compressor based on novel 14T hybrid full adders in 10 nm wrap gate CNTFET technology.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
16	Pramod Patali, Shahana Thottathikkulam Kassim	Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
16	Daniel Etiemble	Best implementations of quaternary adders.	CoRR	2020	DBLP BibTeX RDF
16	Ulrich Brenner, Anna Hermann, Jannik Silvanus	Constructing Depth-Optimum Circuits for Adders and AND-OR Paths.	CoRR	2020	DBLP BibTeX RDF
16	Francisco José Orts Gómez, Gloria Ortega López, Elías F. Combarro, Ester M. Garzón	A review on reversible quantum adders.	J. Netw. Comput. Appl.	2020	DBLP DOI BibTeX RDF
16	Ghassem Jaberipur, Bardia Nadimi	Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1}, 2^{n}+2^{n-1}-1, 2^{n+1}-1\}$.	IEEE Trans. Circuits Syst. I Fundam. Theory Appl.	2020	DBLP DOI BibTeX RDF
16	Amr Mohammaden, Mohammed E. Fouda, Lobna A. Said, Ahmed G. Radwan	Memristor-CNTFET based Ternary Full Adders.	MWSCAS	2020	DBLP DOI BibTeX RDF
16	Fabio G. Rossato G. da Silva, Cristina Meinhardt, Ricardo Reis 0001	Mitigation Effects of Decoupling Cells on Full Adders Process Variability.	MWSCAS	2020	DBLP DOI BibTeX RDF
16	Wu Yang, Himanshu Thapliyal	Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing.	ISVLSI	2020	DBLP DOI BibTeX RDF
16	Somayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet	Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders.	NorCAS	2020	DBLP DOI BibTeX RDF
16	Joao N. C. Fiche, Marco T. D. Sousa, Jeferson F. Chaves, Marco A. Ribeiro, Leandro Maia Silva, Luiz Filipe M. Vieira, Omar P. Vilela Neto	Energy reduction opportunities in Field-Coupled Nanocomputing Adders.	SBCCI	2020	DBLP DOI BibTeX RDF
16	Kleanthis Papachatzopoulos, Vassilis Paliouras	Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations.	ARITH	2020	DBLP DOI BibTeX RDF
16	Pedro Aquino Silva, Cristina Meinhardt	Energy-Efficient Design of Approximated Full Adders.	ICECS	2020	DBLP DOI BibTeX RDF
16	Adriana N. Borodzhieva, Iordan I. Stoev, Ivanka D. Tsvetkova, Snezhinka Zaharieva, V. A. Mutkov	Computer-Based Education in the Course "Digital Electronics" Teaching the Topic "Adders-Subtractors".	MIPRO	2020	DBLP DOI BibTeX RDF
16	Himanshu Thapliyal, Edgard Muñoz-Coreas, Vladislav Khalus	Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing.	ICCD	2020	DBLP DOI BibTeX RDF
16	Mineo Kaneko	Insertion-Based Procedural Construction and Optimization of Parallel Prefix Adders.	ISCAS	2020	DBLP DOI BibTeX RDF