Search results for "clock-gating"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Pietro Babighian, Luca Benini, Enrico Macii	A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks.	DATE	2004	DBLP DOI BibTeX RDF
14	Cao Cao, Bengt Oelmann	Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design.	DSD	2004	DBLP DOI BibTeX RDF
14	Ruchira Sasanka, Sarita V. Adve, Yen-Kuang Chen, Eric Debes	The energy efficiency of CMP vs. SMT for multimedia workloads.	ICS	2004	DBLP DOI BibTeX RDF	multimedia, energy efficiency, CMP, SMT
14	Kim M. Hazelwood, David M. Brooks	Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization.	ISLPED	2004	DBLP DOI BibTeX RDF	voltage emergencies, power-aware computing, hardware-software co-design, dI/dt
14	Tilman Glökler, Andreas Hoffmann 0002, Heinrich Meyr	Methodical Low-Power ASIP Design Space Exploration.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	ICORE, low power, ASIP, application-specific instruction set processor, low energy, LISA
14	Arindam Mukherjee 0001, Malgorzata Marek-Sadowska	Clock and Power Gating with Timing Closure.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
14	Alex K. Jones, Prithviraj Banerjee	An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
14	Allan Hartstein, Thomas R. Puzak	Optimum Power/Performance Pipeline Depth.	MICRO	2003	DBLP DOI BibTeX RDF
14	Russ Joseph, David M. Brooks, Margaret Martonosi	Control Techniques to Eliminate Voltage Emergencies in High Performance Processors.	HPCA	2003	DBLP DOI BibTeX RDF
14	Sergio Saponara, Luca Fanucci, Luca Serafini	Low-Power FFT/IFFT VLSI Macro Cell for Scalable Broadband VDSL Modem.	IWSOC	2003	DBLP DOI BibTeX RDF
14	Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Fabrizio Pro, Massimo Poncino	Energy-aware design techniques for differential power analysis protection.	DAC	2003	DBLP DOI BibTeX RDF	low-power design, differential power analysis
14	Hongbo Yang, Guang R. Gao, Clement Leung	On achieving balanced power consumption in software pipelined loops.	CASES	2002	DBLP DOI BibTeX RDF	power-aware compilation, instruction level parallelism, software pipelining
14	Victor V. Zyuban, Philip N. Strenski	Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels.	ISLPED	2002	DBLP DOI BibTeX RDF	hardware intensity, energy efficiency, metric, power, energy
14	Ad M. G. Peeters, Kees van Berkel 0001	Synchronous Handshake Circuits.	ASYNC	2001	DBLP DOI BibTeX RDF
14	Tao Li, Chen Ding	Instruction Balance and Its Relation to Program Energy Consumption.	LCPC	2001	DBLP DOI BibTeX RDF
14	Meng Tong Tan, Joseph Sylvester Chang, Yit Chow Tong	A novel low-voltage low-power wave digital filter bank for an intelligent noise reduction digital hearing instrument.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
14	David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook	Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.	IEEE Micro	2000	DBLP DOI BibTeX RDF
14	David M. Brooks, Margaret Martonosi	Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance.	HPCA	1999	DBLP DOI BibTeX RDF
14	Uzi Zangi, Ran Ginosar	A low power video processor.	ISLPED	1998	DBLP DOI BibTeX RDF