Search results for "coprocessors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Xizhen Xu, Sotirios G. Ziavras	H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication.	ICCD	2005	DBLP DOI BibTeX RDF
12	Rodolfo Pellizzoni, Giuseppe Lipari	Improved Schedulability Analysis of Real-Time Transactions with Earliest Deadline Scheduling.	IEEE Real-Time and Embedded Technology and Applications Symposium	2005	DBLP DOI BibTeX RDF
12	Markus G. Kuhn	Security Limits for Compromising Emanations.	CHES	2005	DBLP DOI BibTeX RDF	emission security, protection standards, side channels, Eavesdropping, Tempest, video displays
12	Gerald R. Morris, Viktor K. Prasanna	An FPGA-Based Floating-Point Jacobi Iterative Solver.	ISPAN	2005	DBLP DOI BibTeX RDF
12	Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing.	DAC	2005	DBLP DOI BibTeX RDF	security IC, encryption, smart card, side-channel attack, differential power analysis, countermeasure
12	Sven Heithecker, Rolf Ernst	Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements.	DAC	2005	DBLP DOI BibTeX RDF	QoS, FPGA, flow control, priorities, memory access, traffic shaping, SDRAM
12	Deepu Talla, Ching-Yu Hung, Raj Talluri, Frank Brill, David Smith, David Brier, Bruce Xiong, Derek Huynh	Anatomy of a Portable Digital Mediaprocessor.	IEEE Micro	2004	DBLP DOI BibTeX RDF
12	Jakob Carlström, Thomas Boden	Synchronous Dataflow Architecture for Network Processors.	IEEE Micro	2004	DBLP DOI BibTeX RDF
12	Gabriel Vanrenen, Sean W. Smith	Distributing Security-Mediated PKI.	EuroPKI	2004	DBLP DOI BibTeX RDF
12	Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger	Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards.	DATE	2004	DBLP DOI BibTeX RDF
12	Elena Trichina, Tymur Korkishko	Secure AES Hardware Module for Resource Constrained Devices.	ESAS	2004	DBLP DOI BibTeX RDF
12	Prabhat Mishra 0001, Nikil D. Dutt	Functional Validation of Programmable Architectures.	DSD	2004	DBLP DOI BibTeX RDF
12	Patrick Schaumont, Kazuo Sakiyama, Alireza Hodjat, Ingrid Verbauwhede	Embedded Software Integration for Coarse-Grain Reconfigurable Systems.	IPDPS	2004	DBLP DOI BibTeX RDF
12	Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo	Improving Java Performance Using Dynamic Method Migration on FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
12	Lasse Harju, Jari Nurmi	A baseband receiver architecture for UMTS-WLAN interworking applications.	ISCC	2004	DBLP DOI BibTeX RDF
12	James Hendricks, Leendert van Doorn	Secure bootstrap is not enough: shoring up the trusted computing base.	ACM SIGOPS European Workshop	2004	DBLP DOI BibTeX RDF
12	Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar	An ultra low-power processor for sensor networks.	ASPLOS	2004	DBLP DOI BibTeX RDF	picojoule computing, sensor network processor, sensor networks, wireless, asynchronous, low-energy, event-driven
12	Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane	Network Processing Challenges and an Experimental NPU Platform.	DATE	2003	DBLP DOI BibTeX RDF
12	Tom Van Court, Martin C. Herbordt, Richard J. Barton	Case Study of a Functional Genomics Application.	FPL	2003	DBLP DOI BibTeX RDF
12	Ivan Augé, François Donnet, Frédéric Pétrot	Retiming Finite State Machines to Control Hardened Data-Paths.	SBCCI	2003	DBLP DOI BibTeX RDF
12	Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane	StepNP: A System-Level Exploration Platform for Network Processors.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
12	Martijn J. Rutten, Jos T. J. van Eijndhoven, Egbert G. T. Jaspers, Pieter van der Wolf, Evert-Jan D. Pol, Om Prakash Gangwal, Adwin H. Timmer	A Heterogeneous Multiprocessor Architecture for Flexible Media Processing.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
12	Marcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich	Reconfigurable Implementation of Elliptic Curve Crypto Algorithms.	IPDPS	2002	DBLP DOI BibTeX RDF
12	Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert-Jan D. Pol, Egbert G. T. Jaspers, Pieter van der Wolf, Om Prakash Gangwal, Adwin H. Timmer	Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing.	IPDPS	2002	DBLP DOI BibTeX RDF	high-performance media processing, heterogeneous multiprocessor architecture, Scalability, synchronization
12	Alessandro Marongiu, Paolo Palazzari, Vittorio Rosato	High Level Synthesis for Programmable Devices: The HADES Project.	IPDPS	2002	DBLP DOI BibTeX RDF
12	Chris Lattner, Shashank Shekhar, Anand Shukla, Vikram S. Adve	Addressing Fundamental Bottlenecks in Link-Time and Dynamic Optimization.	IPDPS	2002	DBLP DOI BibTeX RDF
12	Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid	Using On-Chip Configurable Logic to Reduce Embedded System Software Energy.	FCCM	2002	DBLP DOI BibTeX RDF
12	Wieland Fischer, Jean-Pierre Seifert	Note on Fast Computation of Secret RSA Exponents.	ACISP	2002	DBLP DOI BibTeX RDF	Carmichael's $lambda$-function, Secret exponent, Short public key, RSA, Chinese Remainder Theorem, Key generation
12	Alexander Iliev, Sean W. Smith	Prototyping an Armored Data Vault: Rights Management on Big Brother's Computer.	Privacy Enhancing Technologies	2002	DBLP DOI BibTeX RDF
12	Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim	Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip.	ASAP	2002	DBLP DOI BibTeX RDF
12	Jean-Jacques Quisquater	CHES: Past, Present, and Future.	CHES	2002	DBLP DOI BibTeX RDF
12	M. Ernst, Michael Jung 0002, Felix Madlener, Sorin A. Huss, Rainer Blümel	A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n).	CHES	2002	DBLP DOI BibTeX RDF	$ mathbb {GF}(2^n)$ arithmetic, Karatsuba multiplication, VHDL model generator, coprocessor synthesis, FPGA hardware acceleration, Atmel FPSLIC platform, Elliptic Curve cryptography
12	Sandra J. Weber, JoAnn M. Paul, Donald E. Thomas	Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
12	Santanu Dutta	Architecture and design of NX-2700: a programmable single-chip HDTV all-format-decode-and-display processor.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
12	Thomas Lehmann, Andreas Schreckenberg	Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux.	FPL	2001	DBLP DOI BibTeX RDF
12	James TenEyck, G. Sampath	A Java-Based Model of Resource Sharing among Independent Users on the Internet.	HPCN	2001	DBLP DOI BibTeX RDF
12	Dmitri Asonov, Markus Schaal, Johann Christoph Freytag	Absolute Privacy in Voting.	ISC	2001	DBLP DOI BibTeX RDF
12	Shan Jiang, Sean W. Smith, Kazuhiro Minami	Securing Web Servers against Insider Attack .	ACSAC	2001	DBLP DOI BibTeX RDF
12	Mary W. Hall, Craig S. Steele	Memory Management in a PIM-Based Architecture.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
12	Janusz Sosnowski, Tomasz Bech	Testing Arithmetic Coprocessor in System Environment.	DATE	2000	DBLP DOI BibTeX RDF
12	Bart Kienhuis, Edwin Rijpkema, Ed F. Deprettere	Compaan: deriving process networks from Matlab for embedded signal processing architectures.	CODES	2000	DBLP DOI BibTeX RDF	mapping, Matlab, process networks, embedded architectures
12	Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria	Instruction-level power estimation for embedded VLIW cores.	CODES	2000	DBLP DOI BibTeX RDF
12	Pascal Paillier	Low-Cost Double-Size Modular Exponentiation or How to Stretch Your Cryptoprocessor.	Public Key Cryptography	1999	DBLP DOI BibTeX RDF
12	Sean W. Smith, Elaine R. Palmer, Steve H. Weingart	Using a High-Performance, Programmable Secure Coprocessor.	Financial Cryptography	1998	DBLP DOI BibTeX RDF
12	José Carlos Alves, José Silva Matos	RVC - A Reconfigurable Coprocessor for Vector Processing Applications.	FCCM	1998	DBLP DOI BibTeX RDF
12	Rodney Van Meter, Gregory G. Finn, Steve Hotz	VISA: Netstation's Virtual Internet SCSI Adapter.	ASPLOS	1998	DBLP DOI BibTeX RDF
12	Alex R. Bugeja, W. Yang	A reconfigurable VLSI coprocessing system for the block matching algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
12	Timothy J. Callahan, John Wawrzynek	Datapath-oriented FPGA mapping and placement for configurable computing.	FCCM	1997	DBLP DOI BibTeX RDF
12	David M'Raïhi, David Naccache, Jacques Stern, Serge Vaudenay	XMX: A Firmware-Oriented Block Cipher Based on Modular Multiplications.	FSE	1997	DBLP DOI BibTeX RDF
12	Ricardo García Rosa, Teresa de Pedro, Alison Rosetti	Fuzzy Traffic Police for Autonomous Vehicles.	EUROCAST	1997	DBLP DOI BibTeX RDF	fuzzy model, autonomous vehicles
12	Yakov I. Fet	Vertical Processing Systems: A Survey.	IEEE Micro	1995	DBLP DOI BibTeX RDF
12	Michael J. Schulte, Earl E. Swartzlander Jr.	Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	arithmetic algorithms, computer arithmetic, hardware, Interval arithmetic, precision, coprocessor, numerical computations
12	Philippe Béguin, Jean-Jacques Quisquater	Fast Server-Aided RSA Signatures Secure Against Active Attacks.	CRYPTO	1995	DBLP DOI BibTeX RDF
12	F. Battini, P. L. Mantovani, Marco Mattavelli	Evaluation of a SPARC Board Equipped with the Ada Tasking Coprocessor (ATAC).	Ada-Europe	1995	DBLP DOI BibTeX RDF
12	Mircea R. Stan, Wayne P. Burleson, Christopher I. Connolly, Roderic A. Grupen	Analog VLSI for robot path planning.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
12	Rumen Andonov, Sanjay V. Rajopadhye	Optimal Tile Sizing.	CONPAR	1994	DBLP DOI BibTeX RDF	2-dimensional discrete nonlinear optimization, dynamic data dependencies, message vectorization, SPMD programs, communication-computation overlap
12	Philippe Béguin, Jean-Jacques Quisquater	Secure Acceleration of DSS Signatures Using Insecure Server.	ASIACRYPT	1994	DBLP DOI BibTeX RDF
12	Adi Shamir	Memory Efficient Variants of Public-Key Schemes for Smart Card Applications.	EUROCRYPT	1994	DBLP DOI BibTeX RDF
12	Ulrich Holtmann, Rolf Ernst	Experiments with low-level speculative computation based on multiple branch prediction.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
12	Rolf Ernst, Jörg Henkel, Thomas Benner	Hardware-Software Cosynthesis for Microcontrollers.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
12	Johannes M. Mulder, Robert J. Portier, A. Srivastava, R. in 't Velt	Efficient macro-code emulation in hardwired pipelined processors.	MICRO	1988	DBLP BibTeX RDF
12	Robert E. Loesh, Donald J. Reifer, Steven M. Jacobs	Software management issues for new system designs.	AFIPS National Computer Conference	1984	DBLP DOI BibTeX RDF