Search results for "datapath"

Hits ?▲	Authors	Title	Venue	Year	Link
17	Klaus Schneider 0001, Anoop Bhagyanath, Julius Roob	Code generation criteria for buffered exposed datapath architectures from dataflow graphs.	LCTES	2022	DBLP DOI BibTeX RDF
17	Anoop Bhagyanath, Klaus Schneider 0001	Buffer Allocation for Exposed Datapath Architectures.	MCSoC	2022	DBLP DOI BibTeX RDF
17	Armand Behroozi, Sunghyun Park 0004, Scott A. Mahlke	Loner: utilizing the CPU vector datapath to process scalar integer data.	CC	2022	DBLP DOI BibTeX RDF
17	Klaus Schneider 0001, Anoop Bhagyanath, Julius Roob	Virtual Buffers for Exposed Datapath Architectures.	MBMV	2022	DBLP BibTeX RDF
17	Junxue Zhang 0001, Chaoliang Zeng, Hong Zhang 0025, Shuihai Hu, Kai Chen 0005	LiteFlow: towards high-performance adaptive neural networks for kernel datapath.	SIGCOMM	2022	DBLP DOI BibTeX RDF
17	Samuel Coward, George A. Constantinides, Theo Drane	Automatic Datapath Optimization using E-Graphs.	ARITH	2022	DBLP DOI BibTeX RDF
17	Tomasz Osinski, Jan Palimaka, Mateusz Kossakowski, Frédéric Dang Tran, El-Fadel Bonfoh, Halina Tarasiuk	A novel programmable software datapath for software-defined networking.	CoNEXT	2022	DBLP DOI BibTeX RDF
17	Jun-Seok Park, Changsoo Park, Suknam Kwon, Hyeong-Seok Kim, Taeho Jeon, Yesung Kang, Heonsoo Lee, Dongwoo Lee, James Kim, YoungJong Lee, Sangkyu Park, Jun-Woo Jang, Sanghyuck Ha, MinSeong Kim, Jihoon Bang, Sukhwan Lim, Inyup Kang	A Multi-Mode 8K-MAC HW-Utilization-Aware Neural Processing Unit with a Unified Multi-Precision Datapath in 4nm Flagship Mobile SoC.	ISSCC	2022	DBLP DOI BibTeX RDF
17	Haiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan, Yuan Xie 0001	Alleviating datapath conflicts and design centralization in graph analytics acceleration.	DAC	2022	DBLP DOI BibTeX RDF
17	MohammadReza Taheri, Amir Sabbagh Molahosseini, Keivan Navi	Efficient Incorporation of the RNS Datapath in Reverse Converter.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
17	Paulo C. Santos 0001, João Paulo Cardoso de Lima, Rafael Fão de Moura, Marco A. Z. Alves, Antonio C. S. Beck, Luigi Carro	Enabling Near-Data Accelerators Adoption by Through Investigation of Datapath Solutions.	Int. J. Parallel Program.	2021	DBLP DOI BibTeX RDF
17	Daniele Passaretti, Thilo Pionteck	Configurable Pipelined Datapath for Data Acquisition in Interventional Computed Tomography.	FCCM	2021	DBLP DOI BibTeX RDF
17	Irene Zhang, Amanda Raybuck, Pratyush Patel, Kirk Olynyk, Jacob Nelson 0001, Omar S. Navarro Leija, Ashlie Martinez, Jing Liu, Anna Kornfeld Simpson, Sujay Jayakar, Pedro Henrique Penna, Max Demoulin, Piali Choudhury, Anirudh Badam	The Demikernel Datapath OS Architecture for Microsecond-scale Datacenter Systems.	SOSP	2021	DBLP DOI BibTeX RDF
17	Mehmet Kayaalp 0001	Using Logisim-evolution for Teaching Datapath and Control.	WCAE	2021	DBLP DOI BibTeX RDF
17	Vijay Dahiphale, Gaurav Bansod, Ankur Zambare, Narayan Pisharoty	Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA.	Frontiers Inf. Technol. Electron. Eng.	2020	DBLP DOI BibTeX RDF
17	Siva Nishok Dhanuskodi, Samuel Allen, Daniel E. Holcomb	Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
17	Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger	High Throughput/Gate AES Hardware Architectures Based on Datapath Compression.	IEEE Trans. Computers	2020	DBLP DOI BibTeX RDF
17	Shathanaa Rajmohan, Ramasubramanian Natarajan	A Memetic Algorithm-Based Design Space Exploration for Datapath Resource Allocation During High-Level Synthesis.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
17	Qi Nie, Sharad Malik	MemFlow: Memory-Driven Data Scheduling With Datapath Co-Design in Accelerators for Large-Scale Inference Applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
17	Gopinath Mahale, Pramod P. Udupa, Kiran Kolar Chandrasekharan, Sehwan Lee	WinDConv: A Fused Datapath CNN Accelerator for Power-Efficient Edge Devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
17	Shilpa Pendyala, Sheikh Ariful Islam, Srinivas Katkoori	Interval Arithmetic and Self-Similarity Based RTL Input Vector Control for Datapath Leakage Minimization.	ACM Trans. Design Autom. Electr. Syst.	2020	DBLP DOI BibTeX RDF
17	Shahzad, Eun-Sung Jung	Flexible IoT Datapath Programming using P4.	CoRR	2020	DBLP BibTeX RDF
17	Marc Dahlem, Klaus Schneider 0001	Compiling synchronous languages to optimal move code for exposed datapath architectures.	SCOPES	2020	DBLP DOI BibTeX RDF
17	Jiun Hong, TaeGeon Lee, Saad Arslan, HyungWon Kim 0001	Compact CNN Training Accelerator with Variable Floating-Point Datapath.	ISOCC	2020	DBLP DOI BibTeX RDF
17	Junghoon Cho, Junhyun Song, Jongsun Park 0001	Implementation of Low Cost ARIA Architecture with Composite Field Optimization and Datapath Modification.	ISOCC	2020	DBLP DOI BibTeX RDF
17	David Langerman, Alex Johnson, Kyle Buettner, Alan D. George	Beyond Floating-Point Ops: CNN Performance Prediction with Critical Datapath Length.	HPEC	2020	DBLP DOI BibTeX RDF
17	Nusa Zidaric	Automated Design Space Exploration and Datapath Synthesis for Finite Field Arithmetic with Applications to Lightweight Cryptography.		2020	RDF
17	Vijay Dahiphale, Hrishikesh Raut, Gaurav Bansod	Design and Implementation of novel datapath designs of lightweight cipher RECTANGLE for resource constrained environment.	Multim. Tools Appl.	2019	DBLP DOI BibTeX RDF
17	Yuki Taguchi, Ryota Kawashima, Hiroki Nakayama, Tsunemasa Hayashi, Hiroshi Matsuo	Fast Datapath Processing Based on Hop-by-Hop Packet Aggregation for Service Function Chaining.	IEICE Trans. Inf. Syst.	2019	DBLP DOI BibTeX RDF
17	Yu Wang 0136, Donghoon Yeo, Hyunchul Shin	Effective datapath logic extraction techniques using connection vectors.	IET Circuits Devices Syst.	2019	DBLP DOI BibTeX RDF
17	Utkarsh Gupta, Priyank Kalla, Vikas Rao	Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
17	Mahmood Fazlali, Mohammad K. Fallah, Naemeh Hosseinpour, Ali Katanforoush	Accelerating datapath merging by task parallelisation on multicore systems.	Int. J. Parallel Emergent Distributed Syst.	2019	DBLP DOI BibTeX RDF
17	Shathanaa Rajmohan, Ramasubramanian Natarajan	Group influence based improved firefly algorithm for Design Space Exploration of Datapath resource allocation.	Appl. Intell.	2019	DBLP DOI BibTeX RDF
17	Ho Keun Kim, Myung Hoon Sunwoo	Low Power AES Using 8-Bit and 32-Bit Datapath Optimization for Small Internet-of-Things (IoT).	J. Signal Process. Syst.	2019	DBLP DOI BibTeX RDF
17	Alex Hirvonen, Kati Tervo, Heikki Kultala, Pekka Jääskeläinen	AEx: Automated Customization of Exposed Datapath Soft-Cores.	DSD	2019	DBLP DOI BibTeX RDF
17	Kanishkan Vadivel, Roel Jordans, Sander Stuijk, Henk Corporaal, Pekka Jääskeläinen, Heikki Kultala	Towards Efficient Code Generation for Exposed Datapath Architectures.	SCOPES	2019	DBLP DOI BibTeX RDF
17	Markus Anders, Klaus Schneider 0001	A Formal Semantics of Exposed Datapath Architectures with Buffered Processing Units.	ACSD	2019	DBLP DOI BibTeX RDF
17	Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders 0001, Himanshu Kaul, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001, Vivek De, Sanu Mathew	A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
17	Qinhao Wang, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita	High-Level Engineering Change Through Programmable Datapath and SMT Solvers.	ISCAS	2019	DBLP DOI BibTeX RDF
17	Pratik Pachange, Gaurav Bansod	A Fast and Efficient Datapath Designs of Lightweight Cipher RoadRunneR on FPGA's for Resource Constrained Environments.	IoTSMS	2019	DBLP DOI BibTeX RDF
17	Anirban Sengupta, Deepak Kachave	Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath.	IEEE Trans. Aerosp. Electron. Syst.	2018	DBLP DOI BibTeX RDF
17	Marc Dahlem, Anoop Bhagyanath, Klaus Schneider 0001	Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP.	CoRR	2018	DBLP BibTeX RDF
17	Piotr Patronik, Stanislaw J. Piestrak	Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels.	J. Signal Process. Syst.	2018	DBLP DOI BibTeX RDF
17	Marc Dahlem, Anoop Bhagyanath, Klaus Schneider 0001	Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP.	Theory Pract. Log. Program.	2018	DBLP DOI BibTeX RDF
17	Avinash Raikwar, Amit Kumar Mishra	Datapath Integrated Mapping in BTS Interconnects.	MWSCAS	2018	DBLP DOI BibTeX RDF
17	Qi Nie, Sharad Malik	MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications.	ASP-DAC	2018	DBLP DOI BibTeX RDF
17	Markus Anders, Anoop Bhagyanath, Klaus Schneider 0001	On Memory Optimal Code Generation for Exposed Datapath Architectures with Buffered Processing Units.	ACSD	2018	DBLP DOI BibTeX RDF
17	Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise	A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath.	FCCM	2018	DBLP DOI BibTeX RDF
17	Mark A. Anders 0001, Himanshu Kaul, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001	2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
17	Jiaming Xu, Ao Fan, Minyi Lu, Weiwei Shan	Differential Power Analysis of 8-Bit Datapath AES for IoT Applications.	TrustCom/BigDataSE	2018	DBLP DOI BibTeX RDF
17	Minyi Lu, Ao Fan, Jiaming Xu, Weiwei Shan	A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS.	TrustCom/BigDataSE	2018	DBLP DOI BibTeX RDF
17	Arman Roohi, Ramtin Zand, Ronald F. DeMara	Logic-Encrypted Synthesis for Energy-Harvesting-Powered Spintronic-Embedded Datapath Design.	ACM Great Lakes Symposium on VLSI	2018	DBLP DOI BibTeX RDF
17	Qiao Xiang, Franck Le, Yeon-Sup Lim, Vinod K. Mishra, Christopher Williams 0001, Yang Richard Yang, Hongwei Zhang	OpenSDC: A Novel, Generic Datapath for Software Defined Coalitions.	MILCOM	2018	DBLP DOI BibTeX RDF
17	Ting Lin, Shan Cao, Shunqing Zhang, Shugong Xu	A Unified Reconfigurable Datapath for 5G Compatible LDPC Decoding.	APCCAS	2018	DBLP DOI BibTeX RDF
17	Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran	AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
17	Junghoon Oh, Mineo Kaneko	Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2017	DBLP DOI BibTeX RDF
17	Yu Wang 0136, Hyunchul Shin	Effective regularity extraction and placement techniques for datapath-intensive circuits.	IET Circuits Devices Syst.	2017	DBLP DOI BibTeX RDF
17	Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski	Advanced Datapath Synthesis using Graph Isomorphism.	CoRR	2017	DBLP BibTeX RDF
17	Payman Behnam, Bijan Alizadeh, Sajjad Taheri	Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs.	CoRR	2017	DBLP BibTeX RDF
17	Martin Broich, Tobias G. Noll	Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency.	J. Signal Process. Syst.	2017	DBLP DOI BibTeX RDF
17	Cheng-Chun Tu, Joe Stringer, Justin Pettit	Building an Extensible Open vSwitch Datapath.	ACM SIGOPS Oper. Syst. Rev.	2017	DBLP DOI BibTeX RDF
17	Anoop Bhagyanath, Klaus Schneider 0001	Exploring different execution paradigms in exposed datapath architectures with buffered processing units.	SAMOS	2017	DBLP DOI BibTeX RDF
17	Heikki O. Kultala, Pekka Jääskeläinen, Johannes IJzerman, Lasse Lehtonen, Timo Viitanen, Markku J. Mäkitalo, Jarmo H. Takala	Exposed datapath optimizations for loop scheduling.	SAMOS	2017	DBLP DOI BibTeX RDF
17	Anoop Bhagyanath, Klaus Schneider 0001	Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units.	ACSD	2017	DBLP DOI BibTeX RDF
17	Cunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski	Advanced datapath synthesis using graph isomorphism.	ICCAD	2017	DBLP DOI BibTeX RDF
17	Akshay Narayan 0001, Frank Cangialosi, Prateesh Goyal, Srinivas Narayana, Mohammad Alizadeh, Hari Balakrishnan	The Case for Moving Congestion Control Out of the Datapath.	HotNets	2017	DBLP DOI BibTeX RDF
17	Minas Dasygenis, Thanasis Karpouzis, Konstantinos Stergiou 0001	Template matching of a coarse grain reconfigurable architecture datapath using constraint programming.	PCI	2017	DBLP DOI BibTeX RDF
17	Zhongqi An, Zhengyu Zhang, Qiang Li, Jing Xing, Hao Du, Zhan Wang, Zhigang Huo, Jie Ma	Optimizing the Datapath for Key-value Middleware with NVMe SSDs over RDMA Interconnects.	CLUSTER	2017	DBLP DOI BibTeX RDF
17	Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang	Graph-Based Logic Bit Slicing for Datapath-Aware Placement.	DAC	2017	DBLP DOI BibTeX RDF
17	Weihua Zheng, Shenping Xiao, Kenli Li 0001, Keqin Li 0001, Weijin Jiang	A performance-efficient and datapath-regular implementation of modified split-radix fast Fourier transform.	J. Intell. Fuzzy Syst.	2016	DBLP DOI BibTeX RDF
17	Huawei Huang, Song Guo 0001, Jinsong Wu 0001, Jie Li 0002	Green DataPath for TCAM-Based Software-Defined Networks.	IEEE Commun. Mag.	2016	DBLP DOI BibTeX RDF
17	Junghoon Oh, Mineo Kaneko	Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2016	DBLP DOI BibTeX RDF
17	Alberto A. Del Barrio, Jason Cong, Román Hermida	A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
17	Deepak Kachave, Anirban Sengupta	Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors.	Microelectron. Reliab.	2016	DBLP DOI BibTeX RDF
17	Yu Yuan, Erdal Oruklu	Leakage reduction techniques for FinFET datapath circuits.	EIT	2016	DBLP DOI BibTeX RDF
17	Onur Kayiran, Adwait Jog, Ashutosh Pattnaik, Rachata Ausavarungnirun, Xulong Tang, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das	μC-States: Fine-grained GPU Datapath Power Management.	PACT	2016	DBLP DOI BibTeX RDF
17	Yifan He, Maurice Peemen, Luc Waeijen, Erkan Diken, Mattia Fiumara, Gerard K. Rauwerda, Henk Corporaal, Tong Geng	A configurable SIMD architecture with explicit datapath for intelligent learning.	SAMOS	2016	DBLP DOI BibTeX RDF
17	Anoop Bhagyanath, Klaus Schneider 0001	Optimal compilation for exposed datapath architectures with buffered processing units by SAT solvers.	MEMOCODE	2016	DBLP DOI BibTeX RDF
17	Junghoon Oh, Mineo Kaneko	Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components.	ISVLSI	2016	DBLP DOI BibTeX RDF
17	Michael Adriaansen, Mark Wijtvliet, Roel Jordans, Luc Waeijen, Henk Corporaal	Code Generation for Reconfigurable Explicit Datapath Architectures with LLVM.	DSD	2016	DBLP DOI BibTeX RDF
17	Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich	ReOrder: Runtime datapath generation for high-throughput multi-stream processing.	ReConFig	2016	DBLP DOI BibTeX RDF
17	Payman Behnam, Bijan Alizadeh, Sajjad Taheri, Masahiro Fujita	Formally analyzing fault tolerance in datapath designs using equivalence checking.	ASP-DAC	2016	DBLP DOI BibTeX RDF
17	Yuki Fukazawa, Keita Watanabe, Yuki Minoura, Toshio Kondo, Takahiro Sasaki	SIMD-based datapath with efficient operation structure for motion estimation.	ICASSP	2016	DBLP DOI BibTeX RDF
17	Joonas Multanen, Heikki Kultala, Matias Koskela, Timo Viitanen, Pekka Jääskeläinen, Jarmo Takala, Aram Danielyan, Cristóvão Cruz	OpenCL programmable exposed datapath high performance low-power image signal processor.	NORCAS	2016	DBLP DOI BibTeX RDF
17	Cunxi Yu, Maciej J. Ciesielski	Automatic word-level abstraction of datapath.	ISCAS	2016	DBLP DOI BibTeX RDF
17	Ayub Chin Abdullah, Chia Yee Ooi, Nordinah Bt Ismail, Nurita Binti Mohammad	Power-aware through-silicon-via minimization by partitioning finite state machine with datapath.	ISCAS	2016	DBLP DOI BibTeX RDF
17	Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran	Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications.	ICICDT	2016	DBLP DOI BibTeX RDF
17	V. R. Devanathan, Sumant Kale	A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath.	ITC	2016	DBLP DOI BibTeX RDF
17	Guang-Ming Tang	Studies on Datapath Circuits for Superconductor Bit-Slice Microprocessors.		2016	RDF
17	Anirban Sengupta, Saumya Bhadauria	Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis.	Expert Syst. Appl.	2015	DBLP DOI BibTeX RDF
17	Kan Shi, David Boland, George A. Constantinides	Imprecise Datapath Design: An Overclocking Approach.	ACM Trans. Reconfigurable Technol. Syst.	2015	DBLP DOI BibTeX RDF
17	Weihua Zheng, Kenli Li 0001, Keqin Li 0001	Datapath-regular implementation and scaled technique for N=3×2m DFTs.	Signal Process.	2015	DBLP DOI BibTeX RDF
17	Anirban Sengupta, Saumya Bhadauria	Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computing.	Adv. Eng. Softw.	2015	DBLP DOI BibTeX RDF
17	Saumya Bhadauria, Anirban Sengupta	Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis.	Appl. Math. Comput.	2015	DBLP DOI BibTeX RDF
17	Bijan Alizadeh, Payman Behnam, Somayeh Sadeghi Kohan	A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.	IEEE Trans. Computers	2015	DBLP DOI BibTeX RDF
17	Anirban Sengupta, Vipul Kumar Mishra	Simultaneous exploration of optimal datapath and loop based high level transformation during area-delay tradeoff in architectural synthesis using swarm intelligence.	Int. J. Knowl. Based Intell. Eng. Syst.	2015	DBLP DOI BibTeX RDF
17	Anirban Sengupta, Reza Sedaghat	Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget.	Microelectron. Reliab.	2015	DBLP DOI BibTeX RDF
17	Pekka Jääskeläinen, Heikki Kultala, Timo Viitanen, Jarmo Takala	Code Density and Energy Efficiency of Exposed Datapath Architectures.	J. Signal Process. Syst.	2015	DBLP DOI BibTeX RDF
17	Luc Waeijen, Dongrui She, Henk Corporaal, Yifan He	A Low-Energy Wide SIMD Architecture with Explicit Datapath.	J. Signal Process. Syst.	2015	DBLP DOI BibTeX RDF
17	Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos	Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures.	ARC	2015	DBLP DOI BibTeX RDF