Search results for "glitch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Cristiano Forzan, Davide Pandini	A complete methodology for an accurate static noise analysis.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	noise propagation, crosstalk, signal integrity
14	Sachin Shrivastava, Sreeram Chandrasekar	Crosstalk Noise Analysis at Multiple Frequencies.	VLSI Design	2005	DBLP DOI BibTeX RDF
14	B. S. Manoj 0001, Rajesh Mishra, Ramesh R. Rao	SEBAG: A New Dynamic End-to-End Connection Management Scheme for Multihomed Mobile Hosts.	IWDC	2005	DBLP DOI BibTeX RDF
14	Chun-Yueh Huang, Tsung-Tien Hou, Chi-Chieh Chuang, Hung-Yu Wang	Design of 12-bit 100-MHz Current-Steering DAC for SoC Applications.	IWSOC	2005	DBLP DOI BibTeX RDF
14	Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown	Incremental retiming for FPGA physical synthesis.	DAC	2005	DBLP DOI BibTeX RDF	FPGA, retiming, physical synthesis
14	Weisheng Chong, Masanori Hariyama, Michitaka Kameyama	Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits.	ISVLSI	2004	DBLP DOI BibTeX RDF
14	Katherine Shu-Min Li, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen	A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
14	Alireza Kasnavi, Joddy W. Wang, Mahmoud Shahram, Jindrich Zejda	Analytical modeling of crosstalk noise waveforms using Weibull function.	ICCAD	2004	DBLP DOI BibTeX RDF
14	Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda	Delay noise pessimism reduction by logic correlations.	ICCAD	2004	DBLP DOI BibTeX RDF
14	Michele Favalli	"Victim Gate" Crosstalk Fault Model.	DFT	2004	DBLP DOI BibTeX RDF
14	An Yu, David S. Brée	A Clock-less Implementation of the AES Resists to Power and Timing Attacks.	ITCC (2)	2004	DBLP DOI BibTeX RDF	clock-less circuits, AES, timing attacks, cryptosystems, power attacks
14	Sachin Shrivastava, Dhanoop Varghese, Vikas Narang, N. V. Arvind	Improved Approach for Noise Propagation to Identify Functional Noise Violations.	VLSI Design	2004	DBLP DOI BibTeX RDF
14	Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell	CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.	VLSI Design	2004	DBLP DOI BibTeX RDF
14	Fei Li 0003, Deming Chen, Lei He 0001, Jason Cong	Architecture evaluation for power-efficient FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA power model, low power design, FPGA architecture
14	Taku Uchino, Jason Cong	An interconnect energy model considering coupling effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
14	Alexey Glebov, Sergey Gavrilov, David T. Blaauw, Vladimir Zolotov	False-noise analysis using logic implications.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	circuit logic, VLSI (very large scale integration), noise analysis
14	Sung-Mo Kang	On-chip thermal engineering for peta-scale integration.	ISPD	2002	DBLP DOI BibTeX RDF
14	Xun Liu, Marios C. Papaefthymiou	Incorporation of input glitches into power macromodeling.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
14	Keliu Shu, Edgar Sánchez-Sinencio, José Silva-Martínez	A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
14	Hwang-Cherng Chow, I-Chyn Wey	A 3.3 V 1 GHz high speed pipelined Booth multiplier.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
14	Süleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale	Power analysis of multiplier blocks.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
14	Keliu Shu, Edgar Sánchez-Sinencio	A 5-GHz prescaler using improved phase switching.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
14	Yongsang Yoo, Minkyu Song	Design of a 1.8V 10bit 300MSPS CMOS digital-to-analog converter with a novel deglitching circuit and inverse thermometer decoder.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
14	Mark Vesterbacka, J. Jacob Wikner	Design of encoders for linear-coded D/A converters.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
14	Imed Ben Dhaou, N. Money, Hannu Tenhunen	Fast low-power characterization of arithmetic units in DSM CMOS.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
14	Nicholas Freitag McPhee, Riccardo Poli	A Schema Theory Analysis of the Evolution of Size in Genetic Programming with Linear Representations.	EuroGP	2001	DBLP DOI BibTeX RDF
14	Nikola Nedovic, Vojin G. Oklobdzija	Dynamic Flip-Flop with Improved Power.	ICCD	2000	DBLP DOI BibTeX RDF
14	Rita Mayer-Sommer	Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards.	CHES	2000	DBLP DOI BibTeX RDF
14	Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou	A structure-oriented power modeling technique for macrocells.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
14	Jack L. Chan, Steve S. Chung	Universal Switched-Current Integrator Blocks for SI Filter Design.	ASP-DAC	1999	DBLP DOI BibTeX RDF
14	Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao	Fault modeling and simulation for crosstalk in system-on-chip interconnects.	ICCAD	1999	DBLP DOI BibTeX RDF
14	Sven Simon 0001, Marek Wróblewski	Low power datapath design using transformation similar to temporal localization of SFGs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
14	Unni Narayanan, Peichen Pan, C. L. Liu 0001	Low power logic synthesis under a general delay model.	ISLPED	1998	DBLP DOI BibTeX RDF
14	Mark B. Josephs, Jelio Todorov Yantchev	CMOS design of the tree arbiter element.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF