Search results for "interconnect"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	Ayhan A. Mutlu, Jiayong Le, Ruben Molina, Mustafa Celik	Parametric analysis to determine accurate interconnect extraction corners for design performance.	ISQED	2009	DBLP DOI BibTeX RDF
27	Yan Lin 0001, Lei He 0001, Mike Hutton	Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
27	Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng 0001	Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
27	Shilpa Bhoj, Dinesh Bhatia	Early stage FPGA interconnect leakage power estimation.	ICCD	2008	DBLP DOI BibTeX RDF
27	Zhiyi Yu, Bevan M. Baas	A low-area interconnect architecture for chip multiprocessors.	ISCAS	2008	DBLP DOI BibTeX RDF
27	T. Venkata Kalyan, Madhu Mutyam, Vijaya Sankara Rao Pasupureddi	Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
27	Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
27	Xiaoji Ye, Frank Liu 0001, Peng Li 0001	Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
27	Jongsun Kim, Ingrid Verbauwhede, M.-C. Frank Chang	Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
27	Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu, Lei He	TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	Love Singhal, Elaheh Bozorgzadeh, David Eppstein	Interconnect Criticality-Driven Delay Relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	Yan Lin 0001, Lei He 0001	Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, uncertainty, process variation, stochastic, physical synthesis
27	Yan Lin 0001, Lei He 0001	Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.	DATE	2007	DBLP DOI BibTeX RDF
27	Brajesh Kumar Kaushik, Sankar Sarkar, Rajendra Prasad Agarwal, Ramesh C. Joshi	Crosstalk Analysis of an Inductively and Capacitively Coupled Interconnect Driven by a CMOS Gate.	ICIT	2007	DBLP DOI BibTeX RDF
27	Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud	Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect.	ASP-DAC	2007	DBLP DOI BibTeX RDF
27	Shilpa Bhoj, Dinesh Bhatia	Pre-route Interconnect Capacitance and Power Estimation in FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
27	Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri	A methodology for interconnect dimension determination.	ISPD	2007	DBLP DOI BibTeX RDF
27	Taemin Kim, Xun Liu	Compatibility path based binding algorithm for interconnect reduction in high level synthesis.	ICCAD	2007	DBLP DOI BibTeX RDF
27	Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl	IntSim: A CAD tool for optimization of multilevel interconnect networks.	ICCAD	2007	DBLP DOI BibTeX RDF
27	Boyan Semerdjiev, Dimitrios Velenis	Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Boyan Semerdjiev, Dimitrios Velenis	Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees.	VLSI Design	2007	DBLP DOI BibTeX RDF
27	Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli	Early wire characterization for predictable network-on-chip global interconnects.	SLIP	2007	DBLP DOI BibTeX RDF	early wire characterization, design methodology, NoCs, global interconnects
27	Hoyeol Cho, Kyung-Hoae Koo, Pawan Kapur, Krishna Saraswat	Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects.	SLIP	2007	DBLP DOI BibTeX RDF	Cu, bandwidth density, power, latency, optics, carbon nanotube, Global interconnects
27	Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta	Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
27	James D. Ma, Rob A. Rutenbar	Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
27	Maurice Meijer, Rohini Krishnan, Martijn T. Bennebroek	Energy-efficient FPGA interconnect design.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
27	Florin Dumitrascu, Iuliana Bacivarov, Lorenzo Pieralisi, Marius Bonaciu, Ahmed Amine Jerraya	Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
27	Vishal Suthar, Shantanu Dutt	Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults.	DATE	2006	DBLP DOI BibTeX RDF
27	Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee 0001, Jwu E. Chen	IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults.	ASP-DAC	2006	DBLP DOI BibTeX RDF
27	Shweta Shah, Nazanin Mansouri, Adrián Núñez-Aldana	Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
27	Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh	Stable and compact inductance modeling of 3-D interconnect structures.	ICCAD	2006	DBLP DOI BibTeX RDF
27	Simon Hollis, Simon W. Moore	An area-efficient, pulse-based interconnect.	ISCAS	2006	DBLP DOI BibTeX RDF
27	Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal	Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	measurement, process variations, extraction, VLSI interconnects
27	Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande	NoC Interconnect Yield Improvement Using Crosspoint Redundancy.	DFT	2006	DBLP DOI BibTeX RDF
27	Narender Hanchate, Nagarajan Ranganathan	Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization.	ISQED	2006	DBLP DOI BibTeX RDF
27	Andrew B. Kahng, Kambiz Samadi, Puneet Sharma	Study of Floating Fill Impact on Interconnect Capacitance.	ISQED	2006	DBLP DOI BibTeX RDF
27	Praveen Ghanta, Sarma B. K. Vrudhula	Variational Interconnect Delay Metrics for Statistical Timing Analysis.	ISQED	2006	DBLP DOI BibTeX RDF
27	Uri Cummings	Ethernet interconnects - Low-latency ethernet: the ubiquitous datacenter interconnect.	SC	2006	DBLP DOI BibTeX RDF
27	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards	Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
27	Magdy A. El-Moursy, Eby G. Friedman	Shielding effect of on-chip interconnect inductance.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
27	Shankar Balachandran, Dinesh Bhatia	A priori wirelength and interconnect estimation based on circuit characteristic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
27	Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao	The Y architecture for on-chip interconnect: analysis and methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
27	Peng Li 0001, Frank Liu 0001, Xin Li 0001, Lawrence T. Pileggi, Sani R. Nassif	Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction.	DATE	2005	DBLP DOI BibTeX RDF
27	Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay	Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance.	DATE	2005	DBLP DOI BibTeX RDF
27	Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin	Leakage-Aware Interconnect for On-Chip Network.	DATE	2005	DBLP DOI BibTeX RDF
27	Rong Jiang 0002, Charlie Chung-Ping Chen	Comprehensive frequency dependent interconnect extraction and evaluation methodology.	ASP-DAC	2005	DBLP DOI BibTeX RDF
27	Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Virgilio Fernandez, Eby G. Friedman	Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
27	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	moment calculation, sources of variation, sensitivity, statistical timing analysis, elmore delay
27	Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda	Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture.	ISQED	2005	DBLP DOI BibTeX RDF
27	Chung-Kuan Tsai, Malgorzata Marek-Sadowska	An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis.	ISQED	2005	DBLP DOI BibTeX RDF
27	Haihua Yan, Adit D. Singh	A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects.	VLSI Design	2005	DBLP DOI BibTeX RDF
27	Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel	ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips.	VLSI Design	2005	DBLP DOI BibTeX RDF
27	Magdy A. El-Moursy, Eby G. Friedman	Power characteristics of inductive interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
27	Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek	Low energy FPGA interconnect design.	FPGA	2004	DBLP DOI BibTeX RDF
27	Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi	An Interconnect Channel Design Methodology for High Performance Integrated Circuits.	DATE	2004	DBLP DOI BibTeX RDF
27	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Representative frequency for interconnect R(f)L(f)C extraction.	ASP-DAC	2004	DBLP DOI BibTeX RDF
27	Aristides Efthymiou, John Bainbridge, Douglas A. Edwards	Adding Testability to an Asynchronous Interconnect for GALS SoC.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
27	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	BFT, scalability, pipelining, bus, MP-SoC
27	Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel	Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model.	DFT	2004	DBLP DOI BibTeX RDF
27	Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Frank Liu 0001, Sani R. Nassif, Sarma B. K. Vrudhula	Variational delay metrics for interconnect timing analysis.	DAC	2004	DBLP DOI BibTeX RDF	Performance, Design
27	Beng Hwee Ong, Choon Beng Sia, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li	Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling.	SLIP	2004	DBLP DOI BibTeX RDF	distributed effects, frequency dependence elements, physical model, skin effects
27	Ruibing Lu, Cheng-Kok Koh	Interconnect Planning with Local Area Constrained Retiming.	DATE	2003	DBLP DOI BibTeX RDF
27	Weiping Liao, Lei He 0001	Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion.	ICCAD	2003	DBLP DOI BibTeX RDF
27	Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao 0001, Rajendran Panda, Sachin S. Sapatnekar	Table look-up based compact modeling for on-chip interconnect timing and noise analysis.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
27	Sambuddha Bhattacharya, C.-J. Richard Shi	Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
27	Pranav Anbalagan, Jeffrey A. Davis	Maximum multiplicity distributions (MMD).	SLIP	2003	DBLP DOI BibTeX RDF	system-level prediction, wire-length distributions, simulated annealing
27	Taku Uchino, Jason Cong	An interconnect energy model considering coupling effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
27	George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson 0001	Point to Point GALS Interconnect.	ASYNC	2002	DBLP DOI BibTeX RDF
27	Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham	Balancing the Interconnect Topology for Arrays of Processors between Cost and Power.	ICCD	2002	DBLP DOI BibTeX RDF
27	Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita	On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.	ITC	2002	DBLP DOI BibTeX RDF
27	Ilkka Saastamoinen, David A. Sigüenza-Tortosa, Jari Nurmi	Interconnect IP Node for Future System-on-Chip Designs.	DELTA	2002	DBLP DOI BibTeX RDF	System-on-Chip, reuse, on-chip communication, packet network
27	Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl	Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI).	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
27	Jason Cong, Tianming Kong, Z. D. Pan	Buffer block planning for interconnect planning and prediction.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
27	Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay	Interconnect synthesis without wire tapering.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
27	Daniel Eckerbert, Per Larsson-Edefors	Interconnect-Driven Short-Circuit Power Modeling.	DSD	2001	DBLP DOI BibTeX RDF
27	Jason Cong, David Zhigang Pan, Prasanna V. Srinivas	Improved crosstalk modeling for noise constrained interconnect optimization.	ASP-DAC	2001	DBLP DOI BibTeX RDF
27	Shail Aditya, Michael S. Schlansker	ShiftQ: a bufferred interconnect for custom loop accelerators.	CASES	2001	DBLP DOI BibTeX RDF
27	Alexander V. Shafarenko, Vladimir Vasekin	An Adaptive, Reconfigurable Interconnect for Computational Clusters.	CCGRID	2001	DBLP DOI BibTeX RDF
27	Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John Marty Emmert	On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs.	IOLTW	2001	DBLP DOI BibTeX RDF
27	Kenneth Rose	A comprehensive look at system level model.	SLIP	2001	DBLP DOI BibTeX RDF
27	Li-Fu Chang, Keh-Jeng Chang, Christophe J. Bianchi	A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect Impedance.	ISQED	2000	DBLP DOI BibTeX RDF
27	Haluk Konuk	Voltage- and current-based fault simulation for interconnect open defects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
27	Yiqun Lin, Robert Lomenick, Rex Lowther, Wenhua Ni, Widad Rafie-Hibner, Orlando Ruiz, Jim Furino	Interconnect model generation tool.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
27	Pradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh	Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization.	VLSI Design	1999	DBLP DOI BibTeX RDF
27	M. B. Anand, Hideki Shibata, Masakazu Kakumu	Multiobjective optimization of VLSI interconnect parameters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
27	Jason Cong, Lei He 0001	An efficient technique for device and interconnect optimization in deep submicron designs.	ISPD	1998	DBLP DOI BibTeX RDF
27	Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic	Minimizing FPGA Interconnect Delays.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
27	Lawrence T. Pileggi	Coping with RC(L) interconnect design headaches.	ICCAD	1995	DBLP DOI BibTeX RDF
27	Andreas Nowatzyk, Paul R. Prucnal	Are Crossbars Really Dead? The Case for Optical Multiprocessor Interconnect Systems.	ISCA	1995	DBLP DOI BibTeX RDF
27	Demos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage	Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
27	Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage	RC interconnect synthesis-a moment fitting approach.	ICCAD	1994	DBLP DOI BibTeX RDF
27	Christos A. Papachristou, Haluk Konuk	A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm.	DAC	1990	DBLP DOI BibTeX RDF
27	Norman S. Matloff, Stephen Kowel, Charles Eldering	Optimul: An optional interconnect for multiprocessor systems.	ICS	1988	DBLP DOI BibTeX RDF
27	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Timing-aware power-optimal ordering of signals.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Wire ordering, wire spacing, power optimization, interconnect optimization
27	Sansiri Tanachutiwat, Wei Wang 0003	Exploring Multi-layer Graphene Nanoribbon Interconnects.	NanoNet	2008	DBLP DOI BibTeX RDF	Graphene, Modeling, Interconnect, Conductance
27	N. Venkateswaran 0002, S. Balaji, V. Sridhar	Fault tolerant bus architecture for deep submicron based processors.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF	deep submicron technology, fault tolerance, interconnect, electromigration
27	Eun Jung Kim 0001, Greg M. Link, Ki Hwan Yum, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Chita R. Das	A Holistic Approach to Designing Energy-Efficient Cluster Interconnects.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Buffer design, cluster interconnect, dynamic link shutdown, link design, dynamic voltage scaling, energy optimization, switch design
27	M. A. Sarwar, Alan D. George, David E. Collins	Reliability Modeling of SCI Ring-Based Topologies.	LCN	2000	DBLP DOI BibTeX RDF	SCI ring-based topologies, cluster interconnects, point-to-point ring-based interconnect, switched ring topologies, 1D k-ary n-cube switching fabrics, 2D k-ary n-cube switching fabrics, UltraSAN, single-ring system, redundant ring, fault tolerance, Petri nets, multiprocessor interconnection networks, network topology, reliability modeling, link failures, system buses, multiprocessor interconnects, scalable coherent interface
27	W. Stephen Lacy, José Cruz-Rivera, D. Scott Wills	The Offset Cube: A Three-Dimensional Multicomputer Network Topology Using Through-Wafer Optics.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	MPP networks, ultra-compact systems, offset cube, 3D packaging, through-wafer signaling, adaptive routing, optical interconnect, deadlock freedom, 3D mesh
26	Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou 0001	Optimizing wirelength and routability by searching alternative packings in floorplanning.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	wirelength reduction, Floorplanning