Search results for "manufacturability"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Michel Côté, Philippe Hurat	Standard Cell Printability Grading and Hot Spot Detection.	ISQED	2005	DBLP DOI BibTeX RDF
12	Manish Garg, Laurent Le Cam, Matthieu Gonzalez	Lithography Driven Layout Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
12	Artur Balasinski	DfM for SoC, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
12	Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak	Flexible ASIC: shared masking for multiple media processors.	DAC	2005	DBLP DOI BibTeX RDF	optimization, interconnect, ASIC
12	Li-Da Huang, Xiaoping Tang, Hua Xiang 0001, Martin D. F. Wong, I-Min Liu	A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
12	Maria Luisa Garcia-Romeu, Quim de Ciurana	Design and Manufacturing Assistance Tool for Drawing Sheet Metal Parts.	CDVE	2004	DBLP DOI BibTeX RDF	Concurrent Engineering Tools, Manufacturing Design, sheet metal processes, computer manufacturing, DSS
12	Monica Donno, Enrico Macii, Luca Mazzoni	Power-aware clock tree planning.	ISPD	2004	DBLP DOI BibTeX RDF	clock tree synthesis and routing, physical design and optimization, low-power design, digital design
12	Yong Zhao, Cheng Zhao, Jianzhong Cha	An Intelligent Design Method of Product Scheme Innovation.	WSC	2004	DBLP DOI BibTeX RDF
12	Tim Fühner, Andreas Erdmann, Richárd Farkas, Bernd Tollkühn, Gabriella Kókai	Genetic Algorithms to Improve Mask and Illumination Geometries in Lithographic Imaging Systems.	EvoWorkshops	2004	DBLP DOI BibTeX RDF
12	Mark A. Lavin, Fook-Luen Heng, Gregory A. Northrop	Backend CAD flows for "restrictive design rules".	ICCAD	2004	DBLP DOI BibTeX RDF
12	Sani R. Nassif, Duane S. Boning, Nagib Hakim	The care and feeding of your statistical static timer.	ICCAD	2004	DBLP DOI BibTeX RDF
12	Sani R. Nassif	The impact of variability on power.	ISLPED	2004	DBLP DOI BibTeX RDF	power, variability, integrated circuit
12	Jaeho Lee 0004, Joon Young Park, Deok-Soo Kim, Hyun-Chan Lee	Polyhedron Splitting Algorithm for 3D Layer Generation.	ICCSA (2)	2004	DBLP DOI BibTeX RDF
12	Yu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu	Failure Factor Based Yield Enhancement for SRAM Designs.	DFT	2004	DBLP DOI BibTeX RDF
12	Michel Côté, Philippe Hurat	Layout Printability Optimization Using a Silicon Simulation Methodology.	ISQED	2004	DBLP DOI BibTeX RDF
12	Charles Njinda	A Hierarchical DFT Architecture for Chip, Board and System Test/Debug.	ITC	2004	DBLP DOI BibTeX RDF
12	Hans T. Heineken, Jitendra Khare	Test Strategies For a 40Gbps Framer SoC.	ITC	2004	DBLP DOI BibTeX RDF
12	Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif	Optimal shielding/spacing metrics for low power design.	ISVLSI	2003	DBLP DOI BibTeX RDF
12	Martin Schrader, Roderick McConnell	SoC Design and Test Considerations.	DATE	2003	DBLP DOI BibTeX RDF
12	Yu Chen 0005, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky, Yuhong Zheng	Area Fill Generation With Inherent Data Volume Reduction.	DATE	2003	DBLP DOI BibTeX RDF
12	Yervant Zorian	Leveraging Infrastructure IP for SoC Yield.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
12	Hyung Rim Choi, Byung Joo Park, Hyun Soo Kim, Yong-Sung Park, Young Jae Park	Multi-Agent based negotiation support systems for order based manufacturers.	ICEC	2003	DBLP DOI BibTeX RDF	scheduling and sales engineer, intelligent agents, negotiation, multi-agent, virtual manufacturing
12	Puneet Gupta 0001, Andrew B. Kahng	Manufacturing-Aware Physical Design.	ICCAD	2003	DBLP DOI BibTeX RDF
12	Yu Chen 0005, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky	Area fill synthesis for uniform layout density.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
12	Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong	Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
12	Li-Da Huang, Xiaoping Tang, Hua Xiang 0001, D. F. Wong 0001, I-Min Liu	A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem.	DATE	2002	DBLP DOI BibTeX RDF
12	Mark Fiala, Anup Basu	Panoramic Stereo Reconstruction Using Non-SVP Optics.	ICPR (4)	2002	DBLP DOI BibTeX RDF
12	Daniel N. Maynard	Productivity Optimization Techniques for the Proactive Semiconductor Manufacturer (invited).	ISQED	2002	DBLP DOI BibTeX RDF	Modeling, Productivity, Design for Manufacturing (DFM), Characterization, Checking
12	Eric Dupont, Michael Nicolaidis	Robustness IPs for Reliability and Security of SoCs.	ITC	2002	DBLP DOI BibTeX RDF
12	Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji	Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
12	Yervant Zorian	Embedding infrastructure IP for SOC yield improvement.	DAC	2002	DBLP DOI BibTeX RDF	embedded test & repair, semiconductor IP, yield optimization, test resource partitioning
12	Krzysztof S. Berezowski	Transistor Chainning with Integrated Dynamic Folding for 1-D Leaf Cell Synthesis.	DSD	2001	DBLP DOI BibTeX RDF
12	Martin R. Frerichs	Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling: invited talk.	ASP-DAC	2001	DBLP DOI BibTeX RDF
12	Yu Chen 0005, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky	Hierarchical dummy fill for process uniformity.	ASP-DAC	2001	DBLP DOI BibTeX RDF
12	Andreas Lechner, Andrew Richardson 0001, B. Hermes	Short Circuit Faults in State-of-the-Art ADCs - Are They Hard or Soft?	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
12	Ruiqi Tian, Xiaoping Tang, D. F. Wong 0001	Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process.	ISPD	2001	DBLP DOI BibTeX RDF
12	Carmen M. Pancerella, James D. Myers, Christine L. Yang, Deborah K. Gracio	Collaborative Problem Solving Environments - Minitrack Introduction.	HICSS	2001	DBLP DOI BibTeX RDF
12	Mykola Blyzniuk, Irena Kazymyra	Development of the Special Software Tools for the Defect/Fault Analysis in the Complex Gates from Standard Cell Library.	DFT	2001	DBLP DOI BibTeX RDF	Test Vector Components, Software Tool, VLSI Circuit, Spot Defect, Fault Identification, Complex Gate
12	Neil Harrison	A Simple via Duplication Tool for Yield Enhancement.	DFT	2001	DBLP DOI BibTeX RDF
12	Kees Veelenturf	The Road to Better Reliability and Yield Embedded DfM Tools.	DATE	2000	DBLP DOI BibTeX RDF	wire spreading, yield prediction, yield improvement, DfM
12	Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty	Transformational Placement and Synthesis.	DATE	2000	DBLP DOI BibTeX RDF
12	Yervant Zorian	Yield Improvement and Repair Trade-Off for Large Embedded Memories.	DATE	2000	DBLP DOI BibTeX RDF	silicon repair, BIST, DFM, Yield improvement
12	Wieslaw Kuzmicz	Internet-Based Virtual Manufacturing: A Verification Tool for IC Designs.	ISQED	2000	DBLP DOI BibTeX RDF	analog IC design, statistical simulation, virtual manufacturing
12	Betty Prince	Quality Memory Blocks -- Balancing the Trade-Offs.	ISQED	2000	DBLP DOI BibTeX RDF
12	Mark E. Dean	Trends in Computing.	FMCAD	2000	DBLP DOI BibTeX RDF
12	Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky	Filling algorithms and analyses for layout density control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
12	Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno	Computing in Memory Architectures for Digital Image Processing.	MTDT	1999	DBLP DOI BibTeX RDF
12	Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey	Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
12	Jian Li 0061, Rajesh K. Gupta 0001	An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions.	DATE	1998	DBLP DOI BibTeX RDF
12	Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma	Interconnect Tuning Strategies for High-Performance Ics.	DATE	1998	DBLP DOI BibTeX RDF
12	Andrew B. Kahng, Gabriel Robins, Anish Singh, Huijuan Wang, Alexander Zelikovsky	Filling and slotting: analysis and algorithms.	ISPD	1998	DBLP DOI BibTeX RDF
12	Stuart K. Tewksbury, Lawrence A. Hornak	Optical Clock Distribution in Electronic Systems.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
12	Howard D. Owens, Baxter F. Womack, Mario J. Gonzalez	Software Error Classification using Purify.	ICSM	1996	DBLP DOI BibTeX RDF	Purify, maintenance, detection, Defects
12	Roni Yagel, Shao-Chiung Lu, Alec B. Rebello, Richard Allen Miller	Volume-Based Reasoning and Visualization of Diecastability.	IEEE Visualization	1995	DBLP DOI BibTeX RDF
12	Joo Y. Jung, Samir B. Billatos	An expert system for assembly based on Axiomatic Design principles.	J. Intell. Robotic Syst.	1993	DBLP DOI BibTeX RDF	Axiomatic design, design for assembly, expert systems, knowledge base
12	Raghu Karinthi, Dana S. Nau	An Algebraic Approach to Feature Interactions.	IEEE Trans. Pattern Anal. Mach. Intell.	1992	DBLP DOI BibTeX RDF	geometric interactions, Protosolid solid modeling system, EFHA process planning system, solid modelling, algebra, spatial reasoning, spatial reasoning, feature interactions, CAD/CAM, CAD/CAM, geometric reasoning, algebraic approach, CAD systems
12	Dennis L. Young, Jim Teplik, Harrison D. Weed, Neil T. Tracht, Antonio R. Alvarez	Application of statistical design and response surface methods to computer-aided VLSI device design II. Desirability functions and Taguchi methods.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
12	I. C. You, Chong-Nam Chu, Rangasami L. Kashyap	Symbolic representation of three-dimensional objects to aid local and global shape analysis for defect prediction of casting design.	Appl. Intell.	1991	DBLP DOI BibTeX RDF	Casting design, pattern model, feature, skeleton extraction
12	I. C. You, Chong-Nam Chu, Rangasami L. Kashyap	Knowledge Representation and Control Structure Based on Three-Dimensional Symbolic Skeletons for CAD/CAM Integration.	IEA/AIE (Vol. 1)	1990	DBLP DOI BibTeX RDF
12	Osama K. Eyada, Yiannakis A. Ioannou, Jin B. Ong	An interactive tolerance system.	IEA/AIE (1)	1989	DBLP DOI BibTeX RDF	C
12	Antonio R. Alvarez, Behrooz L. Abdi, Dennis L. Young, Harrison D. Weed, Jim Teplik, Eric R. Herald	Application of statistical design and response surface methods to computer-aided VLSI device design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
12	Robin L. Steele	An Expert System Application in Semicustom VLSI Design.	DAC	1987	DBLP DOI BibTeX RDF