Search results for "retargetable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Lennart Augustsson, Howard Mansell, Ganesh Sittampalam	Paradise: a two-stage DSL embedded in Haskell.	ICFP	2008	DBLP DOI BibTeX RDF	dsels, paradise, Haskell, metaprogramming
12	Carlo Galuzzi, Koen Bertels	A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures.	ARC	2008	DBLP DOI BibTeX RDF
12	Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi	Compiling custom instructions onto expression-grained reconfigurable architectures.	CASES	2008	DBLP DOI BibTeX RDF	horizontal microprogramming, compilers, instruction set extensions, coarse-grained reconfigurable architectures, data-flow architectures
12	Haibing Guan, Bo Liu 0001, Tingtao Li, Alei Liang	Multithreaded Optimizing Technique for Dynamic Binary Translator CrossBit.	CSSE (5)	2008	DBLP DOI BibTeX RDF
12	Congying Han, Guoping He, Hua Duan, Xuping Zhang	A Binding Number Computation of Graph.	FSKD (4)	2008	DBLP DOI BibTeX RDF
12	Zhonglei Wang, Antonio Sánchez, Andreas Herkersdorf	SciSim: a software performance estimation framework using source code instrumentation.	WOSP	2008	DBLP DOI BibTeX RDF	debugging information, software performance estimation, source code instrumentation, microarchitecture
12	Praveen Raghavan, Andy Lambrechts, Javed Absar, Murali Jayapala, Francky Catthoor, Diederik Verkest	Coffee: COmpiler Framework for Energy-Aware Exploration.	HiPEAC	2008	DBLP DOI BibTeX RDF
12	Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee	An Overview of a Compiler for Mapping Software Binaries to Hardware.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
12	Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek	Automatic Design Space Exploration of Register Bypasses in Embedded Processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
12	Paul Curzon, Rimvydas Ruksenas, Ann Blandford	An approach to formal verification of human-computer interaction.	Formal Aspects Comput.	2007	DBLP DOI BibTeX RDF	Formal cognitive architecture, Formal verification, Theorem proving, Interactive systems, Human error
12	Ning Qu, Yulai Zhao 0003, Xuetao Guan, Xu Cheng 0001	Unichos: a full system simulator for thin client platform.	SAC	2007	DBLP DOI BibTeX RDF	performance evaluation, computer architecture, thin client, full system simulation
12	Torsten Grust, Manuel Mayr, Jan Rittinger, Sherif Sakr, Jens Teubner	A SQL: 1999 code generator for the pathfinder xquery compiler.	SIGMOD Conference	2007	DBLP DOI BibTeX RDF	relational databases, SQL, XQuery, relational algebra
12	Carlos Morra, João M. P. Cardoso, Jürgen Becker 0001	Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements.	IPDPS	2007	DBLP DOI BibTeX RDF
12	Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	HySim: a fast simulation framework for embedded software development.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	HySim, ISS, simulation, hybrid simulation
12	Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr	A code-generator generator for multi-output instructions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	ISS, code-selection, compiler/architecture co-design, ASIP
12	Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A fast and generic hybrid simulation approach using C virtual machine.	CASES	2007	DBLP DOI BibTeX RDF	simulation, virtual machine, debugging
12	Grigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis	A unified evaluation framework for coarse grained reconfigurable array architectures.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	coarse-grained reconfigurable arrays, reconfigurable romputing, Modulo scheduling, architectural exploration
12	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration for coarse grained reconfigurable arrays.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	coarse-grained reconfigurable arrays, reconfigurable computing, modulo scheduling, architectural exploration
12	Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner	Effective compiler generation by architecture description.	LCTES	2006	DBLP DOI BibTeX RDF	code generation, architecture description language, compiler generation
12	Takashi Nakada, Tomoaki Tsumura, Hiroshi Nakashima	Design and Implementation of aWorkload Specific Simulator.	Annual Simulation Symposium	2006	DBLP DOI BibTeX RDF
12	Koen Van Renterghem, Dieter Verhulst, S. Verschuere, Pieter Demuytere, Jan Vandewege, Xing-Zhi Qiu	A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access.	FPL	2006	DBLP DOI BibTeX RDF
12	Andrzej Bednarski, Christoph W. Kessler	Optimal Integrated VLIW Code Generation with Integer Linear Programming.	Euro-Par	2006	DBLP DOI BibTeX RDF
12	Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki J. Murakami	REDEFIS: a system with a redefinable instruction set processor.	SBCCI	2006	DBLP DOI BibTeX RDF	ISA customization, dynamically reconfigurable processor, low power, SoC, high performance
12	Nikolaos Kavvadias, Spiridon Nikolaidis 0001	A portable specification of zero-overhead looping control hardware applied to embedded processors.	ISCAS	2006	DBLP DOI BibTeX RDF
12	Rajeev Kumar 0004, Amit Gupta, B. S. Pankaj, Mrinmoy Ghosh, P. P. Chakrabarti 0001	Post-compilation optimization for multiple gains with pattern matching.	ACM SIGPLAN Notices	2005	DBLP DOI BibTeX RDF	instruction set FSM, peephole optimization, post-compilation optimization, pattern matching
12	Bingfeng Mei, Andy Lambrechts, Diederik Verkest, Jean-Yves Mignolet, Rudy Lauwereins	Architecture Exploration for a Reconfigurable Architecture Template.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF
12	Wei Qin, Sharad Malik	A Study of Architecture Description Languages from a Model-based Perspective.	MTV	2005	DBLP DOI BibTeX RDF
12	Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Daniele Bagni	Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications.	DATE	2005	DBLP DOI BibTeX RDF
12	Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie	PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors.	DATE	2005	DBLP DOI BibTeX RDF
12	Jason McC. Smith, P. David Stotts	Extending SPQR to Architectural Analysis by Semi-Automated Training.	WICSA	2005	DBLP DOI BibTeX RDF
12	Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti	A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems.	ASP-DAC	2005	DBLP DOI BibTeX RDF
12	Daniel Kästner, Markus Pister 0002	Generic Software Pipelining at the Assembly Level.	SCOPES	2005	DBLP DOI BibTeX RDF	PROPAN, software pipelining, modulo scheduling, postpass optimization
12	Claudio Mucci, Fabio Campi, Antonio Deledda, Alberto Fazzi, Mirco Ferri, Massimo Bocchi	A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture.	IPDPS	2005	DBLP DOI BibTeX RDF
12	Masaharu Imai, Akira Kitajima	Verification Challenges in Configurable Processor Design with ASIP Meister.	CHARME	2005	DBLP DOI BibTeX RDF
12	David Garlan, William K. Reinholtz, Bradley R. Schmerl, Nicholas D. Sherman, Tony Tseng	Bridging the Gap between Systems Design.	SEW	2005	DBLP DOI BibTeX RDF
12	Ali Erdem Özcan, Sébastien Jean, Jean-Bernard Stefani	Bringing Ease and Adaptability to MPSoC Software Design: A Component-Based Approach.	CASSIS	2005	DBLP DOI BibTeX RDF
12	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
12	Gabriele Luculli	Efficient and Effective Simulation of Memory Maps for System-on-Chip.	ECBS	2004	DBLP DOI BibTeX RDF
12	Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Raimundo S. Barreto, Fernando F. Carvalho	Towards a Software Power Cost Analysis Framework Using Colored Petri Net.	PATMOS	2004	DBLP DOI BibTeX RDF
12	Ankush Varma, Shuvra S. Bhattacharyya	Java-through-C Compilation: An Enabling Technology for Java in Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF
12	Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh	Instruction Selection for Compilers that Target Architectures with Echo Instructions.	SCOPES	2004	DBLP DOI BibTeX RDF
12	Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek	Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration.	FPL	2004	DBLP DOI BibTeX RDF
12	Marcus Bartholomeu, Rodolfo Azevedo, Sandro Rigo, Guido Araujo	Optimizations for Compiled Simulation Using Instruction Type Information.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
12	Gary Gréwal, Thomas Charles Wilson, Andrew Morton	An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF
12	Huanfeng Ma, David S. Doermann	Adaptive Hindi OCR using generalized Hausdorff image comparison.	ACM Trans. Asian Lang. Inf. Process.	2003	DBLP DOI BibTeX RDF	generalized Hausdorff image comparison, Optical character recognition (OCR), document processing, script identification
12	Rafael Ballagas, Meredith Ringel, Maureen C. Stone, Jan O. Borchers	iStuff: a physical user interface toolkit for ubiquitous computing environments.	CHI	2003	DBLP DOI BibTeX RDF	ubiquitous computing, tangible user interfaces, programming environments, development tools, user interface toolkits, input and interaction technologies, wireless devices, intermediation
12	Cristian Coarfa, Yuri Dotsenko, Jason Eckhardt, John M. Mellor-Crummey	Co-array Fortran Performance and Potential: An NPB Experimental Study.	LCPC	2003	DBLP DOI BibTeX RDF
12	Rainer Leupers	Compiler Design Issues for Embedded Processors.	IEEE Des. Test Comput.	2002	DBLP DOI BibTeX RDF
12	Todd A. Proebsting	BURG, IBURG, WBURG, GBURG: so many trees to rewrite, so little time (invited talk).	ACM SIGPLAN Workshop on Rule-Based Programming	2002	DBLP DOI BibTeX RDF
12	Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek	Improving Code Efficiency for Reconfigurable VLIW Processors.	IPDPS	2002	DBLP DOI BibTeX RDF
12	Domenico Barretta, William Fornaciari, Mariagiovanna Sami, Danilo Pau	SIMD Extension to VLIW Multicluster Processors for Embedded Applications.	ICCD	2002	DBLP DOI BibTeX RDF
12	Yung-Chia Lin, Yuan-Shin Hwang, Jenq Kuen Lee	Compiler Optimizations with DSP-Specific Semantic Descriptions.	LCPC	2002	DBLP DOI BibTeX RDF
12	Ahmed E. Hassan, Richard C. Holt	Architecture recovery of web applications.	ICSE	2002	DBLP DOI BibTeX RDF
12	Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann 0002	A universal technique for fast and flexible instruction-set architecture simulation.	DAC	2002	DBLP DOI BibTeX RDF
12	Andreas Hoffmann 0002, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr	A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
12	Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith	Exploring Hypermedia Processor Design Space.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	hypermedia processor, synthesis framework, instruction-level parallelism, workload characterization
12	Thomas A. Henzinger, Benjamin Horowitz, Christoph M. Kirsch	Embedded Control Systems Development with Giotto.	LCTES/OM	2001	DBLP DOI BibTeX RDF
12	Christoph W. Keßler, Andrzej Bednarski	A Dynamic Programming Approach to Optimal Integrated Code Generation.	LCTES/OM	2001	DBLP DOI BibTeX RDF	integrated code generation, time profile, dynamic programming, register allocation, instruction scheduling, instruction selection
12	Mahmut T. Kandemir, Ismail Kadayif	Compiler-directed selection of dynamic memory layouts.	CODES	2001	DBLP DOI BibTeX RDF	array reuse, memory layout optimization, software compilation, data dependence, data locality
12	Edward Lank, Jeb S. Thorley, Sean Chen, Dorothea Blostein	On-Line Recognition of UML Diagrams.	ICDAR	2001	DBLP DOI BibTeX RDF
12	Margarida F. Jacome, Gustavo de Veciana	Design Challenges for New Application-Specific Processors.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
12	Stefan Pees, Andreas Hoffmann 0002, Heinrich Meyr	Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language.	DATE	2000	DBLP DOI BibTeX RDF
12	Frank Engel, Johannes Nührenberg, Gerhard P. Fettweis	A generic tool set for application specific processor architectures.	CODES	2000	DBLP DOI BibTeX RDF
12	Naji Ghazal, A. Richard Newton, Jan M. Rabaey	Predicting performance potential of modern DSPs.	DAC	2000	DBLP DOI BibTeX RDF
12	Edward Lank, Jeb S. Thorley, Sean Jy-Shyang Chen	An interactive system for recognizing hand drawn UML diagrams.	CASCON	2000	DBLP BibTeX RDF	UML
12	Ashok Halambi, Peter Grun, Vijay Ganesh, Asheesh Khare, Nikil D. Dutt, Alexandru Nicolau	EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability.	DATE	1999	DBLP DOI BibTeX RDF
12	Rainer Leupers, Johann Elste, Birger Landwehr	Generation of Interpretive and Compiled Instruction Set Simulators.	ASP-DAC	1999	DBLP DOI BibTeX RDF
12	Jeffrey L. Korn, Yih-Farn Chen, Eleftherios Koutsofios	Chava: Reverse Engineering and Tracking of Java Applets.	WCRE	1999	DBLP DOI BibTeX RDF
12	Esther Stümpel, Michael Thies, Uwe Kastens	VLIW Compilation Techniques for Superscalar Architectures.	CC	1998	DBLP DOI BibTeX RDF
12	Takashi Miyamori, Kunle Olukotun	A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications.	FCCM	1998	DBLP DOI BibTeX RDF
12	Andrew A. Duncan, David C. Hendry, Peter Gray	An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems.	FCCM	1998	DBLP DOI BibTeX RDF
12	Pai H. Chou, Gaetano Borriello	Modal Processes: Towards Enhanced Retargetability Through Control Composition of Distributed Embedded Systems.	DAC	1998	DBLP DOI BibTeX RDF
12	Christian S. Collberg	Reverse Interpretation + Mutation Analysis = Automatic Retargeting.	PLDI	1997	DBLP DOI BibTeX RDF	C
12	Mark R. Hartoog, James A. Rowson, Prakash D. Reddy, Soumya Desai, Douglas D. Dunlop, Edwin A. Harcourt, Neeti Khullar	Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign.	DAC	1997	DBLP DOI BibTeX RDF
12	George Hadjiyiannis, Silvina Hanono, Srinivas Devadas	ISDL: An Instruction Set Description Language for Retargetability.	DAC	1997	DBLP DOI BibTeX RDF
12	Clifford Liem, Marco Cornero, Miguel Santana, Pierre G. Paulin, Ahmed Amine Jerraya, Jean-Marc Gentit, Jean Lopez, Xavier Figari, Laurent Bergher	Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor.	DAC	1997	DBLP DOI BibTeX RDF
12	Preston Briggs	Remembering.	ACM SIGPLAN Notices	1996	DBLP DOI BibTeX RDF
12	Peter Pfahler, Georg Piepenbrock	A Comparison of Modulo Scheduling Techniques for Software Pipelining.	CC	1996	DBLP DOI BibTeX RDF	Instruction Level Parallelism, Software Pipelining, VLIW, Superscalar Processors
12	Guido Araujo, Ashok Sudarsanam, Sharad Malik	Instruction Set Design and Optimizations for Address Computation in DSP Architectures.	ISSS	1996	DBLP DOI BibTeX RDF
12	Norman Ramsey	Relocating Machine Instructions by Currying.	PLDI	1996	DBLP DOI BibTeX RDF
12	Jörg Wilberg, A. Kuth, Raul Camposano, Wolfgang Rosenstiel, Heinrich Theodor Vierhaus	A Design Exploration Environment.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
12	J. Shu, Thomas Charles Wilson, Dilip K. Banerji	Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation.	VLSI Design	1996	DBLP DOI BibTeX RDF
12	Gert Goossens, Dirk Lanneer, Marc Pauwels, Francis Depuydt, Koen Schoofs, Augusli Kifli, Marco Cornero, Paolo Petroni, Francky Catthoor, Hugo De Man	Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
12	Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala	DSP design tool requirements for embedded systems: A telecommunications industrial perspective.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
12	Todd A. Proebsting	Optimizing an ANSI C Interpreter with Superoperators.	POPL	1995	DBLP DOI BibTeX RDF	C
12	Mary F. Fernandez	Simple and Effective Link-Time Optimization of Modula-3 Programs.	PLDI	1995	DBLP DOI BibTeX RDF	C++, Modula-3
12	Trung A. Diep, Christopher Nelson, John Paul Shen	Performance Evaluation of the PowerPC 620 Microarchitecture.	ISCA	1995	DBLP DOI BibTeX RDF	PowerPC
12	Amit Ganesh	Fusing Loops With Backward Inter Loop Data Dependence.	ACM SIGPLAN Notices	1994	DBLP DOI BibTeX RDF
12	Julie Shipnes, Mike Philip	A Modular Approach to Motorola PowerPC Compilers.	Commun. ACM	1994	DBLP DOI BibTeX RDF	PowerPC
12	Phu Hoang, Jan M. Rabaey	A CAD environment for Real-time DSP implementations on multiprocessors.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
12	Manuel E. Benitez, Jack W. Davidson	The Advantages of Machine-Dependent Global Optimization.	Programming Languages and System Architectures	1994	DBLP DOI BibTeX RDF
12	Andreas Fauth, Günter Hommel, Alois C. Knoll, Carsten Müller	Global Code Selection of Directed Acyclic Graphs.	CC	1994	DBLP DOI BibTeX RDF
12	Shailesh Sutarwala, Pierre G. Paulin	Flexible modeling environment for embedded systems design.	CODES	1994	DBLP DOI BibTeX RDF
12	Jack W. Davidson, Sanjay Jinturkar	Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses.	PLDI	1994	DBLP DOI BibTeX RDF
12	Marina C. Chen, James R. Cowie	Prototyping Fortran-90 Compilers for Massively Parallel Machines.	PLDI	1992	DBLP DOI BibTeX RDF	FORTRAN, CM-2
12	Philip A. Wilsey, Subrata Dasgupta	A formal model of computer architectures for digital system design environments.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
12	Paul Kenyon, Prathima Agrawal, Sharad C. Seth	High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator.	MICRO	1990	DBLP BibTeX RDF	front-end DAG compiler, hand vs. compiled microcode, microcode compiler, programming environment for CAD, space/time overhead, code generation, hardware accelerator, performance data
12	Edward A. Lee, E. Goei, H. Heine, W.-H. Ho, Shuvra S. Bhattacharyya, Jeffery C. Bier, E. Guntvedt	GABRIEL: A Design Environment for Programmable DSPs.	DAC	1989	DBLP DOI BibTeX RDF
12	Richard H. Lathrop, Robert J. Hall 0001, Gavan Duffy, K. Mark Alexander, Robert S. Kirk	Advances in Functional Abstraction from Structure.	DAC	1988	DBLP BibTeX RDF
12	Jack S. Walicki, John D. Laughlin	Operation scheduling in reconfigurable, multifunction pipelines.	MICRO	1987	DBLP DOI BibTeX RDF