Search results for "x86"

Hits ?▲	Authors	Title	Venue	Year	Link
18	Kaixi Hou, Hao Wang 0002, Wu-chun Feng	ASPaS: A Framework for Automatic SIMDization of Parallel Sorting on x86-based Many-core Processors.	ICS	2015	DBLP DOI BibTeX RDF
18	Kevin Hammond, Christopher Brown 0002, Susmit Sarkar	Timing Properties and Correctness for Structured Parallel Programs on x86-64 Multicores.	FOPARA	2015	DBLP DOI BibTeX RDF
18	Evangelos Ladakis, Giorgos Vasiliadis, Michalis Polychronakis, Sotiris Ioannidis, Georgios Portokalidis	GPU-Disasm: A GPU-Based X86 Disassembler.	ISC	2015	DBLP DOI BibTeX RDF
18	I-Chun Liu, I-Wei Wu, Jean Jyh-Jiun Shann	Instruction Emulation and OS Supports of a Hybrid Binary Translator for x86 Instruction Set Architecture.	UIC/ATC/ScalCom	2015	DBLP DOI BibTeX RDF
18	Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson 0002, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White	4.8 A 28nm x86 APU optimized for power and area efficiency.	ISSCC	2015	DBLP DOI BibTeX RDF
18	Vignesh Babu, David M. Nicol	Detection of x86 malware in AMI data payloads.	SmartGridComm	2015	DBLP DOI BibTeX RDF
18	Chenhan D. Yu, Jianyu Huang, Woody Austin, Bo Xiao 0001, George Biros	Performance optimization for the k-nearest neighbors kernel on x86 architectures.	SC	2015	DBLP DOI BibTeX RDF
18	Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, Michael M. Swift	BadgerTrap: a tool to instrument x86-64 TLB misses.	SIGARCH Comput. Archit. News	2014	DBLP DOI BibTeX RDF
18	Erzhou Zhu, Feng Liu 0024, Xianyong Fang, Xuejun Li 0001, Yindong Yang, Alei Liang	DYBS: A Lightweight Dynamic Slicing Framework for Diagnosing Attacks on x86 Binary Programs.	J. Softw.	2014	DBLP DOI BibTeX RDF
18	John Gatewood Ham	An ECMA-55 Minimal BASIC Compiler for x86-64 Linux.	Comput.	2014	DBLP DOI BibTeX RDF
18	Johannes Hofmann 0001, Jan Treibig, Georg Hager, Gerhard Wellein	Comparing the Performance of Different x86 SIMD Instruction Sets for a Medical Imaging Application on Modern Multi- and Manycore Chips.	CoRR	2014	DBLP BibTeX RDF
18	Peter-Michael Seidel	Directed Test Case Generation for x86 Instruction Decoding.	MTV	2014	DBLP DOI BibTeX RDF
18	Jason Power, Mark D. Hill, David A. Wood 0001	Supporting x86-64 address translation for 100s of GPU lanes.	HPCA	2014	DBLP DOI BibTeX RDF
18	Bingjie Han, Ronggang Wang, Zhenyu Wang 0002, Shengfu Dong, Wenmin Wang, Wen Gao 0001	HEVC decoder acceleration on multi-core X86 platform.	ICASSP	2014	DBLP DOI BibTeX RDF
18	Aditya Basu, Anish Mathuria, Nagendra Chowdary	Automatic Generation of Compact Alphanumeric Shellcodes for x86.	ICISS	2014	DBLP DOI BibTeX RDF
18	Yanlin Li, Jonathan M. McCune, James Newsome, Adrian Perrig, Brandon Baker, Will Drewry	MiniBox: A Two-Way Sandbox for x86 Native Code.	USENIX Annual Technical Conference	2014	DBLP BibTeX RDF
18	Kevin Gillespie, Harry R. Fair III, Carson Henrion, Ravi Jotwani, Stephen V. Kosonocky, Robert S. Orefice, Donald A. Priore, Jonathan White, Kathryn Wilcox	5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS.	ISSCC	2014	DBLP DOI BibTeX RDF
18	Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger	5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor.	ISSCC	2014	DBLP DOI BibTeX RDF
18	Shilpi Goel, Warren A. Hunt Jr., Matt Kaufmann, Soumava Ghosh	Simulation and formal verification of x86 machine-code programs that make system calls.	FMCAD	2014	DBLP DOI BibTeX RDF
18	Dohyeong Kim, William N. Sumner, Xiangyu Zhang 0001, Dongyan Xu, Hira Agrawal	Reuse-oriented reverse engineering of functional components from x86 binaries.	ICSE	2014	DBLP DOI BibTeX RDF
18	Johannes Hofmann 0001, Jan Treibig, Georg Hager, Gerhard Wellein	Comparing the performance of different x86 SIMD instruction sets for a medical imaging application on modern multi- and manycore chips.	WPMVP@PPoPP	2014	DBLP DOI BibTeX RDF
18	Viviane Zwanger, Elmar Gerhards-Padilla, Michael Meier 0001	Codescanner: Detecting (Hidden) x86/x64 code in arbitrary files.	MALWARE	2014	DBLP DOI BibTeX RDF
18	Visvesh S. Sathe 0001, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger	Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
18	Zsombor Paroczi	x86 Instruction Reordering for Code Compression.	Acta Cybern.	2013	DBLP DOI BibTeX RDF
18	Ryad Benadjila, Jian Guo 0001, Victor Lomné, Thomas Peyrin	Implementing Lightweight Block Ciphers on x86 Architectures.	IACR Cryptol. ePrint Arch.	2013	DBLP BibTeX RDF
18	Shilpi Goel, Warren A. Hunt Jr.	Automated Code Proofs on a Formal Model of the X86.	VSTTE	2013	DBLP DOI BibTeX RDF
18	Lucas Vincenzo Davi, Alexandra Dmitrienko, Stefan Nürnberger, Ahmad-Reza Sadeghi	Gadge me if you can: secure and efficient ad-hoc instruction-level randomization for x86 and ARM.	AsiaCCS	2013	DBLP DOI BibTeX RDF
18	Ryad Benadjila, Jian Guo 0001, Victor Lomné, Thomas Peyrin	Implementing Lightweight Block Ciphers on x86 Architectures.	Selected Areas in Cryptography	2013	DBLP DOI BibTeX RDF
18	Erdem Aktas, Kanad Ghose	Run-time control flow authentication: an assessment on contemporary x86 platforms.	SAC	2013	DBLP DOI BibTeX RDF
18	Emily R. Blem, Jaikrishnan Menon, Karthikeyan Sankaralingam	Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures.	HPCA	2013	DBLP DOI BibTeX RDF
18	Furat Afram, Hui Zeng, Kanad Ghose	A group-commit mechanism for ROB-based processors implementing the X86 ISA.	HPCA	2013	DBLP DOI BibTeX RDF
18	Ryan Johnson 0002, Angelos Stavrou	Forced-Path Execution for Android Applications on x86 Platforms.	SERE (Companion)	2013	DBLP DOI BibTeX RDF
18	David Brumley, JongHyup Lee, Edward J. Schwartz, Maverick Woo	Native x86 Decompilation Using Semantics-Preserving Structural Analysis and Iterative Control-Flow Structuring.	USENIX Security Symposium	2013	DBLP BibTeX RDF
18	Jeff Rupley, John King, Eric Quinnell, Frank Galloway, Ken Patton, Peter-Michael Seidel, James Dinh, Hai Bui, Anasua Bhowmik	The Floating-Point Unit of the Jaguar x86 Core.	IEEE Symposium on Computer Arithmetic	2013	DBLP DOI BibTeX RDF
18	Xing Liu, Mikhail Smelyanskiy, Edmond Chow, Pradeep Dubey	Efficient sparse matrix-vector multiplication on x86-based many-core processors.	ICS	2013	DBLP DOI BibTeX RDF
18	Teja Singh, Joshua Bell, Shane Southard	Jaguar: A next-generation low-power x86-64 core.	ISSCC	2013	DBLP DOI BibTeX RDF
18	Magnus O. Myreen, Gregorio Curello	Proof Pearl: A Verified Bignum Implementation in x86-64 Machine Code.	CPP	2013	DBLP DOI BibTeX RDF
18	Qian Wang, Xianyi Zhang, Yunquan Zhang, Qing Yi	AUGEM: automatically generate high performance dense linear algebra kernels on x86 CPUs.	SC	2013	DBLP DOI BibTeX RDF
18	Adam Morrison 0001, Yehuda Afek	Fast concurrent queues for x86 processors.	PPoPP	2013	DBLP DOI BibTeX RDF
18	Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh	Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
18	Denis Foley, Pankaj Bansal, Don Cherepacha, Robert Wasmuth, Aswin Gunasekar, Srinivasa Rao Gutta, Ajay Naini	A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices.	IEEE J. Solid State Circuits	2012	DBLP DOI BibTeX RDF
18	Edouard Bugnion, Scott Devine, Mendel Rosenblum, Jeremy Sugerman, Edward Y. Wang	Bringing Virtualization to the x86 Architecture with the Original VMware Workstation.	ACM Trans. Comput. Syst.	2012	DBLP DOI BibTeX RDF
18	Rafael Vidal Aroca, Luiz Marcos Garcia Gonçalves	Towards green data centers: A comparison of x86 and ARM architectures power efficiency.	J. Parallel Distributed Comput.	2012	DBLP DOI BibTeX RDF
18	Amitabha Roy 0002, Steven Hand 0001, Tim Harris 0001	Weak atomicity for the x86 memory consistency model.	J. Parallel Distributed Comput.	2012	DBLP DOI BibTeX RDF
18	Jeroen Van Cleemput, Bart Coppens 0001, Bjorn De Sutter	Compiler mitigations for time attacks on modern x86 processors.	ACM Trans. Archit. Code Optim.	2012	DBLP DOI BibTeX RDF
18	Jeff Rupley	"Jaguar" AMD's next generation low power x86 core.	Hot Chips Symposium	2012	DBLP DOI BibTeX RDF
18	Amit Vasudevan, Jonathan M. McCune, James Newsome, Adrian Perrig, Leendert van Doorn	CARMA: a hardware tamper-resistant isolated execution environment on commodity x86 platforms.	AsiaCCS	2012	DBLP DOI BibTeX RDF
18	Richard Wartell, Vishwath Mohan, Kevin W. Hamlen, Zhiqiang Lin	Binary stirring: self-randomizing instruction addresses of legacy x86 binary code.	CCS	2012	DBLP DOI BibTeX RDF
18	Keaton Mowery, Sriram Keelveedhi, Hovav Shacham	Are AES x86 cache timing attacks still feasible?	CCSW	2012	DBLP DOI BibTeX RDF
18	Alexander Heinecke, Thomas Auckenthaler, Carsten Trinitis	Exploiting State-of-the-Art x86 Architectures in Scientific Computing.	ISPDC	2012	DBLP DOI BibTeX RDF
18	Christian Engelbert Ngono, Thomas Djotio Ndié	Implementation of a Function VoWiFi Communication on Android-x86.	AFRICOMM	2012	DBLP DOI BibTeX RDF
18	Keji Chen, Yizhou Duan, Leju Yan, Jun Sun 0012, Zongming Guo	Efficient SIMD optimization of HEVC encoder over X86 processors.	APSIPA	2012	DBLP BibTeX RDF
18	Leju Yan, Yizhou Duan, Jun Sun 0012, Zongming Guo	Implementation of HEVC decoder on x86 processors with SIMD optimization.	VCIP	2012	DBLP DOI BibTeX RDF
18	Kirill Kononenko	A unified approach to identifying and healing vulnerabilities in x86 machine code.	MobiCom	2012	DBLP DOI BibTeX RDF
18	Antoni Portero, Alberto Scionti, Zhibin Yu, Paolo Faraboschi, Caroline Concatto, Luigi Carro, Arne Garbade, Sebastian Weis, Theo Ungerer, Roberto Giorgi	Simulating the future kilo-x86-64 core processors and their infrastructure.	SpringSim (ANSS)	2012	DBLP BibTeX RDF
18	Dhiraj D. Kalamkar, Joshua D. Trzasko, Srinivas Sridharan 0002, Mikhail Smelyanskiy, Daehyun Kim 0001, Armando Manduca, Yunhong Shu, Matt A. Bernstein, Bharat Kaul, Pradeep Dubey	High Performance Non-uniform FFT on Modern X86-based Multi-core Systems.	IPDPS	2012	DBLP DOI BibTeX RDF
18	Takayoshi Fujii, Katsunari Yoshioka, Junji Shikata, Tsutomu Matsumoto	An Efficient Dynamic Detection Method for Various x86 Shellcodes.	SAINT	2012	DBLP DOI BibTeX RDF
18	Greg Morrisett, Gang Tan, Joseph Tassarotti, Jean-Baptiste Tristan, Edward Gan	RockSalt: better, faster, stronger SFI for the x86.	PLDI	2012	DBLP DOI BibTeX RDF
18	Nishkam Ravi, Yi Yang 0018, Tao Bao, Srimat T. Chakradhar	Apricot: an optimizing compiler and productivity tool for x86-compatible many-core coprocessors.	ICS	2012	DBLP DOI BibTeX RDF
18	Steve J. Dillen, Donald A. Priore, Aaron Horiuchi, Samuel Naffziger	Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules.	CICC	2012	DBLP DOI BibTeX RDF
18	Visvesh S. Sathe 0001, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger	Resonant clock design for a power-efficient high-volume x86-64 microprocessor.	ISSCC	2012	DBLP DOI BibTeX RDF
18	Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Durgesh Srivastava, Satish Venkatesan, Hyung-Jin Lee, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Krishnamurthy Soumyanath, Sunder Ramamurthy	32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver.	ISSCC	2012	DBLP DOI BibTeX RDF
18	Svilen Kanev, Gu-Yeon Wei, David M. Brooks	XIOSim: power-performance modeling of mobile x86 cores.	ISLPED	2012	DBLP DOI BibTeX RDF
18	Aaron Rogers, David Kaplan, Eric Quinnell, Bill Kwan	The core-C6 (CC6) sleep state of the AMD bobcat x86 microprocessor.	ISLPED	2012	DBLP DOI BibTeX RDF
18	Wing-Chi Poon, Aloysius K. Mok	Improving the Latency of VMExit Forwarding in Recursive Virtualization for the x86 Architecture.	HICSS	2012	DBLP DOI BibTeX RDF
18	Jae-Won Min, Sung-Min Jung, Dong-Young Lee, Tai-Myoung Chung	Jump Oriented Programming on Windows Platform (on the x86).	ICCSA (3)	2012	DBLP DOI BibTeX RDF
18	Zongwei Zhou, Virgil D. Gligor, James Newsome, Jonathan M. McCune	Building Verifiable Trusted Path on Commodity x86 Computers.	IEEE Symposium on Security and Privacy	2012	DBLP DOI BibTeX RDF
18	Ulf Kargén, Nahid Shahmehri	InputTracer: A Data-Flow Analysis Tool for Manual Program Comprehension of x86 Binaries.	SCAM	2012	DBLP DOI BibTeX RDF
18	Ulan Degenbaev	Formal specification of the x86 instruction set architecture.		2012	RDF
18	Josef Weidendorfer	Intel Core Microarchitecture, x86 Processor Family.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
18	Ravi Jotwani, Sriram Sundaram, Stephen Kosonocky, Alex Schaefer, Victor Andrade, Amy Novak, Sam Naffziger	An x86-64 Core in 32 nm SOI CMOS.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
18	Brad Burgess, Brad Cohen, Marvin Denman, Jim Dundas, David Kaplan, Jeff Rupley	Bobcat: AMD's Low-Power x86 Processor.	IEEE Micro	2011	DBLP DOI BibTeX RDF
18	Rubén Apolloni, Daniel Chaver, Fernando Castro, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado	Hybrid timing-address oriented load-store queue filtering for an x86 architecture.	IET Comput. Digit. Tech.	2011	DBLP DOI BibTeX RDF
18	Francisco G. Montoya, Alfredo Alcayde, Pedro Sánchez, Consolación Gil, Maria Dolores Gil Montoya, Julio Gómez	Comparative analysis of power variables in high performance embedded and x86 architectures using GNU/Linux.	Comput. Electr. Eng.	2011	DBLP DOI BibTeX RDF
18	Thomas Sperl	Taking the redpill: Artificial Evolution in native x86 systems	CoRR	2011	DBLP BibTeX RDF
18	Peter-Michael Seidel	Formal Verification of an Iterative Low-Power x86 Floating-Point Multiplier with Redundant Feedback	ACL2	2011	DBLP DOI BibTeX RDF
18	Don Revelle	Hypervisors and Virtual Machines: Implementation Insights on the x86 Architecture.	login Usenix Mag.	2011	DBLP BibTeX RDF
18	Chi-Keung Luk, Ryan Newton, William Hasenplaugh, Mark Hampton, Geoff Lowney	A Synergetic Approach to Throughput Computing on x86-Based Multicore Desktops.	IEEE Softw.	2011	DBLP DOI BibTeX RDF
18	Sean White	High-performance power-efficient x86-64 server and desktop processors using the core codenamed "Bulldozer".	Hot Chips Symposium	2011	DBLP DOI BibTeX RDF
18	Richard Wartell, Yan Zhou 0001, Kevin W. Hamlen, Murat Kantarcioglu, Bhavani Thuraisingham	Differentiating Code from Data in x86 Binaries.	ECML/PKDD (3)	2011	DBLP DOI BibTeX RDF
18	Ping Chen 0003, Xiao Xing, Bing Mao, Li Xie 0001, Xiaobin Shen 0001, Xinchun Yin	Automatic construction of jump-oriented programming shellcode (on the x86).	AsiaCCS	2011	DBLP DOI BibTeX RDF
18	Ahmed M. Azab, Peng Ning, Xiaolan Zhang 0001	SICE: a hardware-level strongly isolated computing environment for x86 multi-core platforms.	CCS	2011	DBLP DOI BibTeX RDF
18	J.-M. Huang, R. R. Xiao, H. Guo, K. Han	A Method Based on Bochs for Accelerating the x86 Timing Emulator.	CSISE (2)	2011	DBLP DOI BibTeX RDF
18	Gilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Emile Gottschlich, Jungwoo Ha, Youfeng Wu	CoreRacer: a practical memory race recorder for multicore x86 TSO processors.	MICRO	2011	DBLP DOI BibTeX RDF
18	Jan Treibig, Georg Hager, Gerhard Wellein	likwid-bench: An Extensible Microbenchmarking Platform for x86 Multicore Compute Nodes.	Parallel Tools Workshop	2011	DBLP DOI BibTeX RDF
18	Renan Augusto Starke, Rômulo Silva de Oliveira	Impact of the x86 System Management Mode in Real-Time Systems.	SBESC	2011	DBLP DOI BibTeX RDF
18	Hussein Karaki, Haitham Akkary, Shahrokh Shahidzadeh	X86-ARM binary hardware interpreter.	ICECS	2011	DBLP DOI BibTeX RDF
18	Chao Wang 0001, Malay K. Ganai	Predicting Concurrency Failures in the Generalized Execution Traces of x86 Executables.	RV	2011	DBLP DOI BibTeX RDF
18	Michael David Black, Priyadarshini Komala	A full system x86 simulator for teaching computer organization.	SIGCSE	2011	DBLP DOI BibTeX RDF
18	Santosh Sonawane, Tzi-cker Chiueh	Optimization of an Instrumentation Tool for Stripped Win32/X86 Binaries.	ICPADS	2011	DBLP DOI BibTeX RDF
18	Michael Golden, Srikanth Arekapudi, James Vinh	40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core.	ISSCC	2011	DBLP DOI BibTeX RDF
18	Srinivasa Rao Gutta, Denis Foley, Ajay Naini, Robert Wasmuth, Don Cherepacha	A low-power integrated x86-64 and graphics processor for mobile computing devices.	ISSCC	2011	DBLP DOI BibTeX RDF
18	Amitabha Roy 0002, Steven Hand 0001, Tim Harris 0001	Weak atomicity under the x86 memory consistency model.	PPoPP	2011	DBLP DOI BibTeX RDF
18	Kevin Coogan, Saumya K. Debray	Equational Reasoning on x86 Assembly Code.	SCAM	2011	DBLP DOI BibTeX RDF
18	Avadh Patel, Furat Afram, Shunfei Chen, Kanad Ghose	MARSS: a full system simulator for multicore x86 CPUs.	DAC	2011	DBLP DOI BibTeX RDF
18	Amitabha Roy 0002	Software lock elision for x86 machine code.		2011	RDF
18	Jih-Ching Chiu, Yu-Liang Chou, Tseng-Kuei Lin	The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA.	J. Inf. Sci. Eng.	2010	DBLP BibTeX RDF
18	Frederick Ryckbosch, Stijn Polfliet, Lieven Eeckhout	Fast, Accurate, and Validated Full-System Software Simulation of x86 Hardware.	IEEE Micro	2010	DBLP DOI BibTeX RDF
18	Emmet Caulfield, Andreas Hellander	CellMC - a multiplatform model compiler for the Cell Broadband Engine and x86.	Bioinform.	2010	DBLP DOI BibTeX RDF
18	Adrianto Wirawan, Chee Keong Kwoh 0001, Bertil Schmidt	Multi-threaded vectorized distance matrix computation on the CELL/BE and x86/SSE2 architectures.	Bioinform.	2010	DBLP DOI BibTeX RDF