| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Yongjoo Kim, Jongeun Lee, Jinyong Lee, Toan X. Mai, Ingoo Heo, Yunheung Paek |
Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture.  |
ARC  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Grigorios Mingas, Christos-Savvas Bouganis |
Parallel Tempering MCMC Acceleration Using Reconfigurable Hardware. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kashif Latif, M. Muzaffar Rao, Athar Mahboob, Arshad Aziz |
Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt |
Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tassadaq Hussain, Muhammad Shafiq 0003, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé |
PPMC: A Programmable Pattern Based Memory Controller. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yarkin Doröz, Erkay Savas |
Constructing Cluster of Simple FPGA Boards for Cryptologic Computations. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ehsan Zadkhosh, Sepide Fatahi, Mahmood Ahmadi |
Performance Analysis of Reconfigurable Processors Using MVA Analysis. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Geoffrey Ndu, Jim D. Garside |
Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Takahiro Watanabe, Minoru Watanabe |
Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas, Wayne Luk |
Optimising Performance of Quadrature Methods with Reduced Precision. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise |
ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sayyed Arash Ostadzadeh, Roel Meeuws, Imran Ashraf, Carlo Galuzzi, Koen Bertels |
The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sen Ma, Miaoqing Huang, Eugene Cartwright, David Andrews 0001 |
Scalable Memory Hierarchies for Embedded Manycore Systems. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tannous Frangieh, Richard Stroop, Peter Athanas, Teresa Cervero |
A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongbing Fan, Yue-Ang Chen, Yu-Liang Wu |
R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Annie Avakian, Natwar Agrawal, Ranga Vemuri |
Reconfigurable Multicore Architecture for Dynamic Processor Reallocation. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Wang 0003, Xi Li 0003, Xuehai Zhou, Xiaojing Feng |
CRAIS: A Crossbar Based Adaptive Interconnection Scheme. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kizheppatt Vipin, Suhaib A. Fahmy |
Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Markus Weinhardt |
Teaching Hardware/Software Codesign on a Reconfigurable Computing Platform. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tim Güneysu, Igor L. Markov, André Weimerskirch |
Securely Sealing Multi-FPGA Systems. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt |
A Connection Router for the Dynamic Reconfiguration of FPGAs. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Stewart Denholm, Kuen Hung Tsoi, Peter R. Pietzuch, Wayne Luk |
Efficient Communication for FPGA Clusters. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Gang Zhou, Li Li 0027, Harald Michalik |
Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Abid Rafique, Nachiket Kapre, George A. Constantinides |
A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Florent de Dinechin, Laurent-Stéphane Didier |
Table-Based Division by Small Integer Constants. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Oliver C. S. Choy, Ray C. C. Cheung, Peter M. Athanas, Kentaro Sano (eds.) |
Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Manish Kumar Jaiswal, Ray C. C. Cheung |
High Performance Reconfigurable Architecture for Double Precision Floating Point Division. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Luzhou Wang, Kentaro Sano, Satoru Yamamoto |
Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary Chun Tak Chow, David B. Thomas, Wayne Luk, Stephen Weston |
Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Ting Loke, Yajun Ha |
A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters. |
ARC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Umer Farooq 0001, Husain Parvez, Zied Marrakchi, Habib Mehrez |
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kevin Cunningham, Prawat Nagvajara |
Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Koch 0001, Ram Krishnamurthy 0001, John McAllister, Roger F. Woods, Tarek A. El-Ghazawi (eds.) |
Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Francisco Barranco, Matteo Tomasi, Javier Díaz 0001, Eduardo Ros 0001 |
Hierarchical Optical Flow Estimation Architecture Using Color Cues. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch |
FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hironobu Morita, Minoru Watanabe |
MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk |
FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Andreas Engel 0003, Björn Liebig, Andreas Koch 0001 |
Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Christophe Le Lann, David Boland, George A. Constantinides |
The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev |
A Reconfigurable Audio Beamforming Multi-Core Processor. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Séamas McGettrick, Kunjan Patel, Chris J. Bleakley |
High Performance Programmable FPGA Overlay for Digital Signal Processing. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jon T. Butler, Tsutomu Sasao |
Index to Constant Weight Codeword Converter. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Wu, Yi Shan, Xiaoming Chen 0003, Yu Wang 0002, Huazhong Yang |
FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xuezheng Chu, John McAllister, Roger F. Woods |
A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario Alberto Ibarra-Manzano, Dora Luz Almanza-Ojeda |
An FPGA Implementation for Texture Analysis Considering the Real-Time Requirements of Vision-Based Systems. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Traian Tulbure |
A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami |
Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Samuel Bayliss, George A. Constantinides |
Application Specific Memory Access, Reuse and Reordering for SDRAM. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Christophe Alias, Bogdan Pasca 0001, Alexandru Plesco |
Automatic Generation of FPGA-Specific Pipelined Accelerators. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikolaos Alachiotis 0001, Alexandros Stamatakis |
FPGA Optimizations for a Pipelined Floating-Point Exponential Unit. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Pavel G. Zaykov, Georgi Kuzmanov |
Architectural Support for Multithreading on Reconfigurable Hardware. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jair Fajardo Junior, Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro |
Towards an Adaptable Multiple-ISA Reconfigurable Processor. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexandre Cornu, Steven Derrien, Dominique Lavenier |
HLS Tools for FPGA: Faster Development with Better Performance. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sascha Mühlbach, Andreas Koch 0001 |
NetStage/DPR: A Self-adaptable FPGA Platform for Application-Level Network Security. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gordon J. Brebner |
Reconfigurable Computing for High Performance Networking Applications. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Mikel Azkarate-askasua, Imanol Martinez |
A (Fault-Tolerant)2 Scheduler for Real-Time HW Tasks. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura |
A Regular Expression Matching Circuit Based on a Decomposed Automaton. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Grand, Lilian Bossuet, Bertrand Le Gal, Guy Gogniat, Dominique Dallet |
Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nehir Sönmez, Oriol Arcas, Gokhan Sayilar, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero |
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Manouk V. Manoukian, George A. Constantinides |
Accurate Floating Point Arithmetic through Hardware Error-Free Transformations. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | François Duhem, Fabrice Muller, Philippe Lorenzini |
FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy 0001, Ranjani Narayan |
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro |
CReAMS: An Embedded Multiprocessor Platform. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander Biedermann, Marc Stöttinger, Lijing Chen, Sorin A. Huss |
Secure Virtualization within a Multi-processor Soft-Core System-on-Chip Architecture. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Steve B. Furber |
Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mauricio Vanegas, Leonardo Rubio, Matteo Tomasi, Javier Díaz 0001, Eduardo Ros 0001 |
On-Chip Ego-Motion Estimation Based on Optical Flow. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Subhasis Das, Sachin Patkar |
A Compact Gaussian Random Number Generator for Small Word Lengths. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefan Schulze, Sergei Sawitzki |
Design, Implementation, and Verification of an Adaptable Processor in Lava HDL. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Weibo Pan, William P. Marnane |
A Correlation Power Analysis Attack against Tate Pairing on FPGA. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Janardhan Singaraju, John A. Chandy |
Active Storage Networks for Accelerating K-Means Data Clustering. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert |
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power. |
ARC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Steven J. E. Wilton |
Towards Analytical Methods for FPGA Architecture Investigation. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahmood Fazlali, Ali Zakerolhosseini, Georgi Gaydadjiev |
A Modified Merging Approach for Datapath Configuration Time Reduction. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt |
Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka |
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Christopher Claus, Rehan Ahmed, Florian Altenried, Walter Stechele |
Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Masato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer |
A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung |
Design Automation for Reconfigurable Interconnection Networks. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Reibel Boesen, Pascal Schleuniger, Jan Madsen |
Feasibility Study of a Self-healing Hardware Platform. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Harald Devos, Wim Meeus, Dirk Stroobandt |
Towards a Tighter Integration of Generated and Custom-Made Hardware. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mehdi Darouich, Stéphane Guyetant, Dominique Lavenier |
A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance Systems. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Johann Glaser, Markus Damm, Jan Haase 0001, Christoph Grimm 0001 |
A Dedicated Reconfigurable Architecture for Finite State Machines. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Siew Kei Lam, Yun Deng, Jian Hu, Xilong Zhou, Thambipillai Srikanthan |
Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Labrecque, Mark C. Jeffrey, J. Gregory Steffan |
Application-Specific Signatures for Transactional Memory in Soft Processors. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo |
Generic Systolic Array for Run-Time Scalable Cores. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Marc Stöttinger, Alexander Biedermann, Sorin Alexander Huss |
Virtualization within a Parallel Array of Homogeneous Processing Units. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides |
Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Victoria Rodellar, Elvira Martínez de Icaya, Francisco Díaz Pérez, Virginia Peinado |
Cost and Performance Evaluation of a Noise Filter for Partitioning in Co-design Methodologies. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Adrien Le Masle, Wayne Luk, Jared Eldredge, Kristopher Carver |
Parametric Encryption Hardware Design. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Niels Penneman, Luc Perneel, Martin Timmerman, Bjorn De Sutter |
An FPGA-Based Real-Time Event Sampler. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Akkarat Boonpoonga, Sompop Janyavilas, Phaophak Sirisuk, Monai Krairiksh |
FPGA Implementation of QR Decomposition Using MGS Algorithm. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daisaku Seto, Minoru Watanabe |
MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej Wielgosz, Ernest Jamro, Pawel Russek, Kazimierz Wiatr |
Hardware Implementation of the Orbital Function for Quantum Chemistry Calculations. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kunjan Patel, Chris J. Bleakley |
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kostas Siozios, Dimitrios Soudris, Dionisios N. Pnevmatikatos |
A Framework for Enabling Fault Tolerance in Reconfigurable Architectures. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Alok Prakash, Siew Kei Lam, Amit Kumar Singh 0002, Thambipillai Srikanthan |
Architecture-Aware Custom Instruction Generation for Reconfigurable Processors. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Phak Len Eh Kan, Tim Allen, Steven F. Quigley |
A GMM-Based Speaker Identification System on FPGA. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Suhaib A. Fahmy, Linda Doyle |
Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Abdulhadi Shoufan, Sorin Alexander Huss |
Reconfigurable Computing Education in Computer Science. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
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