Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Chandan Kumar Jha 0001, Kailash Prasad, Arun Singh Tomar, Joycee Mekie |
SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors. |
ISCAS |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Raul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella |
Customized Posit Adders and Multipliers using the FloPoCo Core Generator. |
ISCAS |
2020 |
DBLP DOI BibTeX RDF |
|
16 | D. Vaithiyanathan 0001, Rajhans Kolhe, Alok Kumar Mishra 0001, Pari J. Britto, K. Kunaraj |
Performance Analysis of 8-Point Approximate DCT Architecture Using Conventional and Hybrid Adders. |
iSES |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Yamini devi Ykuntam, Katta Pavani, Krishna Saladi |
Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI circuit designs. |
ICCCNT |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Usha Maddipati, Shaik Ahemedali, Maddipati Sri Sai Ramya, M. D. Praneeth Reddy, K. N. J. Priya |
Comparative analysis of 16-tap FIR filter design using different adders. |
ICCCNT |
2020 |
DBLP DOI BibTeX RDF |
|
16 | I. V. Ushenina, E. V. Chirkova |
Implementing Sticky Bit Generators Based on FPGA Carry-Chains for Floating-Point Adders. |
CSOC (3) |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Ireneusz Brzozowski |
Comparative Analysis of Power Consumption of Parallel Prefix Adders. |
MIXDES |
2020 |
DBLP BibTeX RDF |
|
16 | Muhammad Abdullah Hanif, Rehan Hafiz, Osman Hasan, Muhammad Shafique 0001 |
PEMACx: A Probabilistic Error Analysis Methodology for Adders with Cascaded Approximate Units. |
DAC |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Yizhi Chen, Ardalan Najafi, Alberto García Ortiz |
On the Effects of Data Distribution on Small-error Approximate Adders. |
MOCAST |
2020 |
DBLP DOI BibTeX RDF |
|
16 | Mansi Jhamb, Tejaswini Dhall, Tamish Verma, Hinduja Pudi |
Pipelined adders for ultralow-power wearables. |
Turkish J. Electr. Eng. Comput. Sci. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Manan Mewada, Mazad Zaveri, Rajesh Amratlal Thakker |
Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures. |
Integr. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto |
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. |
IEEE Trans. Very Large Scale Integr. Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Hareesh-Reddy Basireddy, Karthikeya Challa, Tooraj Nikoubin |
Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures. |
IEEE Trans. Very Large Scale Integr. Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Sara Hashemi, Mostafa Rahimi Azghadi, Keivan Navi |
Design and analysis of efficient QCA reversible adders. |
J. Supercomput. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Pramod Patali, Shahana Thottathikkulam Kassim |
High throughput FIR filter architectures using retiming and modified CSLA based adders. |
IET Circuits Devices Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Yi Wu, You Li, Xiangxuan Ge, Yuan Gao 0012, Weikang Qian |
An Efficient Method for Calculating the Error Statistics of Block-Based Approximate Adders. |
IEEE Trans. Computers |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Sunil Dutt, Satyabrata Dash, Sukumar Nandi, Gaurav Trivedi |
Analysis, Modeling and Optimization of Equal Segment Based Approximate Adders. |
IEEE Trans. Computers |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu 0001 |
Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Amina Qureshi, Osman Hasan |
Formal Probabilistic Analysis of Low Latency Approximate Adders. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Seyed-Sajad Ahmadpour, Mohammad Mosleh, Saeed Rasouli Heikalabad |
Robust QCA full-adders using an efficient fault-tolerant five-input majority gate. |
Int. J. Circuit Theory Appl. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Morteza Rezaalipour, Mohammad Rezaalipour, Sarvenaz Tajasob, Masoud Dehyadegari |
IDrAx: A tool-chain for designing efficient approximate adders. |
Microelectron. J. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Sarvenaz Tajasob, Morteza Rezaalipour, Masoud Dehyadegari |
Designing energy-efficient imprecise adders with multi-bit approximation. |
Microelectron. J. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Daniel Etiemble |
Comparing ternary and binary adders and multipliers. |
CoRR |
2019 |
DBLP BibTeX RDF |
|
16 | P. Balasubramanian 0001 |
Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders. |
CoRR |
2019 |
DBLP BibTeX RDF |
|
16 | Seyed-Sajad Ahmadpour, Mohammad Mosleh |
New designs of fault-tolerant adders in quantum-dot cellular automata. |
Nano Commun. Networks |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Masoud Pashaeifar, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram |
A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Kleanthis Papachatzopoulos, Vassilis Paliouras |
Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Leonardo Bandeira Soares, Morgana Macedo Azevedo da Rosa, Cláudio Machado Diniz, Eduardo Antonio Cesar da Costa, Sergio Bampi |
Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Sana Mazahir, Muhammad Kamran Ayub, Osman Hasan, Muhammad Shafique 0001 |
Probabilistic Error Analysis of Approximate Adders and Multipliers. |
Approximate Circuits |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Muhammad Abdullah Hanif, Rehan Hafiz, Muhammad Shafique 0001 |
Configurable Models and Design Space Exploration for Low-Latency Approximate Adders. |
Approximate Circuits |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Kyle Price, James E. Stine |
Using Carry Increment Adders to Enhance Energy Savings with Spanning-Tree Adder Structures. |
MWSCAS |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Roger Endrigo Carvalho Porto, Luciano Agostini, Bruno Zatt, Nuno Roma, Marcelo Schiavon Porto |
Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders. |
LASCAS |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Fabio G. Rossato G. da Silva, Cristina Meinhardt, Ricardo Augusto da Luz Reis |
FinFET Variability and Near-threshold operation: Impact on Full Adders design using XOR Blocks. |
ICECS |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Martin Langhammer, Bogdan Pasca 0001, Gregg Baeckler |
High Precision, High Performance FPGA Adders. |
FCCM |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Nima Taherinejad, Théophile Delaroche, David Radakovits, Shahriar Mirabbasi |
A Semi-Serial Topology for Compact and Fast IMPLY-based Memristive Full Adders. |
NEWCAS |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi |
Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. |
ISCAS |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Mineo Kaneko |
A Novel Framework for Procedural Construction of Parallel Prefix Adders. |
ISCAS |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Fasih Ud Din Farrukh, Tuo Xie, Chun Zhang, Zhihua Wang 0001 |
A Solution to Optimize Multi-Operand Adders in CNN Architecture on FPGA. |
ISCAS |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Honglan Jiang, Francisco J. H. Santiago, Mohammad Saeed Ansari, Leibo Liu, Bruce F. Cockburn, Fabrizio Lombardi, Jie Han 0001 |
Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints. |
ACM Great Lakes Symposium on VLSI |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Chandan Kumar Jha 0001, Joycee Mekie |
SEDA - Single Exact Dual Approximate Adders for Approximate Processors. |
DAC |
2019 |
DBLP DOI BibTeX RDF |
|
16 | Jorge Echavarria, Stefan Wildermann, Eduard Potwigin, Jürgen Teich |
Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders. |
IEEE Embed. Syst. Lett. |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Sunil Dutt, Sukumar Nandi, Gaurav Trivedi |
Accuracy enhancement of equal segment based approximate adders. |
IET Comput. Digit. Tech. |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Ali Asghar Vatanjou, Even Låte, Trond Ytterdal, Snorre Aunet |
Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing. |
Microprocess. Microsystems |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Sunil Dutt, Sukumar Nandi, Gaurav Trivedi |
Analysis and Design of Adders for Approximate Computing. |
ACM Trans. Embed. Comput. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Chetan Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas |
Energy efficient design of CNFET-based multi-digit ternary adders. |
Microelectron. J. |
2018 |
DBLP DOI BibTeX RDF |
|
16 | P. Balasubramanian 0001 |
Performance Comparison of some Synchronous Adders. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
16 | Yongcheng Ding, Lucas Lamata, Mikel Sanz, Xi Chen 0059, Enrique Solano |
Experimental Implementation of a Quantum Autoencoder via Quantum Adders. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
16 | Shahrzad Keshavarz, Daniel E. Holcomb |
Privacy Leakages in Approximate Adders. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
16 | Moein Sarvaghad-Moghaddam, Ali A. Orouji |
New Symmetric and Planar Designs of Reversible Full-Adders/Subtractors in Quantum-Dot Cellular Automata. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
16 | Avishek Sinha Roy, Anindya Sundar Dhar |
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
16 | P. Balasubramanian 0001 |
Approximate Early Output Asynchronous Adders Based on Dual-Rail Data Encoding and 4-Phase Return-to-Zero and Return-to-One Handshaking. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
16 | Kamel Abdelouahab, François Berry, Maxime Pelcat |
The Challenge of Multi-Operand Adders in CNNs on FPGAs: How not to solve it! |
CoRR |
2018 |
DBLP BibTeX RDF |
|
16 | Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu 0001 |
Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach. |
CoRR |
2018 |
DBLP BibTeX RDF |
|
16 | Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis |
Evaluation of variability using Schmitt trigger on full adders layout. |
Microelectron. Reliab. |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Ardalan Najafi, Moritz Weißbrich, Guillermo Payá Vayá, Alberto García Ortiz |
Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics. |
IEEE J. Emerg. Sel. Topics Circuits Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Xiao-Ping Cui, Weiqiang Liu 0001, Shumin Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi |
Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders. |
J. Signal Process. Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Dariush Abedi, Ghassem Jaberipur |
Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata. |
IEEE Trans. Circuits Syst. II Express Briefs |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Martin Kumm, Oscar Gustafsson, Mario Garrido, Peter Zipf |
Optimal Single Constant Multiplication Using Ternary Adders. |
IEEE Trans. Circuits Syst. II Express Briefs |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Kleanthis Papachatzopoulos, Vassilis Paliouras |
Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability. |
IEEE Trans. Circuits Syst. II Express Briefs |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Kamel Abdelouahab, Maxime Pelcat, François Berry |
The challenge of multi-operand adders in CNNs on FPGAs: how not to solve it! |
SAMOS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Nikolay V. Butyrlagin, Nikolay I. Chernov, Nikolay N. Prokopenko, Vladislav Y. Yugai |
Design of Two-Valued and Multivalued Current Digital Adders Based on the Mathematical Tool of Linear Algebra. |
EWDTS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | D. Celia, Vinita Vasudevan, Nitin Chandrachoodan |
Optimizing power-accuracy trade-off in approximate adders. |
DATE |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Bharath Srinivas Prabakaran, Semeen Rehman, Muhammad Abdullah Hanif, Salim Ullah, Ghazal Mazaheri, Akash Kumar 0001, Muhammad Shafique 0001 |
DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems. |
DATE |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Leonardo Bandeira Soares, Morgana M. A. da Rosa, Cláudio Machado Diniz, Eduardo A. C. da Costa, Sergio Bampi |
Exploring power-performance-quality tradeoff of approximate adders for energy efficient sobel filtering. |
LASCAS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Martin Hardieck, Martin Kumm, Patrick Sittel, Peter Zipf |
Constant Matrix Multiplication with Ternary Adders. |
ICECS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Talha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri |
10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs. |
ICECS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Vojtech Mrazek, Zdenek Vasícek |
Evolutionary design of large approximate adders optimized for various error criteria. |
GECCO (Companion) |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Scott Tancock, Ekin Arabul, Naim Dahnoun, Shahid Mehmood |
Can DSP48A1 adders be used for high-resolution delay generation? |
MECO |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Sarvenaz Tajasob, Morteza Rezaalipour, Masoud Dehyadegari, Mahdi Nazm Bojnordi |
Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks. |
ISLPED |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Samuel Presa Toledo, Alexandra L. Zimpeck, Ricardo Reis 0001, Cristina Meinhardt |
Pros and Cons of Schmitt Trigger Inverters to Mitigate PVT Variability on Full Adders. |
ISCAS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Tingting Zhang, Weiqiang Liu 0001, Emma McLarnon, Máire O'Neill, Fabrizio Lombardi |
Design of Majority Logic (ML) Based Approximate Full Adders. |
ISCAS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Amir Sabbagh Molahosseini, Ailin Asadpoor, Azadeh Alsadat Emrani Zarandi, Leonel Sousa |
Towards Efficient Modular Adders based on Reversible Circuits. |
ISCAS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Avishek Sinha Roy, Anindya Sundar Dhar |
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders. |
ISCAS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Takayuki Moto, Mineo Kaneko |
Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing. |
ISCAS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | D. Celia, Vinita Vasudevan, Nitin Chandrachoodan |
Probabilistic Error Modeling for Two-part Segmented Approximate Adders. |
ISCAS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Jianhui Jiang, Guangming Lu, Zhen Wang |
Methods for Approximate Adders Reliability Estimation Based on PTM Model. |
PRDC |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Mawahib Hussein Sulieman, Zakaria FadlAlrnoula Himat |
On the Design of Nanoscale CMOS Threshold-Logic Adders. |
SSD |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Ioannis Voyiatzis, Costas Efstathiou |
SIC pair generation in near-optimal time with carry-look ahead adders. |
DTIS |
2018 |
DBLP DOI BibTeX RDF |
|
16 | M. Priyadharshni, Sundaram Kumaravel 0001 |
A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications. |
VDAT |
2018 |
DBLP DOI BibTeX RDF |
|
16 | Jean-Michel Fourneau, Erol Gelenbe |
G-Networks with Adders. |
Future Internet |
2017 |
DBLP DOI BibTeX RDF |
|
16 | George Razvan Voicu, Sorin Dan Cotofana |
High-Performance, Cost-Effective 3D Stacked Wide-Operand Adders. |
IEEE Trans. Emerg. Top. Comput. |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Stephan Held, Sophie Spirkl |
Fast Prefix Adders for Non-uniform Input Arrival Times. |
Algorithmica |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Sana Mazahir, Osman Hasan, Rehan Hafiz, Muhammad Shafique 0001, Jörg Henkel |
Probabilistic Error Modeling for Approximate Adders. |
IEEE Trans. Computers |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Burhan Khurshid, Roohie Naaz Mir |
Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs. |
J. Circuits Syst. Comput. |
2017 |
DBLP DOI BibTeX RDF |
|
16 | N. Poornima, V. S. Kanchana Bhaaskaran |
Design and Implementation of 32-Bit High Valency Jackson Adders. |
J. Circuits Syst. Comput. |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Xinghua Yang, Yue Xing 0001, Fei Qiao, Huazhong Yang |
Multistage Latency Adders Architecture Employing Approximate Computing. |
J. Circuits Syst. Comput. |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Fazel Sharifi, Atiyeh Panahi, Mohammad Hossein Moaiyeri, Keivan Navi |
High Performance CNFET-based Ternary Full Adders. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
16 | Lucas Lamata, Unai Alvarez-Rodriguez, José David Martín-Guerrero, Mikel Sanz, Enrique Solano |
Quantum Autoencoders via Quantum Adders with Genetic Algorithms. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
16 | Yi Wu, You Li, Xiangxuan Ge, Weikang Qian |
An Accurate and Efficient Method to Calculate the Error Statistics of Block-based Approximate Adders. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
16 | P. Balasubramanian 0001, K. Prasad |
Asynchronous Early Output Dual-Bit Full Adders Based on Homogeneous and Heterogeneous Delay-Insensitive Data Encoding. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
16 | Dietmar Fey |
Evaluating Ternary Adders using a hybrid Memristor / CMOS approach. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
16 | P. Balasubramanian 0001, Cuong Dang, Douglas L. Maskell, K. Prasad |
Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis. |
CoRR |
2017 |
DBLP BibTeX RDF |
|
16 | Hossein Moradian, Jeong-A Lee, Joonsang Yu |
Efficient Low-Cost Fault-Localization and Self-Repairing Radix-2 Signed-Digit Adders Applying the Self-Dual Concept. |
J. Signal Process. Syst. |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri |
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata. |
IEEE Trans. Circuits Syst. II Express Briefs |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Ardalan Najafi, Moritz Weißbrich, Guillermo Payá Vayá, Alberto García Ortiz |
A fair comparison of adders in stochastic regime. |
PATMOS |
2017 |
DBLP DOI BibTeX RDF |
|
16 | P. Balasubramanian 0001, Cuong Dang, Douglas L. Maskell |
Approximate quasi-delay-insensitive asynchronous adders: Design and analysis. |
MWSCAS |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Soumya Banerjee 0004, Wenjing Rao |
A General Design Framework for Sparse Parallel Prefix Adders. |
ISVLSI |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Xun Jiao, Vincent Camus, Mattia Cacciotti, Yu Jiang 0001, Christian C. Enz, Rajesh K. Gupta 0001 |
Combining structural and timing errors in overclocked inexact speculative adders. |
DATE |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Vojtech Mrazek, Radek Hrbacek, Zdenek Vasícek, Lukás Sekanina |
EvoApproxSb: Library of approximate adders and multipliers for circuit design and benchmarking of approximation methods. |
DATE |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Ayan Palchaudhuri, Anindya Sundar Dhar |
Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs. |
HiPC |
2017 |
DBLP DOI BibTeX RDF |
|