Search results for "CASES"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Jason George, Bo Marr, Bilge Saglam Akgul, Krishna V. Palem	Probabilistic arithmetic and energy efficient embedded signal processing.	CASES	2006	DBLP DOI BibTeX RDF	PCMOS, probabilistic arithmetic, low power, DSP, probabilistic computing
1	Rachid Seghir, Vincent Loechner	Memory optimization by counting points in integer transformations of parametric polytopes.	CASES	2006	DBLP DOI BibTeX RDF	array linearization, cache access optimization, counting lattice points in polytopes, exact memory size computation, polytope model
1	Stephen Hines, David B. Whalley, Gary S. Tyson	Adapting compilation techniques to enhance the packing of instructions into registers.	CASES	2006	DBLP DOI BibTeX RDF	instruction packing, instruction register file, compiler optimizations
1	Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian	Mitigating soft error failures for multimedia applications by selective data protection.	CASES	2006	DBLP DOI BibTeX RDF	horizontally partitioned caches, multimedia embedded systems, selective data protection, soft errors
1	Joel Coburn, Srivaths Ravi 0001, Anand Raghunathan, Srimat T. Chakradhar	SECA: security-enhanced communication architecture.	CASES	2005	DBLP DOI BibTeX RDF	AMBA Bus, security-aware design, small embedded systems, security, communication, access control, architecture, intrusion detection, system-on-chip (SoC), attacks, bus, digital rights management (DRM)
1	Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero	Architectural support for real-time task scheduling in SMT processors.	CASES	2005	DBLP DOI BibTeX RDF	scheduling, real time, multithreading, performance predictability, ILP, thread-level parallelism, SMT
1	A. Goel, C. Mani Krishna 0001, Israel Koren	Energy aware kernel for hard real-time systems.	CASES	2005	DBLP DOI BibTeX RDF	embedded system, dynamic voltage scaling, earliest deadline first, real-time operating system, eCos
1	Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt	Compilation techniques for energy reduction in horizontally partitioned cache architectures.	CASES	2005	DBLP DOI BibTeX RDF	XScale, horizontally-partitioned cache, mini-cache, split cache, compiler, energy, data cache
1	Sitij Agrawal, William Thies, Saman P. Amarasinghe	Optimizing stream programs using linear state space analysis.	CASES	2005	DBLP DOI BibTeX RDF	linear state space systems, embedded, synchronous dataflow, stream programing, streamit
1	Michael Wolfe	How compilers and tools differ for embedded systems.	CASES	2005	DBLP DOI BibTeX RDF
1	Ali El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg	Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing.	CASES	2005	DBLP DOI BibTeX RDF	worst-case execution time, schedulability analysis, superscalar processor, simultaneous multithreading, hard real-time, resource partitioning
1	Thomas M. Conte, Paolo Faraboschi, William H. Mangione-Smith, Walid A. Najjar (eds.)	Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005	CASES	2005	DBLP BibTeX RDF
1	Matthew D. Roper, Ronald A. Olsson	Developing embedded multi-threaded applications with CATAPULTS, a domain-specific language for generating thread schedulers.	CASES	2005	DBLP DOI BibTeX RDF	application-specific schedulers, domain-specific languages, thread scheduling, user-level threads
1	Matthew S. Simpson, Bhuvan Middha, Rajeev Barua	Segment protection for embedded systems using run-time checks.	CASES	2005	DBLP DOI BibTeX RDF	MMU, MPU, ewmbedded systems, safe languages, segment protection, segmentation violations, reliability, compilers, virtual memory, memory safety, run-time checks
1	Montserrat Ros, Peter Sutton	A post-compilation register reassignment technique for improving hamming distance code compression.	CASES	2005	DBLP DOI BibTeX RDF	register reassignment, hamming distance, code compression
1	Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung	Automating custom-precision function evaluation for embedded processors.	CASES	2005	DBLP DOI BibTeX RDF	embedded systems, reconfigurable computing, fixed-point arithmetic, function evaluation
1	Siddhartha Shivshankar, Sunil Vangara, Alexander G. Dean	Balancing register pressure and context-switching delays in ASTI systems.	CASES	2005	DBLP DOI BibTeX RDF	asynchronous software thread integration, software-implemented-communication protocols, hardware to software migration, fine-grain concurrency
1	Guangyu Chen, Mahmut T. Kandemir	Verifiable annotations for embedded java environments.	CASES	2005	DBLP DOI BibTeX RDF	verification, annotation, java virtual machine, just-in-time compilation, flow analysis
1	Milena Milenkovic, Aleksandar Milenkovic, Emil Jovanov	Hardware support for code integrity in embedded processors.	CASES	2005	DBLP DOI BibTeX RDF	attacks, code integrity, code injection
1	Sami Yehia, Nathan Clark, Scott A. Mahlke, Krisztián Flautner	Exploring the design space of LUT-based transparent accelerators.	CASES	2005	DBLP DOI BibTeX RDF	accelerator design, embedded processing, efficient computation
1	Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David T. Blaauw	A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution.	CASES	2005	DBLP DOI BibTeX RDF	sensor network, energy efficiency, microprocessor, memory organization
1	Rony Ghattas, Alexander G. Dean	Energy management for commodity short-bit-width microcontrollers.	CASES	2005	DBLP DOI BibTeX RDF	dynamic frequency scaling, short-bit-width microcontroller, embedded systems, dynamic voltage scaling, energy modeling
1	Nghi Nguyen, Angel Dominguez, Rajeev Barua	Memory allocation for embedded systems with a compile-time-unknown scratch-pad size.	CASES	2005	DBLP DOI BibTeX RDF	data linked list, downloadable codes, embedded loading, embedded systems, compiler, memory allocation, scratch-pad
1	Hyunok Oh, Nikil D. Dutt, Soonhoi Ha	Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs.	CASES	2005	DBLP DOI BibTeX RDF	automatic code synthesis, dynamic loop count, single appearance schedule, memory optimization, synchronous dataflow
1	Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan	The microarchitecture of FPGA-based soft processors.	CASES	2005	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, application specic tradeoff, FPGA, pipeline, exploration, embedded processor, ASIP, microarchitecture, soft processor
1	Hyunseok Lee, Trevor N. Mudge	A dual-processor solution for the MAC layer of a software defined radio terminal.	CASES	2005	DBLP DOI BibTeX RDF	SDR terminal, wireless platform, protocol processing
1	Suman Mamidi, Emily R. Blem, Michael J. Schulte, C. John Glossner, Daniel Iancu, Andrei Iancu, Mayan Moudgill, Sanjay Jinturkar	Instruction set extensions for software defined radio on a multithreaded processor.	CASES	2005	DBLP DOI BibTeX RDF	convolutional encoding, multithreading, forward error correction, software defined radio, Reed-Solomon coding, instruction set extensions, digital signal processor, Viterbi decoding, turbo decoding
1	Mohammad Ali Ghodrat, Tony Givargis, Alexandru Nicolau	Equivalence checking of arithmetic expressions using fast evaluation.	CASES	2005	DBLP DOI BibTeX RDF	expression equivalence, mutual exclusion, interval analysis
1	Laura Pozzi, Paolo Ienne	Exploiting pipelining to relax register-file port constraints of instruction-set extensions.	CASES	2005	DBLP DOI BibTeX RDF	automatic instruction-set extension, constrained scheduling, embedded customised architectures, multi-cycle register access, input/output
1	Thomas Y. Yeh, Glenn Reinman	Fast and fair: data-stream quality of service.	CASES	2005	DBLP DOI BibTeX RDF	NUCA, non-uniform access, per thread degradation, cluster, adaptive, cache, distributed, data-stream, partition, embedded, CMP, chip multiprocessor, migration, bandwidth, QOS, phase, memory wall, PDAS
1	Vassos Soteriou, Noel Eisley, Li-Shiuan Peh	Software-directed power-aware interconnection networks.	CASES	2005	DBLP DOI BibTeX RDF	dynamic voltage, networks on-a-chip (NoC), software-directed power reduction, simulation, interconnection networks, scaling, communication links
1	Xin Li 0020, Jan Lukoschus, Marian Boldt, Michael Harder, Reinhard von Hanxleden	An Esterel processor with full preemption support and its worst case reaction time analysis.	CASES	2005	DBLP DOI BibTeX RDF	reaction time analysis, reactive processing, WCET, synchronous languages, Esterel
1	Feihui Li, Guangyu Chen, Mahmut T. Kandemir, Mary Jane Irwin	Compiler-directed proactive power management for networks.	CASES	2005	DBLP DOI BibTeX RDF	low power, network, compiler, proactive
1	Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia	Micro embedded monitoring for security in application specific instruction-set processors.	CASES	2005	DBLP DOI BibTeX RDF	micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring
1	Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal	Intra-task scenario-aware voltage scheduling.	CASES	2005	DBLP DOI BibTeX RDF	dynamic voltage scheduling, real-time, scenarios, WCET
1	Bhuvan Middha, Matthew S. Simpson, Rajeev Barua	MTSS: multi task stack sharing for embedded systems.	CASES	2005	DBLP DOI BibTeX RDF	cactus stack, meshed stack, out-of-memory, reliability, reuse, runtime checks, heap overflow, stack overflow
1	Tao Zhang 0037, Xiaotong Zhuang, Santosh Pande, Wenke Lee	Anomalous path detection with hardware support.	CASES	2005	DBLP DOI BibTeX RDF	anomalous path, control flow monitoring, monitoring granularity, anomaly detection, hardware support
1	Bramha Allu, Wei Zhang 0002	Static next sub-bank prediction for drowsy instruction cache.	CASES	2004	DBLP DOI BibTeX RDF	compiler, instruction cache, leakage energy
1	Mary Jane Irwin, Wei Zhao, Luciano Lavagno, Scott A. Mahlke (eds.)	Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004	CASES	2004	DBLP BibTeX RDF
1	Ravishankar Rao, Sarma B. K. Vrudhula, Musaravakkam S. Krishnan	Disk drive energy optimization for audio-video applications.	CASES	2004	DBLP DOI BibTeX RDF	multimedia, low power, disk drive, speed control
1	Giovanni Beltrame, Gianluca Palermo, Donatella Sciuto, Cristina Silvano	Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs.	CASES	2004	DBLP DOI BibTeX RDF	multiprocessor, network on chip, low-power design, platform based design
1	Pan Yu, Tulika Mitra	Scalable custom instructions identification for instruction-set extensible processors.	CASES	2004	DBLP DOI BibTeX RDF	subgraph enumeration algorithm, ASIPs, instruction-set extensions, customizable processors
1	Sven Verdoolaege, Rachid Seghir, Kristof Beyls, Vincent Loechner, Maurice Bruynooghe	Analytical computation of Ehrhart polynomials: enabling more compiler analyses and optimizations.	CASES	2004	DBLP DOI BibTeX RDF	Barvinok's decomposition, Ehrhart polynomial, parametric polytope, quasi-polynomial, signed unimodular decomposition, polyhedral model, compiler analysis
1	Timothy Sherwood, Mark Oskin, Brad Calder	Balancing design options with Sherpa.	CASES	2004	DBLP DOI BibTeX RDF	peicewise linear model, computer architecture, design space exploration, application specific processor (ASIP), area minimization
1	Steve Carr 0001, Philip H. Sweany	Automatic data partitioning for the agere payload plus network processor.	CASES	2004	DBLP DOI BibTeX RDF	scheduling, partitioning, network processors
1	Xiaotong Zhuang, Tao Zhang 0037, Hsien-Hsin S. Lee, Santosh Pande	Hardware assisted control flow obfuscation for embedded processors.	CASES	2004	DBLP DOI BibTeX RDF	obfuscation, control flow graph
1	Surupa Biswas, Matthew S. Simpson, Rajeev Barua	Memory overflow protection for embedded systems using run-time checks, reuse and compression.	CASES	2004	DBLP DOI BibTeX RDF	out-of-memory errors, reliability, data compression, reuse, runtime checks, heap overflow, stack overflow
1	David Berner, Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla	Modular design through component abstraction.	CASES	2004	DBLP DOI BibTeX RDF	behavioral interfaces, synchronous languages, component based design
1	Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede	Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques.	CASES	2004	DBLP DOI BibTeX RDF	security, java, design, embedded systems, cryptography
1	Ali El-Haj-Mahmoud, Eric Rotenberg	Safely exploiting multithreaded processors to tolerate memory latency in real-time systems.	CASES	2004	DBLP DOI BibTeX RDF	real-time systems, multithreading, worst-case execution time, memory latency, schedulability test
1	Jesus Garcia, Mark G. Arnold, Leonidas G. Bleris, Mayuresh V. Kothare	LNS architectures for embedded model predictive control processors.	CASES	2004	DBLP DOI BibTeX RDF	FWL, cotransformation, reduced precision, LNS, MPC
1	Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha	General loop fusion technique for nested loops considering timing and code size.	CASES	2004	DBLP DOI BibTeX RDF	embedded DSP, scheduling, retiming, code size, loop fusion
1	Linwei Niu, Gang Quan	Reducing both dynamic and leakage energy consumption for hard real-time systems.	CASES	2004	DBLP DOI BibTeX RDF	embedded system, low power design, DVS, real-time scheduling, leakage power reduction
1	Ken W. Batcher, Robert A. Walker 0001	Cluster miss prediction with prefetch on miss for embedded CPU instruction caches.	CASES	2004	DBLP DOI BibTeX RDF	hiding memory latency, embedded systems, networking, WCET, cache design, cache prefetch
1	Christophe Guillon, Fabrice Rastello, Thierry Bidault, Florent Bouchez	Procedure placement using temporal-ordering information: dealing with code size expansion.	CASES	2004	DBLP DOI BibTeX RDF	min-matching, profiling, instruction cache, Hamiltonian-path, cache miss, code size, code placement
1	Mary Kiemb, Kiyoung Choi	Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems.	CASES	2004	DBLP DOI BibTeX RDF	embedded systems, design space exploration, simultaneous multithreading, SMT
1	Klaus Schneider 0001, Jens Brandt 0001, Tobias Schüle	Causality analysis of synchronous programs with delayed actions.	CASES	2004	DBLP DOI BibTeX RDF	causality, synchronous languages, ternary logic, fixpoints
1	Wei Zhang 0002, Bramha Allu	Loop-based leakage control for branch predictors.	CASES	2004	DBLP DOI BibTeX RDF	compiler, branch prediction, leakage energy
1	John Cornish	Balanced energy optimization.	CASES	2004	DBLP DOI BibTeX RDF
1	Binu K. Mathew, Al Davis, Michael A. Parker	A low power architecture for embedded perception.	CASES	2004	DBLP DOI BibTeX RDF	computer vision, embedded systems, speech recognition, perception, low power design, VLIW, stream processor
1	Vasanth Asokan, Alexander G. Dean	Providing time- and space- efficient procedure calls for asynchronous software thread integration.	CASES	2004	DBLP DOI BibTeX RDF	asynchronous software thread integration, software-implemented communication protocol controllers, hardware to software migration, fine-grain concurrency
1	Ramakrishnan Venkitaraman, Gopal Gupta 0001	Static program analysis of embedded executable assembly code.	CASES	2004	DBLP DOI BibTeX RDF	embedded software components, executable code, static analysis, abstract interpretation, assembly code
1	Noel Eisley, Li-Shiuan Peh	High-level power analysis for on-chip networks.	CASES	2004	DBLP DOI BibTeX RDF	simulation, power analysis, systems-on-a-chip (SoC), link utilization
1	Shaoxiong Hua, Gang Qu 0001	Energy-efficient dual-voltage soft real-time system with (m, k)-firm deadline guarantee.	CASES	2004	DBLP DOI BibTeX RDF	(m, k)-firm, low-power, dynamic voltage scaling, soft real-time
1	Kees A. Vissers	Programming models and architectures for FPGA platforms.	CASES	2004	DBLP DOI BibTeX RDF
1	Valentina Salapura, Christos J. Georgiou, Indira Nair	An efficient system-on-a-chip design methodology for networking applications.	CASES	2004	DBLP DOI BibTeX RDF	network processor, system-on-a-chip
1	Montserrat Ros, Peter Sutton	A hamming distance based VLIW/EPIC code compression technique.	CASES	2004	DBLP DOI BibTeX RDF	VLIW, hamming distance, code compression
1	Mahmut T. Kandemir, Ozcan Ozturk 0001, Mustafa Karaköy	Dynamic on-chip memory management for chip multiprocessors.	CASES	2004	DBLP DOI BibTeX RDF	chip multiprocessors, optimizing compiler, memory bank
1	Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere	Translating affine nested-loop programs to process networks.	CASES	2004	DBLP DOI BibTeX RDF	integer linear programming, process networks, heterogeneous embedded systems
1	Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T. Kandemir	Reducing energy consumption of queries in memory-resident database systems.	CASES	2004	DBLP DOI BibTeX RDF	hardware schemes, query-directed energy management, database, mapping, query optimization, energy, power consumption, layouts, DRAM
1	Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri	A post-compiler approach to scratchpad mapping of code.	CASES	2004	DBLP DOI BibTeX RDF	executable patching, post-compiler processing, dynamic programming, memory hierarchy, optimization algorithm, design automation, power saving, scratchpad memory, embedded design
1	Rajeev Krishna, Scott A. Mahlke, Todd M. Austin	Architectural optimizations for low-power, real-time speech recognition.	CASES	2003	DBLP DOI BibTeX RDF
1	Guilin Chen, Mahmut T. Kandemir, Hendra Saputra, Mary Jane Irwin	Exploiting bank locality in multi-bank memories.	CASES	2003	DBLP DOI BibTeX RDF	affine program, bank locality, embedded systems, energy consumption, optimizing compilers
1	Partha Biswas, Nikil D. Dutt	Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions.	CASES	2003	DBLP DOI BibTeX RDF	dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment
1	Andrei Sergeevich Terechko, Erwan Le Thenaff, Henk Corporaal	Cluster assignment of global values for clustered VLIW processors.	CASES	2003	DBLP DOI BibTeX RDF	compiler, register allocation, VLIW, instruction scheduler, ILP, cluster assignment
1	Alain Darte, Robert Schreiber, Gilles Villard	Lattice-based memory allocation.	CASES	2003	DBLP DOI BibTeX RDF	admissible lattice, critical determinant, successive minima, program transformation, memory allocation
1	Chidamber Kulkarni, Matthias Gries, Christian Sauer 0001, Kurt Keutzer	Programming challenges in network processor deployment.	CASES	2003	DBLP DOI BibTeX RDF	IPv4 forwarding, programming heterogeneous architectures, mapping, programming model, multi-threading, resource sharing
1	Wei Zhang 0002, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin	Performance, energy, and reliability tradeoffs in replicating hot cache lines.	CASES	2003	DBLP DOI BibTeX RDF	cache reliability, line replication, cache memories, leakage power
1	Binu K. Mathew, Al Davis, Zhen Fang 0002	A low-power accelerator for the SPHINX 3 speech recognition system.	CASES	2003	DBLP DOI BibTeX RDF	embedded systems, speech recognition, low power design, ASIC, special purpose hardware
1	Andreas Ermedahl, Friedhelm Stappert, Jakob Engblom	Clustered calculation of worst-case execution times.	CASES	2003	DBLP DOI BibTeX RDF	WCET calculation, embedded systems, hard real-time, WCET analysis
1	Benjamin J. Welch, Shobhit O. Kanaujia, Adarsh Seetharam, Deepaksrivats Thirumalai, Alexander G. Dean	Extending STI for demanding hard-real-time systems.	CASES	2003	DBLP DOI BibTeX RDF	AVR, NTSC video, STIGLitz, post-pass compiler, embedded systems, hardware-to-software migration, fine-grain concurrency, software thread integration
1	Dorit Naishlos, Marina Biberstein, Shay Ben-David, Ayal Zaks	Vectorizing for a SIMdD DSP architecture.	CASES	2003	DBLP DOI BibTeX RDF	compiler controlled cache, rotating register file, SIMD, vectorization, data reuse, subword parallelism, viterbi
1	Joseph A. Fisher	Moving from embedded systems to embedded computing.	CASES	2003	DBLP DOI BibTeX RDF
1	Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown	Increasing the number of effective registers in a low-power processor using a windowed register file.	CASES	2003	DBLP DOI BibTeX RDF	window assignment, low-power, graph partitioning, embedded processor, instruction encoding, register window
1	Hillery C. Hunter, Jaime H. Moreno	A new look at exploiting data parallelism in embedded systems.	CASES	2003	DBLP DOI BibTeX RDF	sub-word parallelism, architecture, embedded, DSP, telecommunications, SIMD, VLIW, processor, ILP, media, DLP, data-level parallelism
1	Federico Angiolini, Luca Benini, Alberto Caprara	Polynomial-time algorithm for on-chip scratchpad memory partitioning.	CASES	2003	DBLP DOI BibTeX RDF	dynamic programming, memory hierarchy, design automation, power saving, scratchpad memory, partitioning algorithm, embedded design
1	Juanjo Noguera, Rosa M. Badia	System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures.	CASES	2003	DBLP DOI BibTeX RDF	reconfigurable computing, dynamic scheduling, clock-gating, frequency scaling, power-performance trade-offs
1	David Goodwin, Darin Petkov	Automatic generation of application specific processors.	CASES	2003	DBLP DOI BibTeX RDF	automatic instruction-set generation, ASIPs, configurable processors, extensible processors
1	Montserrat Ros, Peter Sutton	Compiler optimization and ordering effects on VLIW code compression.	CASES	2003	DBLP DOI BibTeX RDF	compiler optimizations, VLIW, code compression
1	Peter Poplavko, Twan Basten, Marco Bekooij, Jef L. van Meerbergen, Bart Mesman	Task-level timing models for guaranteed performance in multiprocessor networks-on-chip.	CASES	2003	DBLP DOI BibTeX RDF	buffer minimization, performance evaluation, real-time, system-on-chip, network-on-chip, data flow graph
1	V. Krishna Nandivada, Jens Palsberg	Efficient spill code for SDRAM.	CASES	2003	DBLP DOI BibTeX RDF	optimization, integer linear programming, SDRAM, memory layout
1	Ann Gordon-Ross, Frank Vahid	Frequent loop detection using efficient non-intrusive on-chip hardware.	CASES	2003	DBLP DOI BibTeX RDF	frequent loop detection, frequent value profiling, hardware profiling, hot spot detection, on-chip profiling, runtime profiling, dynamic optimization
1	Dino Oliva, Rainer Buchty, Nevin Heintze	AES and the cryptonite crypto processor.	CASES	2003	DBLP DOI BibTeX RDF	round key generation, architecture, cryptography, AES, processor, high-speed, software implementation, high-bandwidth
1	Krishna V. Palem	Energy aware algorithm design via probabilistic computing: from algorithms and models to Moore's law and novel (semiconductor) devices.	CASES	2003	DBLP DOI BibTeX RDF
1	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar, Laxmi N. Bhuyan	Power efficient encoding techniques for off-chip data buses.	CASES	2003	DBLP DOI BibTeX RDF	FV, FV-MSB-LSB, data bus, low power, bus encoding
1	Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Bruce L. Jacob	A control-theoretic approach to dynamic voltage scheduling.	CASES	2003	DBLP DOI BibTeX RDF	nqPID, low-power, dynamic voltage scaling, PID
1	Jaime H. Moreno, Praveen K. Murthy, Thomas M. Conte, Paolo Faraboschi (eds.)	Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003	CASES	2003	DBLP BibTeX RDF
1	Bengu Li, Rajiv Gupta 0001	Simple offset assignment in presence of subword data.	CASES	2003	DBLP DOI BibTeX RDF	SWOA, subword data, SOA, storage assignment
1	Ramnath Venugopalan, Prasanth Ganesan, Pushkin Peddabachagari, Alexander G. Dean, Frank Mueller 0001, Mihail L. Sichitiu	Encryption overhead in embedded systems and sensor network nodes: modeling and analysis.	CASES	2003	DBLP DOI BibTeX RDF	security, sensor networks, embedded systems, encryption
1	Sumesh Udayakumaran, Rajeev Barua	Compiler-decided dynamic memory allocation for scratch-pad based embedded systems.	CASES	2003	DBLP DOI BibTeX RDF	embedded systems, compiler, memory allocation, scratch-pad

Publications at "CASES"( http://dblp.L3S.de/Venues/CASES )