| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Daryl Stewart |
Formal for everyone - Challenges in achievable multicore design and verification.  |
FMCAD  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Dirk Beyer 0001, Philipp Wendler |
Algorithms for software model checking: Predicate abstraction vs. Impact. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Magnus O. Myreen, Michael J. C. Gordon, Konrad Slind |
Decompilation into logic - Improved. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Yang Yang, Lei Bu, Xuandong Li |
Forward and backward: Bounded model checking of linear hybrid automata from two directions. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Brian Keng, Andreas G. Veneris |
Automated debugging of missing input constraints in a formal verification environment. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Eric Feron |
Formal methods for aerospace applications. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Jiazhao Xu, Mark Williams, Hari Mony, Jason Baumgartner |
Enhanced reachability analysis via automated dynamic netlist-based hint generation. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Alessandro Cimatti, Iman Narasamdya, Marco Roveri |
Verification of parametric system designs. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Koen Claessen, Niklas Sörensson |
A liveness checking algorithm that counts. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Alexey Lvov, Luis Alfonso Lastras-Montaño, Viresh Paruthi, Robert Shadowen, Ali El-Zein |
Formal verification of error correcting circuits using computational algebraic geometry. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Eugene Goldberg, Panagiotis Manolios |
Quantifier elimination by Dependency Sequents. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Rohit Sinha 0001, Cynthia Sturton, Petros Maniatis, Sanjit A. Seshia, David A. Wagner 0001 |
Verification with small and short worlds. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Leopold Haller, Alberto Griggio, Martin Brain, Daniel Kroening |
Deciding floating-point logic with systematic abstraction. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Alessandro Cimatti |
Application of SMT solvers to hybrid system verification. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Yan Zhang 0027, Sriram Sankaranarayanan 0001, Fabio Somenzi |
Piecewise linear modeling of nonlinear devices for formal verification of analog circuits. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | V. M. Achutha KiranKumar, Aarti Gupta, Rajnish Ghughal |
Symbolic Trajectory Evaluation: The primary validation Vehicle for next generation Intel® Processor Graphics FPU. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Arnab Sinha, Sharad Malik, Aarti Gupta |
Efficient predictive analysis for detecting nondeterminism in multi-threaded programs. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Yakir Vizel, Orna Grumberg, Sharon Shoham |
Lazy abstraction and SAT-based reachability in hardware model checking. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Jason Baumgartner, Alexander Ivrii, Arie Matsliah, Hari Mony |
IC3-guided abstraction. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Warren A. Hunt Jr., Matt Kaufmann |
A formal model of a large memory that supports efficient execution. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Rüdiger Ehlers, Robert Könighofer, Georg Hofferek |
Symbolically synthesizing small circuits. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler |
Complete and effective robustness checking by means of interpolation. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Vineet Kahlon |
Automatic lock insertion in concurrent programs. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Gianpiero Cabodi, Satnam Singh (eds.) |
Formal Methods in Computer-Aided Design, FMCAD 2012, Cambridge, UK, October 22-25, 2012 |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Alessandro Cimatti, Sergio Mover, Stefano Tonetta |
A quantifier-free SMT encoding of non-linear hybrid automata. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Jasmin Fisher |
Formal methods in cell Biology. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Parosh Aziz Abdulla, Mohamed Faouzi Atig, Othmane Rezine, Jari Stenman |
Multi-pushdown systems with budgets. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Krystof Hoder, Zurab Khasidashvili, Konstantin Korovin, Andrei Voronkov |
Preprocessing techniques for first-order clausification. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Torsten Schaub |
Answer Set Programming. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Tony Hoare |
Algebra of concurrent design. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Chao Yan 0001, Mark R. Greenstreet |
Oscillator verification with probability one. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Ondrej Sery, Grigory Fedyukovich, Natasha Sharygina |
Incremental upgrade checking by means of interpolation-based function summaries. |
FMCAD |
2012 |
DBLP BibTeX RDF |
|
| 1 | Muralidhar Talupur |
Hardware model checking: status, challenges, and opportunities. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Umair Siddique, Osman Hasan |
Formal analysis of fractional order systems in HOL. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Kenneth L. McMillan |
Interpolants from Z3 proofs. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Per Bjesse, Anna Slobodová (eds.) |
International Conference on Formal Methods in Computer-Aided Design, FMCAD '11, Austin, TX, USA, October 30 - November 02, 2011 |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Anton Belov, João Marques-Silva 0001 |
Accelerating MUS extraction with recursive model rotation. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Alessandro Cimatti, Sergio Mover, Stefano Tonetta |
Proving and explaining the unfeasibility of message sequence charts for hybrid systems. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Jayanand Asok Kumar, Lingyi Liu, Shobha Vasudevan |
Scaling probabilistic timing verification of hardware using abstractions in design source code. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Brad D. Bingham, Mark R. Greenstreet, Jesse D. Bingham |
Parameterized verification of deadlock freedom in symmetric cache coherence protocols. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Charlie Shucheng Zhu, Georg Weissenbacher, Sharad Malik |
Post-silicon fault localisation using maximum satisfiability and backbones. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | John Hughes |
Specification based testing with QuickCheck: tutorial talk. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Fabio Somenzi, Aaron R. Bradley |
IC3: where monolithic and incremental meet. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Steven M. German |
A theory of abstraction for arrays. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Sudarshan K. Srinivasan, Raj S. Katti |
Desynchronization: design for verification. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Jonathan Kotker, Dorsa Sadigh, Sanjit A. Seshia |
Timing analysis of interrupt-driven programs under context bounds. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Harsh Raju Chamarthi, Panagiotis Manolios |
Automated specification analysis using an interactive theorem prover. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Bryan A. Brady, Randal E. Bryant, Sanjit A. Seshia |
Learning conditional abstractions. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | John Havlicek, Scott Little |
Realtime regular expressions for analog and mixed-signal assertions. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | J Strother Moore |
The role of human creativity in mechanized verification: invited talk. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Niklas Eén, Alan Mishchenko, Robert K. Brayton |
Efficient implementation of property directed reachability. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Alberto Griggio |
Effective word-level interpolation for software verification. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Aaron R. Bradley, Fabio Somenzi, Zyad Hassan, Yan Zhang 0027 |
An incremental approach to model checking progress properties. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Lee Pike |
Pervasive formal verification in control system design. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Michael L. Case, Jason Baumgartner, Hari Mony, Robert Kanzelman |
Approximate reachability with combined symbolic and ternary simulation. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Sagar Chaki, Arie Gurfinkel, Ofer Strichman |
Time-bounded analysis of real-time systems. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Panagiotis Manolios, Vasilis Papavasileiou |
Pseudo-Boolean Solving by incremental translation to SAT. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Michael L. Case, Jason Baumgartner, Hari Mony, Robert Kanzelman |
Optimal redundancy removal without fixedpoint computation. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Louis Mandel, Florence Plateau, Marc Pouzet |
Static scheduling of latency insensitive designs with Lucy-n. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Aarti Gupta |
Verifying concurrent programs: tutorial talk. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Jun Sawada, Peter Sandon, Viresh Paruthi, Jason Baumgartner, Michael L. Case, Hari Mony |
Hybrid verification of a hardware modular reduction engine. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Prashant Aggarwal, Darrow Chu, Vijay Kadamby, Vigyan Singhal |
Planning for end-to-end formal using simulation-based coverage: invited tutorial. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Mohamed Abdul Basith, Tariq B. Ahmad, André Rossi, Maciej J. Ciesielski |
Algebraic approach to arithmetic design verification. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Robert Könighofer, Roderick Bloem |
Automated error localization and correction for imperative programs. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Freek Verbeek, Julien Schmaltz |
Hunting deadlocks efficiently in microarchitectural models of communication fabrics. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Ivan E. Sutherland |
Self-timing: a step beyond synchrony (tutorial talk). |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Hana Chockler, Alexander Ivrii, Arie Matsliah, Shiri Moran, Ziv Nevo |
Incremental formal verification of hardware. |
FMCAD |
2011 |
DBLP BibTeX RDF |
|
| 1 | Christoph M. Wintersteiger, Youssef Hamadi, Leonardo Mendonça de Moura |
Efficiently solving quantified bit-vector formulas. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Warren A. Hunt Jr. |
Verifying VIA Nano microprocessor components. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Joseph Sifakis |
Embedded systems design - Scientific challenges and work directions. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Malay K. Ganai |
Propelling SAT and SAT-based BMC using careset. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Thomas Ball, Ella Bounimova, Rahul Kumar 0002, Vladimir Levin |
SLAM2: Static driver verification with under 4% false alarms. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Viresh Paruthi |
Large-scale application of formal verification: From fiction to fact. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Nishant Sinha 0001 |
Modular bug detection with inertial refinement. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Massimo Roselli |
Impacting verification closure using formal analysis. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Michael Kuperstein 0001, Martin T. Vechev, Eran Yahav |
Automatic inference of memory fences. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, Alexander Nadel |
SAT-based semiformal verification of hardware. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Michael Siegel |
Achieving earlier verification closure using advanced formal verification. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | ShengYu Shen, Ying Qin, Jianmin Zhang, Sikun Li |
A halting algorithm to determine the existence of decoder. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Hana Chockler |
PINCETTE - Validating changes and upgrades in networked software. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Anders Franzén, Alessandro Cimatti, Alexander Nadel, Roberto Sebastiani, Jonathan Shalev |
Applying SMT in symbolic execution of microcode. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Niklas Eén, Alan Mishchenko, Nina Amla |
A single-instance incremental SAT formulation of proof- and counterexample-based abstraction. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jason Baumgartner, Michael L. Case, Hari Mony |
Coping with Moore's Law (and more): Supporting arrays in state-of-the-art model checkers. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Jun Sawada |
Automatic verification of estimate functions with polynomials of bounded functions. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Alexander Nadel |
Boosting minimal unsatisfiable core extraction. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Sumit Gulwani |
Dimensions in program synthesis. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Alessandro Cimatti, Andrea Micheli, Iman Narasamdya, Marco Roveri |
Verifying SystemC: A software model checking approach. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Joakim Urdahl, Dominik Stoffel, Jörg Bormann, Markus Wedler, Wolfgang Kunz |
Path predicate abstraction by complete interval property checking. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Peter Böhm |
A framework for incremental modelling and verification of on-chip protocols. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | B. A. Krishna, Anamaya Sullerey, Alok Jain |
Formal verification of an ASIC ethernet switch block. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Dirk Beyer 0001, M. Erkan Keremoglu, Philipp Wendler |
Predicate abstraction with adjustable-block encoding. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow |
Automated formal verification of processors based on architectural models. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Lopamudra Sen, Amit Roy, Supriya Bhattacharjee, Bijitendra Mittra, Subir K. Roy |
DFT logic verification through property based formal methods - SOC to IP. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Saddek Bensalem, Marius Bozga, Axel Legay, Thanh-Hung Nguyen, Joseph Sifakis, Rongjie Yan |
Incremental component-based construction and verification using invariants. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Eyad Alkassar, Ernie Cohen, Mark A. Hillebrand, Mikhail Kovalev, Wolfgang J. Paul |
Verifying shadow page table algorithms. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Vineet Kahlon, Weihong Li, Naoto Maeda, Nadia Papakonstantinou, Sriram Sankaranarayanan 0001, Nishant Sinha 0001, Chao Wang 0001 |
Scalable and precise program analysis at NEC. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Leopold Haller, Satnam Singh |
Relieving capacity limits on FPGA-based SAT-solvers. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Johannes Kinder, Helmut Veith |
Precise static analysis of untrusted driver binaries. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Eyad Alkassar, Ernie Cohen, Mark A. Hillebrand, Hristo Pentchev |
Modular specification and verification of interprocess communication. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
| 1 | Moshe Emmer, Zurab Khasidashvili, Konstantin Korovin, Andrei Voronkov |
Encoding industrial hardware verification problems into effectively propositional logic. |
FMCAD |
2010 |
DBLP BibTeX RDF |
|
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