Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Jason Helge Anderson, Kia Bazargan (eds.)	Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018	FPGA	2018	DBLP DOI BibTeX RDF
1	Shuo Wang 0009, Zhe Li 0001, Caiwen Ding, Bo Yuan 0001, Qinru Qiu, Yanzhi Wang, Yun Liang 0001	C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAs.	FPGA	2018	DBLP DOI BibTeX RDF
1	Jialiang Zhang, Jing Li 0073	Degree-aware Hybrid Graph Traversal on FPGA-HMC Platform.	FPGA	2018	DBLP DOI BibTeX RDF
1	Chang Gao 0002, Daniel Neil, Enea Ceolini, Shih-Chii Liu, Tobi Delbrück	DeltaRNN: A Power-efficient Recurrent Neural Network Accelerator.	FPGA	2018	DBLP DOI BibTeX RDF
1	Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne	LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Zheming Jin, Hal Finkel	Evaluation of OpenCL Performance-oriented Optimizations for Streaming Kernels on the FPGA: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Mikhail Asiatici, Damian Maiorano, Paolo Ienne	FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS5)(Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Greg Stitt, Abhay Gupta, Madison N. Emas, David Wilson 0004, Austin Baylis	Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems.	FPGA	2018	DBLP DOI BibTeX RDF
1	Weikang Qiao, Jieqiong Du, Zhenman Fang, Libo Wang, Michael Lo, Mau-Chung Frank Chang, Jason Cong	High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Zhe Chen, Andrew Howe, Hugh T. Blair, Jason Cong	FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Steve Dai, Gai Liu, Zhiru Zhang	A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation.	FPGA	2018	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato	A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA.	FPGA	2018	DBLP DOI BibTeX RDF
1	Wentai Zhang 0001, Jiaxi Zhang 0001, Minghua Shen, Nong Xiao, Guojie Luo	Mapping Large-Scale DNNs on Asymmetric FPGAs: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Shijie Zhou 0001, Rajgopal Kannan, Yu Min, Viktor K. Prasanna	FASTCF: FPGA-based Accelerator for STochastic-Gradient-Descent-based Collaborative Filtering.	FPGA	2018	DBLP DOI BibTeX RDF
1	Xiaoyu Yu, Dong Ye 0005	Performance Comparison of Multiples and Target Detection with Imager-driven Processing Mode for Ultrafast-Imager: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Martin Langhammer, Bogdan Pasca 0001	High-Performance QR Decomposition for FPGAs.	FPGA	2018	DBLP DOI BibTeX RDF
1	Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, Li Jiang 0002	A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Bita Darvish Rouhani, Mohammad Ghasemzadeh 0002, Farinaz Koushanfar	CausaLearn: Automated Framework for Scalable Streaming-based Causal Bayesian Learning using FPGAs.	FPGA	2018	DBLP DOI BibTeX RDF
1	Lana Josipovic, Radhika Ghosal, Paolo Ienne	Dynamically Scheduled High-level Synthesis.	FPGA	2018	DBLP DOI BibTeX RDF
1	Matej Bartík, Sven Ubik, Pavel Kubalík, Tomás Benes	Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Gai Liu, Ecenur Ustun, Shaojie Xiang, Chang Xu 0005, Guojie Luo, Zhiru Zhang	DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis	Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Sean Fox, David Boland, Philip Heng Wai Leong	FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method.	FPGA	2018	DBLP DOI BibTeX RDF
1	Yue Zha, Jing Li 0073	Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM Technology.	FPGA	2018	DBLP DOI BibTeX RDF
1	Chongchong Xu, Chao Wang 0003, Yiwei Zhang 0001, Lei Gong, Xi Li 0003, Xuehai Zhou	Domino: An Asynchronous and Energy-efficient Accelerator for Graph Processing: (Abstract Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Ruizhe Zhao, Xinyu Niu, Wayne Luk	Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only).	FPGA	2018	DBLP DOI BibTeX RDF
1	Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton	Architecture Exploration for HLS-Oriented FPGA Debug Overlays.	FPGA	2018	DBLP DOI BibTeX RDF
1	Yuan Zhou, Khalid Musa Al-Hawaj, Zhiru Zhang	A New Approach to Automatic Memory Banking using Trace-Based Address Mining.	FPGA	2017	DBLP BibTeX RDF
1	Mohammed Alawad, Mingjie Lin	Stochastic-Based Multi-stage Streaming Realization of a Deep Convolutional Neural Network (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu	An OpenCL™ Deep Learning Accelerator on Arria 10.	FPGA	2017	DBLP BibTeX RDF
1	Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei	Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Sumanta Chaudhuri	Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Yongming Shen 0001, Michael Ferdman, Peter A. Milder	Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Jialiang Zhang, Jing Li	Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network.	FPGA	2017	DBLP BibTeX RDF
1	Chi Zhang 0022, Viktor K. Prasanna	Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System.	FPGA	2017	DBLP BibTeX RDF
1	Fubing Mao, Wei Zhang 0012, Bingsheng He, SiewKei Lam	Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer	Automatic Construction of Program-Optimized FPGA Memory Networks.	FPGA	2017	DBLP BibTeX RDF
1	Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang	NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.	FPGA	2017	DBLP BibTeX RDF
1	Ritchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh Gupta 0001, Zhiru Zhang	Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs.	FPGA	2017	DBLP BibTeX RDF
1	Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon	Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays.	FPGA	2017	DBLP BibTeX RDF
1	Hayden Kwok-Hay So, John Wawrzynek	OLAF'17: Third International Workshop on Overlay Architectures for FPGAs.	FPGA	2017	DBLP BibTeX RDF
1	Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois	An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei	Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Gai Liu, Zhiru Zhang	A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping.	FPGA	2017	DBLP BibTeX RDF
1	Srinivas Siripurapu, Aman Gayasen, Padmini Gopalakrishnan, Nitin Chandrachoodan	FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Xin Fang 0001, Stratis Ioannidis, Miriam Leeser	Secure Function Evaluation Using an FPGA Overlay Architecture.	FPGA	2017	DBLP BibTeX RDF
1	Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Ong Gee Hock, Yeong Tat Liew, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra, Guy Boudoukh	Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?	FPGA	2017	DBLP BibTeX RDF
1	Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides	Hardware Synthesis of Weakly Consistent C Concurrency.	FPGA	2017	DBLP BibTeX RDF
1	Jialiang Zhang, Soroosh Khoram, Jing Li 0073	Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search.	FPGA	2017	DBLP BibTeX RDF
1	Subho S. Banerjee, Mohamed El-Hadedy 0001, Jong Bin Lim, Daniel Chen 0001, Zbigniew T. Kalbarczyk, Deming Chen, Ravishankar K. Iyer	ASAP: Accelerated Short Read Alignment on Programmable Hardware (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Haoyang Wu, Tao Wang 0004, Zhiwei Li, Boyan Ding, Xiaoguang Li, Tianfu Jiang, Jun Liu 0063, Songwu Lu	GRT 2.0: An FPGA-based SDR Platform for Cognitive Radio Networks (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	George A. Constantinides	FPGAs in the Cloud.	FPGA	2017	DBLP BibTeX RDF
1	Jonathan W. Greene, Jason Helge Anderson (eds.)	Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017	FPGA	2017	DBLP DOI BibTeX RDF
1	Shuo Wang 0009, Yun Liang 0001	A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Andrew Ling, Jason Anderson	The Role of FPGAs in Deep Learning.	FPGA	2017	DBLP BibTeX RDF
1	Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang	Accelerating Face Detection on Programmable SoC Using C-Based Synthesis.	FPGA	2017	DBLP BibTeX RDF
1	Atieh Lotfi, Rajesh K. Gupta 0001	RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers	FINN: A Framework for Fast, Scalable Binarized Neural Network Inference.	FPGA	2017	DBLP BibTeX RDF
1	Andy Gean Ye, Karthik Ganesan 0002	Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Dennis Weller, Fabian Oboril, Dimitar Lukarski, Jürgen Becker 0001, Mehdi Baradaran Tahoori	Energy Efficient Scientific Computing on FPGAs using OpenCL.	FPGA	2017	DBLP BibTeX RDF
1	Ralf Salomon, Ralf Joost	Precise Coincidence Detection on FPGAs: Three Case Studies (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Minghua Shen, Guojie Luo	Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion.	FPGA	2017	DBLP BibTeX RDF
1	Xiaoyu Ma, Dan Zhang 0004, Derek Chiou	FPGA-Accelerated Transactional Execution of Graph Workloads.	FPGA	2017	DBLP BibTeX RDF
1	Wei Ting Loke, Chin Yang Koay	An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura	A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Emanuele Pezzotti, Alex Iacobucci, Gregory Nash, Umer I. Cheema, Paolo Vinella, Rashid Ansari	FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic Resonance Imaging (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Yufei Ma 0002, Yu Cao 0001, Sarma B. K. Vrudhula, Jae-sun Seo	Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks.	FPGA	2017	DBLP BibTeX RDF
1	Yue Zha, Jialiang Zhang, Zhiqiang Wei, Jing Li 0073	A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Zhipeng Zhao, James C. Hoe	Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Daniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen	Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules.	FPGA	2017	DBLP BibTeX RDF
1	Chang Xu 0005, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, Zhiru Zhang	A Parallel Bandit-Based Approach for Autotuning FPGA Compilation.	FPGA	2017	DBLP BibTeX RDF
1	Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz	Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration.	FPGA	2017	DBLP BibTeX RDF
1	Alex Rodionov, Jonathan Rose	Synchronization Constraints for Interconnect Synthesis.	FPGA	2017	DBLP BibTeX RDF
1	Haohuan Fu, Conghui He, Huabin Ruan, Itay Greenspon, Wayne Luk, Yongkang Zheng, Junfeng Liao, Qing Zhang, Guangwen Yang	Accelerating Financial Market Server through Hybrid List Design (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Sitao Huang, Gowthami Jayashri Manikandan, Anand Ramachandran 0001, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen	Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling.	FPGA	2017	DBLP BibTeX RDF
1	Girish Deshpande, Dinesh K. Bhatia	Thermal Flattening in 3D FPGAs Using Embedded Cooling (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang	Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis.	FPGA	2017	DBLP BibTeX RDF
1	Christophe Bobda, Taylor J. L. Whitaker, Charles A. Kamhoua, Kevin A. Kwiat, Laurent Njilla	Automatic Generation of Hardware Sandboxes for Trojan Mitigation in Systems on Chip (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Yixing Li, Zichuan Liu, Kai Xu 0007, Hao Yu 0001, Fengbo Ren	A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Guohao Dai, Tianhao Huang, Yuze Chi, Ningyi Xu, Yu Wang 0002, Huazhong Yang	ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture.	FPGA	2017	DBLP BibTeX RDF
1	Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow	Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center.	FPGA	2017	DBLP BibTeX RDF
1	Zhuolun He, Guojie Luo	FPGA Acceleration for Computational Glass-Free Displays.	FPGA	2017	DBLP BibTeX RDF
1	Yanqiang Liu, Yao Li 0004, Weilun Xiong, Meng Lai, Cheng Chen, Zhengwei Qi, Haibing Guan	Scala Based FPGA Design Flow (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu 0010	CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Gary William Grewal, Shawki Areibi, Matthew Westrik, Ziad Abuowaimer, Betty Zhao	A Machine Learning Framework for FPGA Placement (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Song Han 0003, Junlong Kang, Huizi Mao, Yiming Hu, Xin Li, Yubin Li, Dongliang Xie, Hong Luo, Song Yao, Yu Wang 0002, Huazhong Yang, William (Bill) J. Dally	ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA.	FPGA	2017	DBLP BibTeX RDF
1	Mostafa Koraei, Magnus Jahre, S. Omid Fatemi	Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Stylianos I. Venieris, Christos-Savvas Bouganis	fpgaConvNet: Automated Mapping of Convolutional Neural Networks on FPGAs (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet	Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only).	FPGA	2017	DBLP BibTeX RDF
1	Chethan Kumar H. B, Prashant Ravi, Gourav Modi, Nachiket Kapre	120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board.	FPGA	2017	DBLP BibTeX RDF
1	Bingzhe Li, M. Hassan Najafi, David J. Lilja	Using Stochastic Computing to Reduce the Hardware Requirements for a Restricted Boltzmann Machine Classifier.	FPGA	2016	DBLP DOI BibTeX RDF
1	Pingakshya Goswami, Dinesh Bhatia	Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Aaron Landy, Greg Stitt	Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Derek Chiou	Intel Acquires Altera: How Will the World of FPGAs be Affected?	FPGA	2016	DBLP DOI BibTeX RDF
1	Paul Grigoras, Pavel Burovskiy, Wayne Luk	CASK: Open-Source Custom Architectures for Sparse Kernels.	FPGA	2016	DBLP DOI BibTeX RDF
1	Sebastien Bellon, Claudio Favi, Miroslaw Malek, Marco Macchetti, Francesco Regazzoni 0001	Evaluating the Impact of Environmental Factors on Physically Unclonable Functions (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Liwei Yang, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow	Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Vinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo	SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC.	FPGA	2016	DBLP DOI BibTeX RDF
1	Matthias Hinkfoth, Ralf Salomon	Increasing the Utility of Self-Calibration Methods in High-Precision Time Measurement Systems (Abstract Only).	FPGA	2016	DBLP DOI BibTeX RDF
1	Jiantao Qiu, Jie Wang 0022, Song Yao, Kaiyuan Guo, Boxun Li, Erjin Zhou, Jincheng Yu, Tianqi Tang 0001, Ningyi Xu, Sen Song, Yu Wang 0002, Huazhong Yang	Going Deeper with Embedded FPGA Platform for Convolutional Neural Network.	FPGA	2016	DBLP DOI BibTeX RDF

Publications at "FPGA"( http://dblp.L3S.de/Venues/FPGA )