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Results
Found 417 publication records. Showing 417 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Yee-Wing Hsieh, Steven P. Levitan |
Abstraction techniques for verification of multiple tightly coupled counters, registers and comparators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 133-138, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Christophe Paoli, Marie-Laure Nivet, Jean François Santucci |
Use of constraint solving in order to generate test vectors for behavioral validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 15-20, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Michael D. Jones, Ganesh Gopalakrishnan |
Toward automated abstraction for protocols on branching networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 147-152, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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1 | M. Beardo, Francesco Bruschi, Fabrizio Ferrandi, Donatella Sciuto |
An approach to functional testing of VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 29-33, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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1 | Bart Vermeulen, Gert-Jan van Rootselaar |
Silicon debug of a co-processor array for video applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 47-52, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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1 | |
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000 ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![IEEE Computer Society, 0-7695-0786-7 The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
|
1 | Stefan Koerner |
Code simulation concept for S/390 processors using an emulation system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 101-102, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Dominique Federici, Paul Bisgambiglia, Jean François Santucci |
High level fault simulation: experiments and results on ITC'99 benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 118-123, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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1 | Hoon Choi, Byeong-Whee Yun, Yun-Tae Lee |
Simulation strategy after model checking: experience in industrial SOC design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 77-79, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Anneliese von Mayrhauser, Tom Chen 0001, Jan Kok, Chuck Anderson 0001, Anita Read, Amjad Hajjar |
On choosing test criteria for behavioral level hardware design verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 124-130, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Karen A. Tomko, Anurag Tiwari |
Hardware/software co-debugging for reconfigurable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 59-63, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | M. S. Jahanpour, Eduard Cerny |
Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 71-76, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Hiroyuki Tomiyama, Taisei Yoshino, Nikil D. Dutt |
Verification of in-order execution in pipelined processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 40-44, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Vivekananda M. Vedula, Jacob A. Abraham |
A novel methodology for hierarchical test generation using functional constraint composition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 9-14, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Fabian Wolf, Rolf Ernst |
Data flow based cache prediction using local simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 155-160, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno |
Behavioral-level test vector generation for system-on-chip designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 21-26, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri |
An approach to high-level synthesis system validation using formally verified transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HLDVT ![In: Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, Berkeley, California, USA, November 8-10, 2000, pp. 80-85, 2000, IEEE Computer Society, 0-7695-0786-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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Displaying result #401 - #417 of 417 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5] |
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