| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Xunzhao Yin, Dayane Alfenas Reis, Michael T. Niemier, Xiaobo Sharon Hu |
Ferroelectric FET Based TCAM Designs for Energy Efficient Computing.  |
ISVLSI  |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammed M. Alawad, Georgia D. Tourassi |
Computationally Efficient Learning of Quality Controlled Word Embeddings for Natural Language Processing. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Amina Annagrebah, E. Bechetoille, I. B. Laktineh, H. Chanal, P. Russo, H. Mathez |
A Multi-phase Time-to-Digital Converter Differential Vernier Ring Oscillato. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Henrique Placido, Ricardo Reis 0001 |
Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Weiguang Chen, Zheng Wang, Shanliao Li, Zhibin Yu 0001, Huijuan Li |
Accelerating Compact Convolutional Neural Networks with Multi-threaded Data Streaming. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Alex Ayling, Satya Venkata Sandeep Avvaru, Keshab K. Parhi |
Not All Feed-Forward MUX PUFs Generate Unique Signatures. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Yinglin Zhao, Jianlei Yang 0001, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang 0001, Youguang Zhang, Weisheng Zhao |
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarit Chakraborty, Susanta Chakraborty |
Routing Performance Optimization for Homogeneous Droplets on MEDA-based Digital Microfluidic Biochips. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Mohamed Asan Basiri, Sandeep K. Shukla |
Formal Hardware Verification of InfoSec Primitives. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Sebastian Pointner, Oliver Frank, Christoph Hazott, Robert Wille |
Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design Flows. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler |
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Changlu Liu, Tianxiang Lan, Qin Li 0016, Kaige Jia, Yidian Fan, Xing Wu 0005, Fei Qiao, Wei Qi, Xin-Jun Liu, Huazhong Yang |
Energy-efficient Analog Processing Architecture for Direction of Arrival with Microphone Array. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Shivam Swami, Kartik Mohanram |
ASSET: Architectures for Smart Security of Non-Volatile Memories. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi |
An ESL Environment for Modeling Electrical Interconnect Faults. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhishek Vashist, Andrew Keats, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly |
Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service Attacks. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ruben Vazquez, Islam Badreldin, Mohamad Hammam Alsafrjalani, Ann Gordon-Ross |
Machine Learning-based Prediction for Phase-Based Dynamic Architectural Specialization. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Chi Fung Brian Fong, Jiandong Mu, Wei Zhang 0012 |
A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ling-Yen Song, Yu-Ying Li, Yung-Chun Lei, Juinn-Dar Huang |
Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic Biochips. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Karthikeyan Nagarajan, Sina Sayyah Ensan, Swagata Mandal, Swaroop Ghosh, Anupam Chattopadhyay |
iMACE: In-Memory Acceleration of Classic McEliece Encoder. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Wei Tai, Rung-Bin Lin |
Morphed Standard Cell Layouts for Pin Length Reduction. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Fatemeh Serajeh-hassani, Mohammad Sadrosadati, Sebastian Pointner, Robert Wille, Hamid Sarbazi-Azad |
Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Edgard Muñoz-Coreas, Himanshu Thapliyal |
Design of Quantum Circuits for Cryptanalysis and Image Processing Applications. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiangyu Chen, Yasuhiro Takahashi |
Design of a CMOS Broadband Transimpedance Amplifier with Floating Active Inductor. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Himanshu Thapliyal, Zachary Kahleifeh |
Approximate Energy Recovery 4-2 Compressor for Low-Power Sub-GHz IoT Applications. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Vamsee Reddy Kommareddy, Clayton Hughes, Simon D. Hammond, Amro Awad |
Investigating Fairness in Disaggregated Non-Volatile Memories. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Anderson Luiz Sartor, Pedro Henrique Exenberger Becker, Stephan Wong, Radu Marculescu, Antonio Carlos Schneider Beck |
Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and Reliability. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Soheil Salehi, Alireza Zaeemzadeh, Adrian Tatulian, Nazanin Rahnavard, Ronald F. DeMara |
MRAM-Based Stochastic Oscillators for Adaptive Non-Uniform Sampling of Sparse Signals in IoT Applications. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Joel Ortiz Sosa, Olivier Sentieys, Christian Roland |
Adaptive Transceiver for Wireless NoC to Enhance Multicast/Unicast Communication Scenarios. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Siavoosh Payandeh Azad, Gert Jervan, Michael Tempelmeier, Johanna Sepúlveda |
CAESAR-MPSoC: Dynamic and Efficient MPSoC Security Zones. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Taehwan Kim 0007, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi |
SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Jonas Gava, Vitor V. Bandeira, Ricardo Reis 0001, Luciano Ost |
Evaluation of Compilers Effects on OpenMP Soft Error Resiliency. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Gopabandhu Hota, Hardik Agrawal, Mrigank Sharad |
An Area Effective Programmable Front-end Amplifier for Neural Signal Acquisition. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Arish S, Sharad Sinha, Smitha K. G. |
Optimization of Convolutional Neural Networks on Resource Constrained Devices. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Yunxiang Zhang 0001, Xiaokun Yang, Lei Wu, Jean Andrian |
A Case Study On Approximate FPGA Design With an Open-Source Image Processing Platform. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Cyril Bresch, David Hély, Stéphanie Chollet, Ioannis Parissis |
TrustFlow: A Trusted Memory Support for Data Flow Integrity. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingze Gao, Qian Wang 0022, Gang Qu 0001 |
Energy and Error Reduction using Variable Bit-width Optimization on Dynamic Fixed Point Format. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhiming Zhang, Qiaoyan Yu |
Modeling Hardware Trojans in 3D ICs. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Ling Qiu, Ziji Zhang, Jon Calhoun 0001, Yingjie Lao |
Towards Data-Driven Approximate Circuit Design. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski |
Formal Verification of Integer Dividers: Division by a Constant. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthew Gaalswyk, James E. Stine |
A Low-Power Recurrence-Based Radix 4 Divider Using Signed-Digit Addition. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroki Koyasu, Yasuhiro Takahashi |
Evaluation of Power Analysis Attacks on Cryptographic Circuit Using Adiabatic Logic. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Satya Venkata Sandeep Avvaru, Keshab K. Parhi |
Effect of Loop Positions on Reliability and Attack Resistance of Feed-Forward PUFs. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Prasad Vernekar, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra |
Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuo Li, Xiaolin Xu, Wayne P. Burleson |
PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process Variations. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Tongxin Yang, Toshinori Sato, Tomoaki Ukezono |
An Approximate Multiply-Accumulate Unit with Low Power and Reduced Area. |
ISVLSI |
2019 |
DBLP DOI BibTeX RDF |
|
| 1 | Haeyoon Cho 0002, Joonho Kong, Arslan Munir, Naresh Kumar Giri |
CT-Cache: Compressed Tag-Driven Cache Architecture. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Liuyang Zhang, Wang Kang 0001, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao |
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Shi, Tongda Wu, Keni Qiu, Huazhong Yang, Yongpan Liu |
Time Stamp Based Scheduling for Energy Harvesting Systems with Hybrid Nonvolatile Hardware Support. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao |
Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Soroush Khaleghi, Wenjing Rao |
Hardware Obfuscation Using Strong PUFs. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Qian Chen, Sheqin Dong |
A Novel Mixed-Size Fixed-Outline Floorplacement Algorithm. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicholas Jao, Akshay Krishna Ramanathan, Srivatsa Rangachar Srinivasa, Sumitha George, John Sampson, Vijaykrishnan Narayanan |
Harnessing Emerging Technology for Compute-in-Memory Support. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Xueqing Li, Longqiang Lai |
Nonvolatile Memory and Computing Using Emerging Ferroelectric Transistors. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yunxi Guo, Timothy Dee, Akhilesh Tyagi |
Multi-block APUF with 2-Level Voltage Supply. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | SreeCharan Gundabolu, Xiaofang Wang |
On-chip Data Security Against Untrustworthy Software and Hardware IPs in Embedded Systems. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Islam Badreldin, Ann Gordon-Ross, Tosiron Adegbija, Mohamad Hammam Alsafrjalani |
Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Grace Li Zhang, Bing Li 0005, Ulf Schlichtmann |
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yingjian Ling, Kan Zhong, Yunsong Wu, Duo Liu, Jinting Ren, Renping Liu, Moming Duan, Weichen Liu, Liang Liang 0002 |
TaiJiNet: Towards Partial Binarized Convolutional Neural Network for Embedded Systems. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Saeideh Shirinzadeh, Rolf Drechsler |
Logic Synthesis for In-memory Computing Using Resistive Memories. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Sri Harsha Gade, Mitali Sinha, Sidhartha Sankar Rout, Sujay Deb |
Enabling Reliable High Throughput On-chip Wireless Communication for Many Core Architectures. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ahmad Patooghy, Ehsan Aerabi, Hamidreza Rezaei, Miguel Mark, Mahdi Fazeli, Michel A. Kinsy |
Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Marjan Asadinia, Christophe Bobda |
Enhancing Lifetime of PCM-Based Main Memory with Efficient Recovery of Stuck-at Faults. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Sukanta Dey, Satyabrata Dash, Sukumar Nandi, Gaurav Trivedi |
PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks Using Cooperative Coevolution. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Zou, Mingjie Lin |
Very Large-Scale and Node-Heavy Graph Analytics with Heterogeneous FPGA+CPU Computing Platform. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajinkya Kale, Johannes Sturm, Vijaya Sankara Rao Pasupureddi |
0.9 to 2.5 GHz Sub-Sampling Receiver Architecture for Dynamically Reconfigurable SDR. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yizhi Wang, Jun Lin 0001, Zhongfeng Wang 0001 |
FPAP: A Folded Architecture for Efficient Computing of Convolutional Neural Networks. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikas Rana |
Area Efficient NMOS Based Positive and Negative Voltage Multiplier. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Rao, Bin Zhang 0022, Jizhong Zhao |
Hardware Implementation of Reconfigurable Separable Convolution. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongfu Li 0003, I-Lun Tseng, Zhao Chuan Lee, Valerio Perez, Vikas Tripathi, Yoong Seang Jonathan Ong |
Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jan Nevoral, Richard Ruzicka, Václav Simek |
CMOS Gates with Second Function. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Changcheng Tang, Zuochang Ye, Yan Wang 0023 |
Parametric Circuit Optimization with Reinforcement Learning. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Debjyoti Bhattacharjee, Anupam Chattopadhyay |
Synthesis, Technology Mapping and Optimization for Emerging Technologies. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Tsung-Yi Ho |
Design Automation and Test for Flow-Based Biochips: Past Successes and Future Challenges. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Iris Hui-Ru Jiang, Hua-Yu Chang |
Recent Research and Challenges in Multiple Patterning Layout Decomposition. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Stornaiuolo, Marco D. Santambrogio, Donatella Sciuto |
On How to Efficiently Implement Deep Learning Algorithms on PYNQ Platform. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Anubhab Baksi, Vikramkumar Pudi, Swagata Mandal, Anupam Chattopadhyay |
Lightweight ASIC Implementation of AEGIS-128. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Luca Marchetti, Yngvar Berg, Mehdi Azadmehr |
A Low Power, High Gain Semi-Floating Gate Amplifier for Resonating Sensors Front-End. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler |
Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Senwen Kan, Jennifer Dworak |
Can Soft Errors be Handled Securely? |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ankit Jindal, Binod Kumar 0001, Nitish Jindal, Masahiro Fujita, Virendra Singh |
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ankit Rehani, Sujay Deb, Pydi Ganga Bahubalindruni, Bhavin Odedara, Srikanth Bojja |
A High-Efficient Current-Mode PWM DC-DC Buck Converter Using Dynamic Frequency Scaling. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinhang Choi, Srivatsa Rangachar Srinivasa, Yasuki Tanabe, Jack Sampson, Vijaykrishnan Narayanan |
A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuting Cao, Hernan M. Palombo, Sandip Ray, Hao Zheng 0001 |
Enhancing Observability for Post-Silicon Debug with On-chip Communication Monitors. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiaoyan Yu, Zhiming Zhang, Jaya Dofe |
Investigating Reliability and Security of Integrated Circuits and Systems. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Debapriya Basu Roy, Debdeep Mukhopadhyay |
Minimalistic Perspective to Public Key Implementations on FPGA. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Suman Adhepalli Muralikrishnan, Pulkit Sapra, Saurabh Agrawal, Piyush Chanana, M. Balakrishnan, P. V. M. Rao |
FPGA-Based Controllers for Compact Low Power Refreshable Braille Display. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Mike Borowczak, Rafer Cooley, Shaya Wolf |
Designing for Security Within and Between IoT Devices. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Ankita Porwal, Chitrakant Sahu |
Biosensing Performance Optimization of DMFET for Fully Filled and Partially Filled Cavity. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Tomás Grimm, Djones Lettnin, Michael Hübner 0001 |
ARCHVerifyr: An Embedded Software-Driven Approach for Architecture Verification. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Faqiang Mei, Lei Zhang 0089, Chongyan Gu, Yuan Cao, Chenghua Wang, Weiqiang Liu 0001 |
A Highly Flexible Lightweight and High Speed True Random Number Generator on FPGA. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongqin Zhou, Keni Qiu, Yuanchao Xu 0002, Xin Shi, Yongpan Liu |
A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhezhi He, Shaahin Angizi, Deliang Fan |
Accelerating Low Bit-Width Deep Convolution Neural Network in MRAM. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Anirban Sengupta, Saraju P. Mohanty |
Functional Obfuscation of DSP Cores Using Robust Logic Locking and Encryption. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Fangxuan Sun, Jun Lin 0001, Zhongfeng Wang 0001 |
An Optimized Architecture For Decomposed Convolutional Neural Networks. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Zihao Liu, Tao Liu 0023, Jie Guo 0002, Nansong Wu, Wujie Wen |
An ECC-Free MLC STT-RAM Based Approximate Memory Design for Multimedia Applications. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu |
Interconnect Delay Analysis for RRAM Crossbar Based FPGA. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Harsha M. V., B. P. Harish |
An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design Automation. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Kalindu Herath, Alok Prakash, Udaree Kanewala, Thambipillai Srikanthan |
Communication-Aware Module Placement for Power Reduction in Large FPGA Designs. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Subrata Das, Debesh Kumar Das |
Floorplanning in Graphene Nanoribbon (GNR) Based Circuits. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
| 1 | Juan Fang, Zeqing Chang, Yanjin Cheng, Hui Zhao 0013 |
Exploration on Routing Configuration of HNoC with Reasonable Energy Consumption. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
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