Search results for "LAS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	José Monteiro 0001, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar	Scheduling Techniques to Enable Power Management.	DAC	1996	DBLP DOI BibTeX RDF
28	Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang	Layout Driven Selecting and Chaining of Partial Scan.	DAC	1996	DBLP DOI BibTeX RDF
28	Mani B. Srivastava, Miodrag Potkonjak	Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach.	DAC	1996	DBLP DOI BibTeX RDF
28	Yong Je Lim, Kyung-Im Son, Heung-Joon Park, Mani Soma	A Statistical Approach to the Estimation of Delay Dependent Switching Activities in CMOS Combinational Circuits.	DAC	1996	DBLP DOI BibTeX RDF
28	Sungju Park	A New Complete Diagnosis Patterns for Wiring Interconnects.	DAC	1996	DBLP DOI BibTeX RDF
28	Byron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi	A Sparse Image Method for BEM Capacitance Extraction.	DAC	1996	DBLP DOI BibTeX RDF
28	Jian Li 0061, Rajesh K. Gupta 0001	HDL Optimization Using Timed Decision Tables.	DAC	1996	DBLP DOI BibTeX RDF
28	Chung-Ping Chen, Yao-Wen Chang, D. F. Wong 0001	Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation.	DAC	1996	DBLP DOI BibTeX RDF
28	Anantha P. Chandrakasan, Isabel Y. Yang, Carlin Vieri, Dimitri A. Antoniadis	Design Considerations and Tools for Low-voltage Digital System Design.	DAC	1996	DBLP DOI BibTeX RDF
28	David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska	A New Hybrid Methodology for Power Estimation.	DAC	1996	DBLP DOI BibTeX RDF
28	V. Chandramouli, Karem A. Sakallah	Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time.	DAC	1996	DBLP DOI BibTeX RDF
28	Mahesh A. Iyer, David E. Long, Miron Abramovici	Identifying Sequential Redundancies Without Search.	DAC	1996	DBLP DOI BibTeX RDF
28	Gopi Ganapathy, Ram Narayan, Glenn Jorden, Denzil Fernandez, Ming Wang, Jim Nishimura	Hardware Emulation for Functional Verification of K5.	DAC	1996	DBLP DOI BibTeX RDF
28	Carsten Borchers, Lars Hedrich, Erich Barke	Equation-Based Behavioral Model Generation for Nonlinear Analog Circuits.	DAC	1996	DBLP DOI BibTeX RDF
28	Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng	Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming.	DAC	1996	DBLP DOI BibTeX RDF
28	Mahesh Mehendale, G. Venkatesh 0001, Sunil D. Sherlekar	Optimized Code Generation of Multiplication-free Linear Transforms.	DAC	1996	DBLP DOI BibTeX RDF
28	James Monaco, David Holloway, Rajesh Raina	Functional Verification Methodology for the PowerPC 604 Microprocessor.	DAC	1996	DBLP DOI BibTeX RDF
28	Anoosh Hosseini, Dimitrios Mavroidis, Pavlos Konas	Code Generation and Analysis for the Functional Verification of Microprocessors.	DAC	1996	DBLP DOI BibTeX RDF
28	Andrew Wolfe	Opportunities and Obstacles in Low-Power System-Level CAD.	DAC	1996	DBLP DOI BibTeX RDF
28	Arun N. Lokanathan, Jay B. Brockman, John E. Renaud	A Methodology for Concurrent Fabrication Process/Cell Library Optimization.	DAC	1996	DBLP DOI BibTeX RDF
28	Robert C. Hutchins, Shankar Hemmady	How to Write Awk and Perl Scripts to Enable Your EDA Tools to Work Together.	DAC	1996	DBLP DOI BibTeX RDF
28	Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino, Donatella Sciuto	Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.	DAC	1996	DBLP DOI BibTeX RDF
28	Andreas Koch	Module Compaction in FPGA-based Regular Datapaths.	DAC	1996	DBLP DOI BibTeX RDF
28	Balakrishnan Iyer, Ramesh Karri	Introspection: A Low Overhead Binding Technique During Self-Diagnosing Microarchitecture Synthesis.	DAC	1996	DBLP DOI BibTeX RDF
28	Olivier Coudert	On Solving Covering Problems.	DAC	1996	DBLP DOI BibTeX RDF
28	Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil	Characterization and Parameterized Random Generation of Digital Circuits.	DAC	1996	DBLP DOI BibTeX RDF
28	Yusuke Matsunaga	An Efficient Equivalence Checker for Combinational Circuits.	DAC	1996	DBLP DOI BibTeX RDF
28	Edmund M. Clarke, Manpreet Khaira, Xudong Zhao 0005	Word Level Model Checking - Avoiding the Pentium FDIV Error.	DAC	1996	DBLP DOI BibTeX RDF
28	Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson	A Technique for Synthesizing Distributed Burst-mode Circuits.	DAC	1996	DBLP DOI BibTeX RDF
28	Paolo Miliozzi, Iasson Vassiliou, Edoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli	Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design.	DAC	1996	DBLP DOI BibTeX RDF
28	Jason Cong, Yean-Yow Hwang	Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design.	DAC	1996	DBLP DOI BibTeX RDF
28	Michael Kantrowitz, Lisa M. Noack	I'm Done Simulating: Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha Microprocessor.	DAC	1996	DBLP DOI BibTeX RDF
28	Chung-Ping Chen, Yao-Ping Chen, D. F. Wong 0001	Optimal Wire-Sizing Formular Under the Elmore Delay Model.	DAC	1996	DBLP DOI BibTeX RDF
28	Cyrus Bamji, Enrico Malavasi	Enhanced Network Flow Algorithm for Yield Optimization.	DAC	1996	DBLP DOI BibTeX RDF
28	C. Norris Ip, David L. Dill	State Reduction Using Reversible Rules.	DAC	1996	DBLP DOI BibTeX RDF
28	Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Engineering Change in a Non-Deterministic FSM Setting.	DAC	1996	DBLP DOI BibTeX RDF
28	Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng	Network Partitioning into Tree Hierarchies.	DAC	1996	DBLP DOI BibTeX RDF
28	Luc Burgun, Frédéric Reblewski, Gérard Fenelon, Jean Barbier, Olivier Lepape	Serial Fault Emulation.	DAC	1996	DBLP DOI BibTeX RDF
28	Kei Suzuki, Alberto L. Sangiovanni-Vincentelli	Efficient Software Performance Estimation Methods for Hardware/Software Codesign.	DAC	1996	DBLP DOI BibTeX RDF
28	Chien-Chung Tsai, Malgorzata Marek-Sadowska	Multilevel Logic Synthesis for Arithmetic Functions.	DAC	1996	DBLP DOI BibTeX RDF
28	Shashidhar Thakur, D. F. Wong 0001, Shankar Krishnamoorthy	Delay Minimal Decomposition of Multiplexers in Technology Mapping.	DAC	1996	DBLP DOI BibTeX RDF
28	Alexei L. Semenov, Alexandre Yakovlev	Verification of asynchronous circuits using Time Petri Net unfolding.	DAC	1996	DBLP DOI BibTeX RDF
28	Hans Sahm, Claus Mayer, Jörg Pleickhardt, Johannes Schuck, Stefan Späth	VDHL Development System and Coding Standard.	DAC	1996	DBLP DOI BibTeX RDF	VHDL
28	Shantanu Dutt, Wenyong Deng	A Probability-Based Approach to VLSI Circuit Partitioning.	DAC	1996	DBLP DOI BibTeX RDF
28	Jagesh V. Sanghavi, Rajeev K. Ranjan 0001, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	High Performance BDD Package By Exploiting Memory Hiercharchy.	DAC	1996	DBLP DOI BibTeX RDF
28	Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin	Energy Characterization based on Clustering.	DAC	1996	DBLP DOI BibTeX RDF
28	Alessandro Bogliolo, Luca Benini, Bruno Riccò	Power Estimation of Cell-Based CMOS Circuits.	DAC	1996	DBLP DOI BibTeX RDF
28	Narayan R. Aluru, V. B. Nadkarni, James White	A Parallel Precorrected FFT Based Capacitance Extraction Program for Signal Integrity Analysis.	DAC	1996	DBLP DOI BibTeX RDF
28	Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic	Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools.	DAC	1996	DBLP DOI BibTeX RDF
28	Frank M. Johannes	Partitioning of VLSI Circuits and Systems.	DAC	1996	DBLP DOI BibTeX RDF
28	Christos A. Papachristou, Mark Spining, Mehrdad Nourani	An Effective Power Management Scheme for RTL Design Based on Multiple Clocks.	DAC	1996	DBLP DOI BibTeX RDF
28	David Lidsky, Jan M. Rabaey	Early Power Exploration - A World Wide Web Application.	DAC	1996	DBLP DOI BibTeX RDF
28	Mattan Kamon, Steve S. Majors	Package and Interconnect Modeling of the HFA3624, a 2.4GHz RF to IF Converter.	DAC	1996	DBLP DOI BibTeX RDF
28	Koichi Sato, Masamichi Kawarabayashi, Hideyuki Emura, Naotaka Maeda	Post-Layout Optimization for Deep Submicron Design.	DAC	1996	DBLP DOI BibTeX RDF
28	Steven Vercauteren, Bill Lin 0001, Hugo De Man	A Strategy for Real-Time Kernel Support in Application-Specific HW/SW Embedded Architectures.	DAC	1996	DBLP DOI BibTeX RDF
28	Jos A. Huisken, F. Welten	FADIC: Architectural Synthesis applied in IC Design.	DAC	1996	DBLP DOI BibTeX RDF
28	Benny Schnaider, Einat Yogev	Software Development in a Hardware Simulation Environment.	DAC	1996	DBLP DOI BibTeX RDF
28	Janardhan H. Satyanarayana, Keshab K. Parhi	HEAT: Hierarchical Energy Analysis Tool.	DAC	1996	DBLP DOI BibTeX RDF
28	Aurobindo Dasgupta, Ramesh Karri	Electromigration Reliability Enhancement via Bus Activity Distribution.	DAC	1996	DBLP DOI BibTeX RDF
28	Jeremy R. Levitt, Kunle Olukotun	A Scalable Formal Verification Methodology for Pipelined Microprocessors.	DAC	1996	DBLP DOI BibTeX RDF
28	Johannes Tausch, Jacob K. White 0001	Multipole Accelerated Capacitance Calculation for Structures with Multiple Dielectrics with high Permittivity Ratios.	DAC	1996	DBLP DOI BibTeX RDF
28	Mien Li, Linda S. Milor	Computing Parametric Yield Adaptively Using Local Linear Models.	DAC	1996	DBLP DOI BibTeX RDF
28	Joel R. Philips, Eli Chiprout, David D. Ling	Efficient Full-Wave Electromagnetic Analysis via Model-Order Reduction of Fast Integral Transforms.	DAC	1996	DBLP DOI BibTeX RDF
28	Bernhard Rohfleisch, Alfred Kölbl, Bernd Wurth	Reducing Power Dissipation after Technology Mapping by Structural Transformations.	DAC	1996	DBLP DOI BibTeX RDF
28	Elisabeth Berrebi, Polen Kission, Serge Vernalde, S. De Troch, Jean-Claude Herluison, Jean Fréhel, Ahmed Amine Jerraya, Ivo Bolsens	Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis.	DAC	1996	DBLP DOI BibTeX RDF
28	Douglas J. Smith	VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C.	DAC	1996	DBLP DOI BibTeX RDF	VHDL
28	Randal E. Bryant	Bit-Level Analysis of an SRT Divider Circuit.	DAC	1996	DBLP DOI BibTeX RDF
28	Yasunori Miyahara, Yoshimoto Oumi, Seijiro Moriyama	Design Methodology for Analog High Frequency ICs.	DAC	1996	DBLP DOI BibTeX RDF
28	Sanjay Sawant, Paul Giordano	RTL Emulation: The Next Leap in System Verification.	DAC	1996	DBLP DOI BibTeX RDF
28	Steven Vercauteren, Bill Lin 0001, Hugo De Man	Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications.	DAC	1996	DBLP DOI BibTeX RDF
28	K. D. Jones, J. P. Privitera	The Automatic Generation of Functional Test Vectors for Rambus Designs.	DAC	1996	DBLP DOI BibTeX RDF
28	P. J. H. Elias, N. P. van der Meijs	Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency.	DAC	1996	DBLP DOI BibTeX RDF
28	Diana Marculescu, Radu Marculescu, Massoud Pedram	Stochastic Sequential Machine Synthesis Targeting Constrained Sequence Generation.	DAC	1996	DBLP DOI BibTeX RDF
28	Ishwar Parulkar, Sandeep K. Gupta 0001, Melvin A. Breuer	Lower Bounds on Test Resources for Scheduled Data Flow Graphs.	DAC	1996	DBLP DOI BibTeX RDF
28	Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng	New Spectral Linear Placement and Clustering Approach.	DAC	1996	DBLP DOI BibTeX RDF
28	Laurence Goodby, Alex Orailoglu	Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths.	DAC	1996	DBLP DOI BibTeX RDF
28	Arjan J. van Genderen, N. P. van der Meijs	Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction.	DAC	1996	DBLP DOI BibTeX RDF
28	L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen	Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies.	DAC	1996	DBLP DOI BibTeX RDF
28	Olivier Coudert, Ramsey W. Haddad, Srilatha Manne	New Algorithms for Gate Sizing: A Comparative Study.	DAC	1996	DBLP DOI BibTeX RDF
28	Ásgeir Th. Eiríksson	Integrating Formal Verification Methods with A Conventional Project Design Flow.	DAC	1996	DBLP DOI BibTeX RDF
28	Mike Murray, Uwe B. Meding, Bill Berg, Yatin Trivedi, Bill McCaffrey, Ted Vucurevich	Issues and Answers in CAD Tool Interoperability.	DAC	1996	DBLP DOI BibTeX RDF
28	Bernhard Wunder, Gunther Lehmann, Klaus D. Müller-Glaser	VAMP: A VHDL-Based Concept for Accurate Modeling and Post Layout Timing Simulation of Electronic Systems.	DAC	1996	DBLP DOI BibTeX RDF
28	Peichen Pan, C. L. Liu 0001	Optimal Clock Period FPGA Technology Mapping for Sequential Circuits.	DAC	1996	DBLP DOI BibTeX RDF
28	Val Popescu, Bill McNamara	Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor.	DAC	1996	DBLP DOI BibTeX RDF
28	Tetsuya Fujimoto, Takashi Kambe	VLSI Design and System Level Verification for the Mini-Disc.	DAC	1996	DBLP DOI BibTeX RDF
28	Ilan Beer, Shoham Ben-David, Cindy Eisner, Avner Landver	RuleBase: An Industry-Oriented Formal Verification Tool.	DAC	1996	DBLP DOI BibTeX RDF
28	Danny Z. Chen, Xiaobo Hu 0001	Efficient Approximation Algorithms for Floorplan Area Minimization.	DAC	1996	DBLP DOI BibTeX RDF
28	Tony Stornetta, Forrest Brewer	Implementation of an Efficient Parallel BDD Package.	DAC	1996	DBLP DOI BibTeX RDF
28	Eric W. Johnson, Luis A. Castillo, Jay B. Brockman	Application of a Markov Model to the Measurement, Simulation, and Diagnosis of an Iterative Design Process.	DAC	1996	DBLP DOI BibTeX RDF
28	John W. Hagerman, Stephen W. Director	Improved Tool and Data Selection in Task Management.	DAC	1996	DBLP DOI BibTeX RDF
28	Bogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi	An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response.	DAC	1996	DBLP DOI BibTeX RDF
28	Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang	Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects.	DAC	1996	DBLP DOI BibTeX RDF
28	Ehat Ercanli, Christos A. Papachristou	A Register File and Scheduling Model for Application Specific Processor Synthesis.	DAC	1996	DBLP DOI BibTeX RDF
28	Sasan Iman, Massoud Pedram	POSE: Power Optimization and Synthesis Environment.	DAC	1996	DBLP DOI BibTeX RDF
28	Jeffery P. Hansen, Masatoshi Sekine	Synthesis by Spectral Translation Using Boolean Decision Diagrams.	DAC	1996	DBLP DOI BibTeX RDF
28	Weikai Sun, Wayne Wei-Ming Dai, Wei Hong II	Fast Parameters Extraction of General Three-Dimension Interconnects Using Geometry Independent Measured Equation of Invariance.	DAC	1996	DBLP DOI BibTeX RDF
28	Joe G. Xi, Wayne Wei-Ming Dai	Useful-Skew Clock Routing With Gate Sizing for Low Power Design.	DAC	1996	DBLP DOI BibTeX RDF
28	Hisakazu Edamatsu, Satoshi Ikawa, Katsuya Hasegawa	Design Methodologies for consumer-use video signal processing LSIs.	DAC	1996	DBLP DOI BibTeX RDF
28	De-Sheng Chen, Majid Sarrafzadeh	An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing.	DAC	1996	DBLP DOI BibTeX RDF
28	Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang	iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips.	DAC	1996	DBLP DOI BibTeX RDF