Search results for "NANOARCH"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Bao Liu, Zhen Cao, Jun Tao 0001, Xuan Zeng 0001, Pushan Tang, H.-S. Philip Wong	Intel LVS logic as a combinational logic paradigm in CNT technology.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Muzaffer O. Simsir, Niraj K. Jha	NanoV: Nanowire-based VLSI design.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Prasad Shabadi, Alexander Khitun, Pritish Narayanan, Mingqiang Bao, Israel Koren, Kang L. Wang, Csaba Andras Moritz	Towards logic functions as the device.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Muzaffer O. Simsir, Ajay N. Bhoj, Niraj K. Jha	Fault modeling for FinFET circuits.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Michael Crocker, Xiaobo Sharon Hu, Michael T. Niemier	Design and comparison of NML systolic architectures.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Eric Rachlin, John E. Savage	Stochastic nanoscale addressing for logic.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra	Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose	Memristor based programmable threshold logic array.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Kotb Jabeur, David Navarro, Ian O'Connor, Pierre-Emmanuel Gaillardon, M. Haykel Ben Jamaa, Fabien Clermidy	Reducing transistor count in clocked standard cells with ambipolar double-gate FETs.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Robinson E. Pino, James W. Bohl, Nathan R. McDonald, Bryant T. Wysocki, Peter J. Rozwood, Kristy A. Campbell, Antonio S. Oblea, Achyut Timilsina	Compact method for modeling and simulation of memristor devices: Ion conductor chalcogenide-based memristor devices.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Shigeru Yamashita, Igor L. Markov	Fast equivalence-checking for quantum circuits.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Marco Ottavi, Salvatore Pontarelli, Erik DeBenedictis, Adelio Salsano, Peter M. Kogge, Fabrizio Lombardi	High throughput and low power dissipation in QCA pipelines using Bennett clocking.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Michele De Marchi, M. Haykel Ben Jamaa, Giovanni De Micheli	Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Xiaowen Wu, Yaoyao Ye, Wei Zhang 0012, Weichen Liu, Mahdi Nikdast, Xuan Wang 0001, Jiang Xu 0001	UNION: A unified inter/intra-chip optical network for chip multiprocessors.	NANOARCH	2010	DBLP DOI BibTeX RDF
1	Shamik Das, Iris Bahar, Michael T. Niemier (eds.)	2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010	NANOARCH	2010	DBLP BibTeX RDF
1	Yiran Chen 0001, Xiaobin Wang	Compact modeling and corner analysis of spintronic memristor.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Pritish Narayanan, Csaba Andras Moritz, Kyoung-won Park, Chi On Chui	Validating cascading of crossbar circuits with an integrated device-circuit exploration.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Navid Farazmand, Mehdi Baradaran Tahoori	Online detection of multiple faults in crossbar nano-architectures using dual rail implementations.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Yehua Su, Wenjing Rao	Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Aaron Dingler, Michael T. Niemier, Xiaobo Sharon Hu, Michael Garrison, M. Tanvir Alam	System-level energy and performance projections for nanomagnet-based logic.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Ming Liu, Haigang Yang, Sansiri Tanachutiwat, Wei Wang 0003	FPGA based on integration of carbon nanorelays and CMOS devices.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Ben Kuiper, Sorin Cotofana	Adaptive Clock Scheduling for pipelined structures.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Yuan Xie 0001, Soumya Eachempati, Aditya Yanamandra, Vijaykrishnan Narayanan, Mary Jane Irwin	Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.	NANOARCH	2009	DBLP DOI BibTeX RDF
1		2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009, San Francisco, CA, USA, July 30-31, 2009	NANOARCH	2009	DBLP BibTeX RDF
1	Somnath Paul, Swarup Bhunia	Computing with nanoscale memory: Model and architecture.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Patrick Lincoln	Challenges in scalable fault tolerance.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Pierre-Emmanuel Gaillardon, Fabien Clermidy, Ian O'Connor, Junchen Liu	Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Nor Zaidi Haron, Said Hamdioui	Residue-based code for reliable hybrid memories.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Shu Li, Tong Zhang 0002	Using carbon nanotube in digital memories.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Inwook Kong, Earl E. Swartzlander Jr., Seong-Wan Kim	Design of a Goldschmidt iterative divider for quantum-dot cellular automata.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Eero Lehtonen, Mika Laiho	Stateful implication logic with memristors.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Saket Srivastava, Aissa Melouki, Bashir M. Al-Hashimi	Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Zahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi	A coding framework for DNA self-assembly.	NANOARCH	2009	DBLP DOI BibTeX RDF
1	Ali Namazi, M. Nourami, M. Saquib	A voterless strategy for defect-tolerant nano-architectures.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Saleh Safiruddin, Sorin Dan Cotofana, Ferdinand Peper	Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Saturnino Garcia, Alex Orailoglu	Online test and fault-tolerance for nanoelectronic programmable logic arrays.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Weiguo Tang, Lei Wang 0003	A DSP nanosystem with defect tolerance.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Wenjing Rao, Alex Orailoglu, Keith Marzullo	Locality aware redundancy allocation in nanoelectronic systems.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Christof Teuscher, Natali Gulbahce, Thimo Rohlf	Assessing random dynamical network architectures for nanoelectronics.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Soumya Eachempati, Vinay Saripalli, Narayanan Vijaykrishnan, Suman Datta	Reconfigurable BDD based quantum circuits.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Gregory S. Snider	Spike-timing-dependent learning in memristive nanodevices.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Ming Liu, Wei Wang 0003	rFGA: CMOS-nano hybrid FPGA using RRAM components.	NANOARCH	2008	DBLP DOI BibTeX RDF
1		2008 IEEE International Symposium on Nanoscale Architectures, NANOARCH 2008, Anaheim, CA, USA, June 12-13, 2008	NANOARCH	2008	DBLP BibTeX RDF
1	Prateek Mishra, Anish Muttreja, Niraj K. Jha	Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt	System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Michael Crocker, Xiaobo Sharon Hu, Michael T. Niemier	Defect tolerance in QCA-based PLAs.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Basheer A. M. Madappuram, Valeriu Beiu, Peter M. Kelly, Liam McDaid	On brain-inspired connectivity and hybrid network topologies.	NANOARCH	2008	DBLP DOI BibTeX RDF
1	Jianwei Dai, Lei Wang 0003, Faquir C. Jain	Analysis of defect tolerance in molecular electronics using information-theoretic measures.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Susmit Biswas, Frederic T. Chong, Tzvetan S. Metodi, Ryan Kastner	A pageable, defect-tolerant nanoscale memory system.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Shamik Das, Matthew F. Bauwens	Clocking nanocircuits for nanocomputers and other nanoelectronic systems.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Shuo Wang, Lei Wang 0003, Faquir C. Jain	Dynamic redundancy allocation for reliable and high-performance nanocomputing.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi	Robust self-assembly of interconnects by parallel DNA growth.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Hua Li, Joseph L. Mundy, William R. Patterson, Dimitrios Kazazis, Alexander Zaslavsky, R. Iris Bahar	Thermally-induced soft errors in nanoscale CMOS circuits.	NANOARCH	2007	DBLP DOI BibTeX RDF
1		2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH 2007, San Jose, CA, USA, October 21-22, 2007	NANOARCH	2007	DBLP BibTeX RDF
1	Dmitri B. Strukov, Konstantin K. Likharev	Prospects for the development of digital CMOL circuits.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Tamer Mohamed, Graham A. Jullien, Wael M. Badawy	Crossbar latch-based combinational and sequential logic for nano FPGA.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Dennis Huo, Qiaoyan Yu, Paul Ampadu	A ballistic nanoelectronic device simulator.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Drew C. Ness, Christian J. Hescott, David J. Lilja	Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Tzvetan S. Metodi, Andrew W. Cross, Darshan D. Thaker, Isaac L. Chuang, Frederic T. Chong	Design-space exploration of fault-tolerant building blocks for large-scale quantum computing.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Ashish Kumar Singh, Hady Ali Zeineddine, Adnan Aziz, Sriram Vishwanath, Michael Orshansky	A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Tom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi	A fast, numerical circuit-level model of carbon nanotube transistor.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Teng Wang, Pritish Narayanan, Csaba Andras Moritz	Combining 2-level logic families in grid-based nanoscale fabrics.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Zhengfei Wang, Huaixiu Zheng, Qinwei Shi, Jie Chen 0002	Emerging nanocircuit paradigm: Graphene-based electronics for nanoscale computing.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo	A shift-register-based QCA memory architecture.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Girish Venkatasubramanian, P. Oscar Boykin, Renato J. O. Figueiredo	Design of high-yield defect-tolerant self-assembled nanoscale memories.	NANOARCH	2007	DBLP DOI BibTeX RDF
1	Kyosun Kim, Ramesh Karri, Alex Orailoglu	Design automation for hybrid CMOS-nonoelectronics crossbars.	NANOARCH	2007	DBLP DOI BibTeX RDF

Publications at "NANOARCH"( http://dblp.L3S.de/Venues/NANOARCH )