Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Steve Trimberger |
Keynote 1 - Moore's law, programmable logic and reconfigurable systems. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Jan Heisswolf, Maximilian Singh, Martin Kupper, Ralf König 0001, Jürgen Becker 0001 |
Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Omar Ahmed, Shawki Areibi |
An efficient application-specific instruction-set processor for packet classification. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Jahanzeb Anwer, Sebastian Meisner, Marco Platzner |
Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Jun Rong Wang, Dan Wang, Jin-Mei Lai |
A hierarchical parallel evolvable hardware based on network on chip. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Swapnil Haria, Viktor K. Prasanna |
Optimal mapping of multiple packet lookup schemes onto FPGA. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | |
2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013, Cancun, Mexico, December 9-11, 2013 |
ReConFig |
2013 |
DBLP BibTeX RDF |
|
1 | Hamed Sajjadi Kia, Mohammad A. Zare, Rajesh G. Kavasseri, Cristinel Ababei |
Dynamic simulation of direct torque control of induction motors with FPGA based accelerators. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Keisuke Dohi, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri |
Performance modeling and optimization of 3-D stencil computation on a stream-based FPGA accelerator. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Maya B. Gokhale |
Keynote 3 - Extreme scale challenges: Can reconfigurable computing come to the rescue? |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Christian de Schryver, Philipp Schläfer, Norbert Wehn, Thomas Fischer 0003, Arnd Poetzsch-Heffter |
Loopy - An open-source TCP/IP rapid prototyping and validation framework. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Guillaume Reymond, Victor Murillo |
A hardware pipelined architecture of a scalable Montgomery modular multiplier over GF(2m). |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Roberto Perez-Andrade, César Torres-Huitzil, René Cumplido, Juan M. Campos |
Processor arrays generation for matrix algorithms used in embedded platforms. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Yu Bai 0004, Mohammed Alawad, Michael Riera, Mingjie Lin |
Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Sam Skalicky, Sonia López, Marcin Lukowiak |
Distributed execution of transmural electrophysiological imaging with CPU, GPU, and FPGA. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Alberto Rodriguez-Garcia, Luis Pizano-Escalante, Ramón Parra-Michel, Omar Humberto Longoria-Gandara, Joaquín Cortez González |
Fast fixed-point divider based on Newton-Raphson method and piecewise polynomial approximation. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Kevin L. Thomas, Michael S. Thompson |
Performance modeling of reconfigurable distributed systems based on the opensparc FPGA board and the SIRC communication framework. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Fabian May, Friedrich Mayer-Lindenberg |
ModHDL: A modular and expandable language for developing synchronous hardware. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Marco Antonio Soto Hernandez, Oscar Alvarado Nava, Eduardo Rodriguez-Martinez, Francisco Javier Zaragoza Martínez |
Tree-less Huffman coding algorithm for embedded systems. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings |
Optimization techniques for a high level synthesis implementation of the Sobel filter. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Abdulhadi Shoufan |
A fault attack on a hardware-based implementation of the secure hash algorithm SHA-512. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Paolo Maistri, Sébastien Tiran, Philippe Maurine, Israel Koren, Régis Leveugle |
Countermeasures against EM analysis for a secured FPGA-based AES implementation. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Zoltán Endre Rákossy, Axel Acosta-Aponte, Anupam Chattopadhyay |
Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Angel Gallego, Javier Mora 0001, Andrés Otero, Eduardo de la Torre, Teresa Riesgo |
A scalable evolvable hardware processing array. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | B. I. Gea-Garcia, J. L. Vázquez-Avila, Remberto Sandoval-Arechiga, J. L. Pizano-Escalante, Ramón Parra-Michel, Mario Siller |
NoC-based hardware function libraries for running multiple DSP algorithms. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura |
A restricted dynamically reconfigurable architecture for low power processors. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Michal Varchola, Milos Drutarovský, Viktor Fischer |
New universal element with integrated PUF and TRNG capability. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Victor Dumitriu, Lev Kirischian |
SoC self-integration mechanism for dynamic reconfigurable systems based on collaborative macro-function units. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Andrea Sanny, Viktor K. Prasanna |
Energy-efficient Median filter on FPGA. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Timm Bostelmann, Sergei Sawitzki |
Improving FPGA placement with a self-organizing map. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Salvador Ibarra-Delgado, Manuel Hernandez Calviño, Nicolás Guil Mata, Juan Gómez-Luna |
A robust and low resource FPGA-based stereoscopic vision algorithm. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Remi Chaintreuil, Rie Uno, Hideharu Amano |
MCMA: A modular processing elements array based low-power coarse-grained reconfigurable accelerator. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Garbi Singla, Félix Tobajas, Valentin de Armas |
Video super resolution algorithm implemented on a low-cost NoC-based MPSoC platform. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko |
FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Muhammed Al Kadi, Patrick Rudolph, Diana Göhringer, Michael Hübner 0001 |
Dynamic and partial reconfiguration of Zynq 7000 under Linux. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Miaoqing Huang, Shiming Li |
A delay-based PUF design using multiplexer chains. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Qingyu Liu, Yuchun Ma, Yu Wang 0002, Wayne Luk, Jinian Bian |
RALP: Reconvergence-aware layer partitioning for 3D FPGAs. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Gary Plumbridge, Neil C. Audsley |
Programming FPGA based NoCs with Java. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Poona Bahrebar, Dirk Stroobandt |
The Hamiltonian-based odd-even turn model for adaptive routing in interconnection networks. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Jo Vliegen, Nele Mentens, Ingrid Verbauwhede |
A single-chip solution for the secure remote configuration of FPGAs using bitstream compression. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez |
Improved method for parallel AES-GCM cores using FPGAs. |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Vinod Pangracious, Habib Mehrez, Nizar Beltaief, Zied Marrakchi, Umer Farooq 0001 |
Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). |
ReConFig |
2013 |
DBLP DOI BibTeX RDF |
|
1 | Dawood Alnajiar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama |
Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Gilberto Ochoa-Ruiz, Ouassila Labbani-Narsis, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser |
Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Robin Bonamy, Daniel Chillet, Sébastien Bilavarn, Olivier Sentieys |
Power consumption model for partial and dynamic reconfiguration. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Johannes Romoth, Dirk Jungewelter, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert 0001 |
Optimizing inter-FPGA communication by automatic channel adaptation. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García |
A VLSI architecture for the K-best Sphere-Decoder in MIMO systems. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Markus Happe, Hendrik Hangmann, Andreas Agne, Christian Plessl |
Eight ways to put your FPGA on fire - A systematic study of heat generators. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Bruno de Abreu Silva, Lucas Albers Cuminato, Vanderlei Bonato |
Reducing the overall cache miss rate using different cache sizes for Heterogeneous Multi-core Processors. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner 0001, Jürgen Becker 0001 |
Determination of on-chip temperature gradients on reconfigurable hardware. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Kaveh Aasaraai, Andreas Moshovos |
SPREX: A soft processor with Runahead execution. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Oguzhan Erdem, Aydin Carus, Hoang Le |
Compact trie forest: Scalable architecture for IP lookup on FPGAs. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Matthias Birk, Matthias Norbert Balzer, Nicole V. Ruiter, Jürgen Becker 0001 |
Comparison of processing performance and architectural efficiency metrics for FPGAs and GPUs in 3D Ultrasound Computer Tomography. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Laurent Gantel, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, François Verdier |
Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Alex A. Birklykke, Yannick Le Moullec, Lars K. Alminde, Ramjee Prasad |
An automated test framework for experimenting with stochastic behavior in reconfigurable logic. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Pedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira |
A scalable array for Cellular Genetic Algorithms: TSP as case study. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jeremy Abramson, Pedro C. Diniz |
Resiliency-aware Scheduling for reconfigurable VLIW processors. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Razvan Nane, Vlad Mihai Sima, Koen Bertels |
A lightweight speculative and predicative scheme for hardware execution. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | David Castells-Rufas, Oscar Vila-Closas, Jordi Carrabina |
Design of a multi-soft-core based Laser Marking controller. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Matthias Pohl, Michael Schaeferling, Gundolf Kiefer, Plamen Petrow, Egmont Woitzel, Frank Papenfuss |
An efficient and scalable architecture for real-time distortion removal and rectification of live camera images. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Nashwa Elaraby, Iyad Obeid |
A model design of a 2560-channel neural spike detection platform. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Yuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi |
A novel physical defects recovery technique for FPGA-IP cores. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Sen Ma, Miaoqing Huang, David Andrews 0001 |
Developing application-specific multiprocessor platforms on FPGAs. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Andrés Otero, Eduardo de la Torre, Teresa Riesgo |
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Turhan Karadeniz, Lotfi Mhamdi, Kees Goossens, J. J. Garcia-Luna-Aceves |
Hardware design and implementation of a Network-on-Chip based load balancing switch fabric. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Christina Gimmler-Dumont, Philipp Schläfer, Norbert Wehn |
FPGA-based rapid prototyping platform for MIMO-BICM design space exploration. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Tobias Kenter, Henning Schmitz, Christian Plessl |
Pragma based parallelization - Trading hardware efficiency for ease of use? |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Vincent Mirian, Paul Chow |
An implementation of a directory protocol for a cache coherent system on FPGAs. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Mohd Nazrin Md. Isa, Khaled Benkrid, Thomas Clayton |
A novel efficient FPGA architecture for HMMER acceleration. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Lubos Gaspar, Viktor Fischer, Tim Güneysu, Zouha Cherif Jouini |
Two IP protection schemes for multi-FPGA systems. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Cuong Pham-Quoc, Zaid Al-Ars, Koen Bertels |
A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Mickaël Dardaillon, Cédric Lauradoux, Tanguy Risset |
Hardware implementation of the GPS authentication. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Benedikt Driessen, Tim Güneysu, Elif Bilge Kavun, Oliver Mischke, Christof Paar, Thomas Pöppelmann |
IPSecco: A lightweight and reconfigurable IPSec core. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Hugo A. Andrade, Arkadeb Ghosal, Kaushik Ravindran, Brian L. Evans |
A methodology for the design and deployment of reliable systems on heterogeneous platforms. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Kliem, Sven-Ole Voigt |
A multi-core FPGA-based SoC architecture with domain segregation. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ling Liu, Jeremia Bär, Felix Friedrich, Jürg Gutknecht, Shiao-Li Tsao |
A low power configurable SoC for simulating delay-based audio effects. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Andy Caley Data, Kent Gilson |
Isolation of behavior design from system implementation. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Adrian Alin Lifa, Petru Eles, Zebo Peng |
Minimization of average execution time based on speculative FPGA configuration prefetch. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Rahul R. Sharma, Yamuna Rajasekhar, Ron Sass |
Exploring hardware work queue support for lightweight threads in MPSoCs. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jose Hugo Barron-Zambrano, César Torres-Huitzil, Horacio Rostro-González |
Versatile FPGA-based locomotion platform for legged robots. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Vianney Lapotre, Guy Gogniat, Jean-Philippe Diguet, Salim Haddad, Amer Baghdadi |
An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Zoltán Endre Rákossy, Tejas Naphade, Anupam Chattopadhyay |
Design and analysis of layered coarse-grained reconfigurable architecture. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Tannous Frangieh, Peter Athanas |
A design assembly framework for FPGA back-end acceleration. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Luis Morales-Velazquez, Roque Alfredo Osornio-Rios, René de Jesús Romero-Troncoso |
FPGA embedded single-cycle 16-bit microprocessor and tools. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Tobias Ziermann, Alexander Butiu, Jürgen Teich, Daniel Ziener |
FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN). |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Ashraful Alam, Zain-ul-Abdin, Bertil Svensson |
Parallelization of the estimation algorithm of the 3D structure tensor. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Andrey Bogdanov, Amir Moradi 0001, Tolga Yalçin |
Efficient and side-channel resistant authenticated encryption of FPGA bitstreams. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Venkatasubramanian Viswanathan, Benjamin Nakache, Rabie Ben Atitallah, Maurice Nakache, Jean-Luc Dekeyser |
Dynamic reconfiguration of modular I/O IP cores for avionic applications. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | A. D. Santana Gil, Manuel Hernandez Calviño, Francisco Javier Quiles-Latorre, Ezequiel Herruzo Gomez, José Ignacio Benavides Benítez |
Optimizing the physical implementation of a reconfigurable cache. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Da Tong, Yi-Hua E. Yang, Viktor K. Prasanna |
A memory efficient IPv6 lookup engine on FPGA. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Mariem Turki, Habib Mehrez, Zied Marrakchi |
Multi-FPGA prototyping environment: Large benchmark generation and signals routing. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez |
Efficient parallel-pipelined GHASH for message authentication. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Marc-André Daigneault, Jean-Pierre David |
Synchronized-transfer-level design methodology applied to hardware matrix multiplication. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Paulo C. Santos 0001, Gabriel L. Nazar, Luigi Carro, Fakhar Anjam, Stephan Wong |
Adapting communication for adaptable processors: A multi-axis reconfiguration approach. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Yukinori Sato, Yasushi Inoguchi, Wayne Luk, Tadao Nakamura |
Evaluating reconfigurable dataflow computing using the Himeno benchmark. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Andrey Bogdanov, Elif Bilge Kavun, Elmar Tischhauser, Tolga Yalçin |
Efficient reconfigurable hardware architecture for accurately computing success probability and data complexity of linear attacks. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | |
2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012, Cancun, Mexico, December 5-7, 2012 |
ReConFig |
2012 |
DBLP BibTeX RDF |
|
1 | Shweta Jain-Mendon, Ron Sass |
A case study of streaming storage format for sparse matrices. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Swapnil Haria, Thilan Ganegedara, Viktor K. Prasanna |
Power-efficient and scalable virtual router architecture on FPGA. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|
1 | Jaime J. Garnica, Sergio López-Buedo, Víctor López 0004, Javier Aracil 0001, José María Gómez Hidalgo |
A FPGA-based scalable architecture for URL legal filtering in 100GbE networks. |
ReConFig |
2012 |
DBLP DOI BibTeX RDF |
|