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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 1076 publication records. Showing 1076 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Stephan Wong |
Exploring ILP and TLP on a Polymorphic VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 3-6, 2017, Proceedings, pp. 177-189, 2017, Springer, 978-3-319-54998-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Sensen Hu, Anthony Brandon, Qi Guo, Yizhuo Wang |
Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings, pp. 3-15, 2017, 978-3-319-56257-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Joost Hoozemans, Rolf Heij, Jeroen van Straten, Zaid Al-Ars |
VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings, pp. 36-43, 2017, 978-3-319-56257-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Joost Hoozemans, Jeroen van Straten, Stephan Wong |
Using a polymorphic VLIW processor to improve schedulability and performance for mixed-criticality systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2017, Hsinchu, Taiwan, August 16-18, 2017, pp. 1-9, 2017, IEEE Computer Society, 978-1-5386-1898-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys |
Run-time Instruction Replication for permanent and soft error mitigation in VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 15th IEEE International New Circuits and Systems Conference, NEWCAS 2017, Strasbourg, France, June 25-28, 2017, pp. 321-324, 2017, IEEE, 978-1-5090-4991-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Rui Chang, Jun Wu 0006, Haoqi Ren |
A compilation method for zero overhead loop in DSPs with VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCSP ![In: 9th International Conference on Wireless Communications and Signal Processing, WCSP 2017, Nanjing, China, October 11-13, 2017, pp. 1-7, 2017, IEEE, 978-1-5386-2062-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Christopher Seifert, Joachim Thiemann, Lukas Gerlach 0001, Tobias Volkmar, Guillermo Payá Vayá, Holger Blume, Steven van de Par |
Real-time implementation of a GMM-based binaural localization algorithm on a VLIW-SIMD processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: 2017 IEEE International Conference on Multimedia and Expo, ICME 2017, Hong Kong, China, July 10-14, 2017, pp. 145-150, 2017, IEEE Computer Society, 978-1-5090-6067-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Mohamed El-Hadedy 0001, Xinfei Guo, Mircea R. Stan, Kevin Skadron |
PPE-ARX: Area- and power-efficient VLIW programmable processing element for IoT crypto-systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: 2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017, Pasadena, CA, USA, July 24-27, 2017, pp. 153-160, 2017, IEEE, 978-1-5386-3439-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Cuong Pham-Quoc, Binh Kieu-Do-Nguyen, Anh-Vu Dinh-Duc |
BKVex: An Adaptable VLIW Processor and Design Framework for Reconfigurable Computing Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACOMP ![In: International Conference on Advanced Computing and Applications, ACOMP 2017, Ho Chi Minh City, Vietnam, November 29 - December 1, 2017, pp. 39-46, 2017, IEEE Computer Society, 978-1-5386-0607-0. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Wei Huang, Zhonghe Guo, Xiaohua Song, Fei Sun |
A cluster-scalable VLIW cryptography processor with high performance and energy efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 414-417, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Mohamed Najoui, Anas Hatim, Said Belkouch |
Novel parallel Givens QR decomposition implementation on VLIW architecture with Efficient memory access for real time image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BDCA ![In: Proceedings of the 2nd international Conference on Big Data, Cloud and Applications, BDCA 2017, Tetouan, Morocco, March 29-30, 2017, pp. 89:1-89:6, 2017, ACM, 978-1-4503-4852-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Johnny Öberg |
Synthesis of VLIW Accelerators from Formal Descriptions in a Real-Time Multi-Core Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAworld ![In: Proceedings of the 14th FPGAworld Conference, FPGAworld '17, Stockholm, Sweden, September 19, 2017, pp. 23-29, 2017, ACM, 978-1-4503-5154-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Hong Ye, Naijie Gu, Xiaoci Zhang, Chuanwen Lin |
An efficient conflict-free memory-addressing unit for SIMD VLIW DSP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPECTS ![In: International Symposium on Performance Evaluation of Computer and Telecommunication Systems, SPECTS 2017, Seattle, WA, USA, July 9-12, 2017, pp. 1-7, 2017, IEEE, 978-1-5386-0529-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Bruce L. Jacob |
The Case for VLIW-CMP as a Building Block for Exascale. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 15(1), pp. 54-57, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Yumin Hou, Hu He 0001, Xu Yang 0003, Deyuan Guo, Xu Wang, Jiawei Fu, Keni Qiu |
FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2016, pp. 8787919:1-8787919:12, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Mahmood Ahmadi, Ehsan Zadkhosh |
A customized and reconfigurable VLIW-based packet classifier on ρ-VEX. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. High Speed Networks ![In: J. High Speed Networks 22(3), pp. 177-192, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Vassilios A. Chouliaras, David Stevens, Vincent M. Dwyer |
VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 47, pp. 466-485, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Renan Augusto Starke, Andreu Carminati, Rômulo Silva de Oliveira |
Evaluating the Design of a VLIW Processor for Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 15(3), pp. 46:1-46:26, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Anderson L. Sartor, Arthur Francisco Lorenzon, Luigi Carro, Fernanda Lima Kastensmidt, Stephan Wong, Antonio C. S. Beck |
Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 13(2), pp. 13:1-13:21, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Mona Aghababaeetafreshi, Lasse Lehtonen, Toni Levanen, Mikko Valkama, Jarmo Takala |
IEEE 802.11ac MIMO Transceiver Baseband Processing on a VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 85(1), pp. 167-182, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Lei Yang, Lei Wang, Xing Zhang, Donglin Wang |
An approach to build cycle accurate full system VLIW simulation platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Simul. Model. Pract. Theory ![In: Simul. Model. Pract. Theory 67, pp. 14-28, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Mounir Bahtat, Said Belkouch, Philippe Elleaume, Philippe Le Gall |
Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Adv. Signal Process. ![In: EURASIP J. Adv. Signal Process. 2016, pp. 38, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Samuel J. Parker, Vassilios A. Chouliaras |
An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 68, pp. 17-37, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Tiago T. Jost, Gabriel L. Nazar, Luigi Carro |
Improving performance in VLIW soft-core processors through software-controlled scratchpads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016, pp. 172-179, 2016, IEEE, 978-1-5090-3076-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Juan Sebastian Piedrahita Giraldo, Luigi Carro, Stephan Wong, Antonio C. S. Beck |
Leveraging Compiler Support on VLIW Processors for Efficient Power Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016, pp. 502-507, 2016, IEEE Computer Society, 978-1-4673-9039-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Samira Nazari, Maryam Hassani, Ali Azarpeyvand |
An ultra-fast multi-objective optimization algorithm for VLIW architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2016 IEEE East-West Design & Test Symposium, EWDTS 2016, Yerevan, Armenia, October 14-17, 2016, pp. 1-7, 2016, IEEE Computer Society, 978-1-5090-0693-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Keni Qiu, Weigong Zhang, Xiaoqiang Wu, Xiaoyan Zhu, Jing Wang 0055, Yuanchao Xu 0002, Chun Jason Xue |
Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 31st Annual ACM Symposium on Applied Computing, Pisa, Italy, April 4-8, 2016, pp. 1710-1716, 2016, ACM, 978-1-4503-3739-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Qi Guo, Anderson Luiz Sartor, Anthony Brandon, Antonio C. S. Beck, Xuehai Zhou, Stephan Wong |
Run-time phase prediction for a reconfigurable VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016, pp. 1634-1639, 2016, IEEE, 978-3-9815-3707-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
16 | Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen |
Variable-length VLIW encoding for code size reduction in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016, pp. 296-299, 2016, IEEE, 978-1-5090-1367-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Anderson Luiz Sartor, Stephan Wong, Antonio C. S. Beck |
Adaptive ILP control to increase fault tolerance for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 27th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2016, London, United Kingdom, July 6-8, 2016, pp. 9-16, 2016, IEEE Computer Society, 978-1-5090-1503-0. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Dan Iorga, Razvan Nane, Yi Lu 0004, Edwin van Dalen, Koen Bertels |
An Image Processing VLIW Architecture for Real-Time Depth Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 28th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2016, Los Angeles, CA, USA, October 26-28, 2016, pp. 158-165, 2016, IEEE Computer Society, 978-1-5090-6108-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Yang Su, Yuechuan Wei, Mingshu Zhang |
Research and Design of Dedicated Instruction for Reconfigurable Matrix Multiplication of VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INCoS ![In: 2016 International Conference on Intelligent Networking and Collaborative Systems, INCoS 2016, Ostrawva, Czech Republic, September 7-9, 2016, pp. 324-327, 2016, IEEE, 978-1-5090-4124-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Yong Zhao, Hans G. Kerkhoff |
A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016, Istanbul, Turkey, April 12-14, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0336-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Boris Hübener |
Analyse verschiedener Architekturvarianten des CoreVA-VLIW-Prozessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2016 |
RDF |
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16 | Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart |
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(1), pp. 125-136, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Gorker Alp Malazgirt, Arda Yurdakul, Smaïl Niar |
Customizing VLIW processors from dynamically profiled execution traces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 39(8), pp. 656-673, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Mostafa I. Soliman |
Merging VLIW and vector processing techniques for a simple, high-performance processor architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 46(7), pp. 637-655, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Xu Yang 0003, Mingbin Zeng, Yanjun Zhang |
Implementing and Optimizing of Entire System Toolkit of VLIW DSP Processors for Embedded Sensor-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. Program. ![In: Sci. Program. 2015, pp. 507896:1-507896:7, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Joost Hoozemans, Stephan Wong, Zaid Al-Ars |
Using VLIW softcore processors for image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2015, Samos, Greece, July 19-23, 2015, pp. 315-318, 2015, IEEE, 978-1-4673-7311-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Anderson Luiz Sartor, Arthur Francisco Lorenzon, Luigi Carro, Fernanda Gusmão de Lima Kastensmidt, Stephan Wong, Antonio Carlos Schneider Beck |
A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015, pp. 485-490, 2015, IEEE Computer Society, 978-1-4799-8719-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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16 | Yong Zhao, Hans G. Kerkhoff |
Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2015 Euromicro Conference on Digital System Design, DSD 2015, Madeira, Portugal, August 26-28, 2015, pp. 353-358, 2015, IEEE Computer Society, 978-1-4673-8035-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Mitsuru Tomono, Makiko Ito, Yoshitaka Nomura, Makoto Mouri, Yoshio Hirose |
An energy-efficient SIMD DSP with multiple VLIW configurations and an advanced memory access unit for LTE-A modem LSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMV ![In: Eighth International Conference on Machine Vision, ICMV 2015, Barcelona, Spain, 19-20 November 2015, pp. 98751T, 2015, SPIE, 9781510601161. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Joost Hoozemans, Jens Johansen, Jeroen van Straten, Anthony Brandon, Stephan Wong |
Multiple contexts in a multi-ported VLIW register file implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, December 7-9, 2015, pp. 1-6, 2015, IEEE, 978-1-4673-9406-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Arthur Francisco Lorenzon, Anderson Luiz Sartor, Antonio Carlos Schneider Beck, Stephan Wong |
A sparse VLIW instruction encoding scheme compatible with generic binaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, December 7-9, 2015, pp. 1-7, 2015, IEEE, 978-1-4673-9406-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Maurice Peemen, Wisnu Pramadi, Bart Mesman, Henk Corporaal |
VLIW Code Generation for a Convolutional Network Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015, Sankt Goar, Germany, June 1-3, 2015, pp. 117-120, 2015, ACM, 978-1-4503-3593-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Haoqi Ren, Zhifeng Zhang, Jun Wu 0006 |
A VLIW DSP for communication applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IGSC ![In: Sixth International Green and Sustainable Computing Conference, IGSC 2015, Las Vegas, NV, USA, December 14-16, 2015, pp. 1-5, 2015, IEEE Computer Society, 978-1-5090-0172-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume |
Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings, pp. 401-410, 2015, Springer, 978-3-319-16213-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Erkan Diken, Lech Józwiak |
A compilation technique and performance profits for VLIW with heterogeneous vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 4th Mediterranean Conference on Embedded Computing, MECO 2015, Budva, Montenegro, June 14-18, 2015, pp. 9-12, 2015, IEEE, 978-1-4799-8999-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Lichao Zhang, Xuetao Wu, Yiqiang Zhao |
Instruction-Level Instantaneous Power Modeling for VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UIC/ATC/ScalCom ![In: 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), Beijing, China, August 10-14, 2015, pp. 1451-1456, 2015, IEEE Computer Society, 978-1-4673-7211-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Juan Sebastian Piedrahita Giraldo, Anderson Luiz Sartor, Luigi Carro, Stephan Wong, Antonio Carlos Schneider Beck |
Evaluation of energy savings on a VLIW processor through dynamic issue-width adaptation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RSP ![In: 2015 International Symposium on Rapid System Prototyping, RSP 2015, Amsterdam, The Netherlands, October 8-9, 2015, pp. 11-17, 2015, IEEE, 978-1-4673-8276-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Guoyue Jiang, Zhaolin Li, Fang Wang, Shaojun Wei |
Scheduling stream programs with improving arithmetic unit usage on NoC-based VLIW multi-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 12th ACM International Conference on Computing Frontiers, CF'15, Ischia, Italy, May 18-21, 2015, pp. 18:1-18:8, 2015, ACM, 978-1-4503-3358-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Erkan Diken, Martin J. O'Riordan, Roel Jordans, Lech Józwiak, Henk Corporaal, David Moloney |
Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 26th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2015, Toronto, ON, Canada, July 27-29, 2015, pp. 181-188, 2015, IEEE Computer Society, 978-1-4799-1925-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Yong Zhao, Hans G. Kerkhoff |
Application of functional IDDQ testing in a VLIW processor towards detection of aging degradation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, Napoli, Italy, April 21-23, 2015, pp. 1-5, 2015, IEEE, 978-1-4799-1999-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Renan Augusto Starke, Andreu Carminati, Rômulo Silva de Oliveira |
Investigating a four-issue deterministic VLIW architecture for real-time systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INDIN ![In: 13th IEEE International Conference on Industrial Informatics, INDIN 2015, Cambridge, United Kingdom, July 22-24, 2015, pp. 215-220, 2015, IEEE, 978-1-4799-6649-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Samuel J. Parker |
An automated OpenCL FPGA compilation framework targeting a configurable, VLIW chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2015 |
RDF |
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16 | Yuanwu Lei, Lei Guo 0029, Yong Dou, Sheng Ma, Jinbo Xu |
FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 7(2), pp. 8:1-8:21, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Cheng-Yu Lee, Min-Chin Hung, Rong-Guey Chang |
Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 26(1), pp. 134-151, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(4), pp. 813-823, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Shan Cao, Zhaolin Li, Fang Wang, Shaojun Wei |
Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(6), pp. 1416-1428, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Yazhi Huang, Liang Shi, Jianhua Li 0003, Qing'an Li, Chun Jason Xue |
WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(1), pp. 168-180, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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16 | Ittetsu Taniguchi, Kohei Aoki, Hiroyuki Tomiyama, Praveen Raghavan, Francky Catthoor, Masahiro Fukui |
Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(2), pp. 606-615, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Vincent Brost, Fan Yang 0019, Charles Meunier |
Flexible VLIW processor based on FPGA for efficient embedded real-time image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Real Time Image Process. ![In: J. Real Time Image Process. 9(1), pp. 47-59, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Xu Yang 0003 |
Path-Dividing Based Scheduling Algorithm for Reducing Energy Consumption of Clustered VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 63(10), pp. 2526-2539, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Erkan Diken, Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal, Felipe Augusto Chies |
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 38(8), pp. 947-959, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Zhibin Liang, Wei Zhang 0055, Yung-Cheng Ma |
Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 11(2), pp. 20:1-20:26, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda |
Shared-port register file architecture for low-energy VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 11(1), pp. 1:1-1:32, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Jinyong Lee, Jongwon Lee, Jongeun Lee, Yunheung Paek |
Improving performance of loops on DIAM-based VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2014, LCTES '14, Edinburgh, United Kingdom - June 12 - 13, 2014, pp. 135-144, 2014, ACM, 978-1-4503-2877-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Mounir Bahtat, Said Belkouch, Philippe Elleaume, Phillipe Le Gall |
Fast enumeration-based modulo scheduling heuristic for VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 26th International Conference on Microelectronics, ICM 2014, Doha, Qatar, December 14-17, 2014, pp. 116-119, 2014, IEEE, 978-1-4799-8153-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
Soft error effects analysis and mitigation in VLIW safety-critical applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 22nd International Conference on Very Large Scale Integration, VLSI-SoC, Playa del Carmen, Mexico, October 6-8, 2014, pp. 1-6, 2014, IEEE, 978-1-4799-6016-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Xuemeng Zhang, Hui Wu 0001, Haiyan Sun, Jingling Xue |
Lifetime holes aware register allocation for clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, pp. 1-4, 2014, European Design and Automation Association, 978-3-9815370-2-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Oliver Stecklina, Michael Methfessel |
A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 17th Euromicro Conference on Digital System Design, DSD 2014, Verona, Italy, August 27-29, 2014, pp. 559-566, 2014, IEEE Computer Society, 978-1-4799-5793-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Miguel Tairum Cruz, Pedro Tomás, Nuno Roma |
Low-power vectorial VLIW architecture for maximum parallelism exploitation of dynamic programming algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCS ![In: International Conference on High Performance Computing & Simulation, HPCS 2014, Bologna, Italy, 21-25 July, 2014, pp. 88-95, 2014, IEEE, 978-1-4799-5312-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Yangzhao Yang, Naijie Gu, Kaixin Ren, Bingqing Hu |
An Approach to Enhance Loop Performance for Multicluster VLIW DSP Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS Workshops ![In: ARCS 2014 - 27th International Conference on Architecture of Computing Systems, Workshop Proceedings, February 25-28, 2014, Luebeck, Germany, University of Luebeck, Institute of Computer Engineering, pp. 1-8, 2014, VDE Verlag / IEEE Xplore, 978-3-8007-3579-2. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
|
16 | Mona Aghababaeetafreshi, Lasse Lehtonen, Toni Levanen, Mikko Valkama, Jarmo Takala |
IEEE 802.11ac MIMO receiver baseband processing on customized VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: 2014 IEEE Workshop on Signal Processing Systems, SiPS 2014, Belfast, United Kingdom, October 20-22, 2014, pp. 232-237, 2014, IEEE, 978-14799-6588-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Julian Hartig, Lukas Gerlach 0001, Guillermo Payá Vayá, Holger Blume |
Customizing a VLIW-SIMD application-specific instruction-set processor for hearing aid devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: 2014 IEEE Workshop on Signal Processing Systems, SiPS 2014, Belfast, United Kingdom, October 20-22, 2014, pp. 115-120, 2014, IEEE, 978-14799-6588-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Mona Aghababaeetafreshi, Lasse Lehtonen, Maliheh Soleimani, Mikko Valkama, Jarmo Takala |
IEEE 802.11AC MIMO transmitter baseband processing on customized VLIW processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2014, Florence, Italy, May 4-9, 2014, pp. 7500-7504, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Martti Forsell, Jussi Roivainen |
REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2014, Pacific Grove, CA, USA, November 2-5, 2014, pp. 1709-1713, 2014, IEEE, 978-1-4799-8297-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Roel Jordans, Lech Józwiak, Henk Corporaal |
Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 3rd Mediterranean Conference on Embedded Computing, MECO 2014, Budva, Montenegro, June 15-19, 2014, pp. 32-35, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Erkan Diken, Roel Jordans, Lech Józwiak, Henk Corporaal |
Construction and exploitation of VLIW asips with multiple vector-widths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 3rd Mediterranean Conference on Embedded Computing, MECO 2014, Budva, Montenegro, June 15-19, 2014, pp. 244-247, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack |
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, pp. 452-453, 2014, IEEE, 978-1-4799-0918-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Boris Hübener, Gregor Sievers, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert 0001 |
CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014, Milano, Italy, August 26-28, 2014, pp. 9-16, 2014, IEEE Computer Society, 978-0-7695-5249-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Davide Patti, Maurizio Palesi, Vincenzo Catania |
Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSOC ![In: Modern Trends and Techniques in Computer Science - 3rd Computer Science On-line Conference 2014 (CSOC 2014), pp. 203-212, 2014, Springer, 978-3-319-06739-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Taisong Jin, Minwook Ahn, Donghoon Yoo, Dongkwan Suh, Yoonseo Choi, Do Hyung Kim 0002, Shihwa Lee |
Nop compression scheme for high speed DSPs based on VLIW architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: IEEE International Conference on Consumer Electronics, ICCE 2014, Las Vegas, NV, USA, January 10-13, 2014, pp. 304-305, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Venkata Ganapathi Puppala |
A VLIW-Vector co-processor design for accelerating Basic Linear Algebraic Operations in OpenCV. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, India, July 16-18, 2014, pp. 1-6, 2014, IEEE, 978-1-4799-5088-1. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Christoph W. Kessler |
Compiling for VLIW DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook of Signal Processing Systems ![In: Handbook of Signal Processing Systems, pp. 1177-1214, 2013, Springer, 978-1-4614-6858-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Xuemeng Zhang, Hui Wu 0001, Jingling Xue |
Instruction scheduling with k-successor tree for clustered VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 17(2), pp. 439-458, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Jongwon Lee, Yohan Ko, Kyoungwoo Lee, Jonghee M. Youn, Yunheung Paek |
Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 9(4), pp. 48:1-48:24, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Yuanwu Lei, Yong Dou, Lei Guo 0029, Jinbo Xu, Jie Zhou 0007, Yazhuo Dong, Hongjian Li |
VLIW coprocessor for IEEE-754 quadruple-precision elementary functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 10(3), pp. 12:1-12:22, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Jongwon Lee, Jonghee M. Youn, Doosan Cho, Yunheung Paek |
Reducing instruction bit-width for low-power VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 18(2), pp. 25:1-25:32, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Petr Pfeifer, Zdenek Plíva, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus |
On performance estimation of a scalable VLIW soft-core in XILINX FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013, pp. 181-186, 2013, IEEE Computer Society, 978-1-4673-6135-4. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
Partition-Based Faults Diagnosis of a VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC (Selected Papers) ![In: VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended Selected Papers, pp. 208-226, 2013, Springer, 978-3-319-23798-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Davide Sabena, Matteo Sonza Reorda, Luca Sterpone |
On the development of diagnostic test programs for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013, pp. 84-89, 2013, IEEE, 978-1-4799-0522-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Amir Hossein Ashouri, Vittorio Zaccaria, Sotirios Xydis, Gianluca Palermo, Cristina Silvano |
A framework for Compiler Level statistical analysis over customized VLIW architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013, pp. 124-129, 2013, IEEE, 978-1-4799-0522-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Anthony Brandon, Stephan Wong |
Support for dynamic issue width in VLIW processors using generic binaries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 827-832, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Mian Muhammad Hamayun, Frédéric Pétrot, Nicolas Fournel |
Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, pp. 576-581, 2013, IEEE, 978-1-4673-3029-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Gregor Sievers, Peter Christ, Julian Einhaus, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert 0001 |
Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCHIP ![In: 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, pp. 1-4, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Kalin Ovtcharov, Ilian Tili, J. Gregory Steffan |
TILT: A multithreaded VLIW soft processor family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 23rd International Conference on Field programmable Logic and Applications, FPL 2013, Porto, Portugal, September 2-4, 2013, pp. 1-4, 2013, IEEE, 978-1-4799-0004-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Kalin Ovtcharov, Ilian Tili, J. Gregory Steffan |
A Multithreaded VLIW Soft Processor Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2013, Seattle, WA, USA, April 28-30, 2013, pp. 232, 2013, IEEE Computer Society, 978-1-4673-6005-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Fakhar Anjam, Stephan Wong |
Configurable Fault-Tolerance for a Configurable VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications - 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings, pp. 167-178, 2013, Springer, 978-3-642-36811-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal |
Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MECO ![In: 2nd Mediterranean Conference on Embedded Computing, MECO 2013, Budva, Montenegro, June 15-20, 2013, pp. 38-41, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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