Search results for "VLIW"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Stephan Wong	Exploring ILP and TLP on a Polymorphic VLIW Processor.	ARCS	2017	DBLP DOI BibTeX RDF
16	Sensen Hu, Anthony Brandon, Qi Guo, Yizhuo Wang	Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor.	ARC	2017	DBLP DOI BibTeX RDF
16	Joost Hoozemans, Rolf Heij, Jeroen van Straten, Zaid Al-Ars	VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications.	ARC	2017	DBLP DOI BibTeX RDF
16	Joost Hoozemans, Jeroen van Straten, Stephan Wong	Using a polymorphic VLIW processor to improve schedulability and performance for mixed-criticality systems.	RTCSA	2017	DBLP DOI BibTeX RDF
16	Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys	Run-time Instruction Replication for permanent and soft error mitigation in VLIW processors.	NEWCAS	2017	DBLP DOI BibTeX RDF
16	Rui Chang, Jun Wu 0006, Haoqi Ren	A compilation method for zero overhead loop in DSPs with VLIW.	WCSP	2017	DBLP DOI BibTeX RDF
16	Christopher Seifert, Joachim Thiemann, Lukas Gerlach 0001, Tobias Volkmar, Guillermo Payá Vayá, Holger Blume, Steven van de Par	Real-time implementation of a GMM-based binaural localization algorithm on a VLIW-SIMD processor.	ICME	2017	DBLP DOI BibTeX RDF
16	Mohamed El-Hadedy 0001, Xinfei Guo, Mircea R. Stan, Kevin Skadron	PPE-ARX: Area- and power-efficient VLIW programmable processing element for IoT crypto-systems.	AHS	2017	DBLP DOI BibTeX RDF
16	Cuong Pham-Quoc, Binh Kieu-Do-Nguyen, Anh-Vu Dinh-Duc	BKVex: An Adaptable VLIW Processor and Design Framework for Reconfigurable Computing Platforms.	ACOMP	2017	DBLP DOI BibTeX RDF
16	Wei Huang, Zhonghe Guo, Xiaohua Song, Fei Sun	A cluster-scalable VLIW cryptography processor with high performance and energy efficiency.	ASICON	2017	DBLP DOI BibTeX RDF
16	Mohamed Najoui, Anas Hatim, Said Belkouch	Novel parallel Givens QR decomposition implementation on VLIW architecture with Efficient memory access for real time image processing applications.	BDCA	2017	DBLP DOI BibTeX RDF
16	Johnny Öberg	Synthesis of VLIW Accelerators from Formal Descriptions in a Real-Time Multi-Core Environment.	FPGAworld	2017	DBLP DOI BibTeX RDF
16	Hong Ye, Naijie Gu, Xiaoci Zhang, Chuanwen Lin	An efficient conflict-free memory-addressing unit for SIMD VLIW DSP.	SPECTS	2017	DBLP DOI BibTeX RDF
16	Bruce L. Jacob	The Case for VLIW-CMP as a Building Block for Exascale.	IEEE Comput. Archit. Lett.	2016	DBLP DOI BibTeX RDF
16	Yumin Hou, Hu He 0001, Xu Yang 0003, Deyuan Guo, Xu Wang, Jiawei Fu, Keni Qiu	FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW.	VLSI Design	2016	DBLP DOI BibTeX RDF
16	Mahmood Ahmadi, Ehsan Zadkhosh	A customized and reconfigurable VLIW-based packet classifier on ρ-VEX.	J. High Speed Networks	2016	DBLP DOI BibTeX RDF
16	Vassilios A. Chouliaras, David Stevens, Vincent M. Dwyer	VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads.	Microprocess. Microsystems	2016	DBLP DOI BibTeX RDF
16	Renan Augusto Starke, Andreu Carminati, Rômulo Silva de Oliveira	Evaluating the Design of a VLIW Processor for Real-Time Systems.	ACM Trans. Embed. Comput. Syst.	2016	DBLP DOI BibTeX RDF
16	Anderson L. Sartor, Arthur Francisco Lorenzon, Luigi Carro, Fernanda Lima Kastensmidt, Stephan Wong, Antonio C. S. Beck	Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
16	Mona Aghababaeetafreshi, Lasse Lehtonen, Toni Levanen, Mikko Valkama, Jarmo Takala	IEEE 802.11ac MIMO Transceiver Baseband Processing on a VLIW Processor.	J. Signal Process. Syst.	2016	DBLP DOI BibTeX RDF
16	Lei Yang, Lei Wang, Xing Zhang, Donglin Wang	An approach to build cycle accurate full system VLIW simulation platform.	Simul. Model. Pract. Theory	2016	DBLP DOI BibTeX RDF
16	Mounir Bahtat, Said Belkouch, Philippe Elleaume, Philippe Le Gall	Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage.	EURASIP J. Adv. Signal Process.	2016	DBLP DOI BibTeX RDF
16	Samuel J. Parker, Vassilios A. Chouliaras	An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor.	J. Syst. Archit.	2016	DBLP DOI BibTeX RDF
16	Tiago T. Jost, Gabriel L. Nazar, Luigi Carro	Improving performance in VLIW soft-core processors through software-controlled scratchpads.	SAMOS	2016	DBLP DOI BibTeX RDF
16	Juan Sebastian Piedrahita Giraldo, Luigi Carro, Stephan Wong, Antonio C. S. Beck	Leveraging Compiler Support on VLIW Processors for Efficient Power Gating.	ISVLSI	2016	DBLP DOI BibTeX RDF
16	Samira Nazari, Maryam Hassani, Ali Azarpeyvand	An ultra-fast multi-objective optimization algorithm for VLIW architecture.	EWDTS	2016	DBLP DOI BibTeX RDF
16	Keni Qiu, Weigong Zhang, Xiaoqiang Wu, Xiaoyan Zhu, Jing Wang 0055, Yuanchao Xu 0002, Chun Jason Xue	Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors.	SAC	2016	DBLP DOI BibTeX RDF
16	Qi Guo, Anderson Luiz Sartor, Anthony Brandon, Antonio C. S. Beck, Xuehai Zhou, Stephan Wong	Run-time phase prediction for a reconfigurable VLIW processor.	DATE	2016	DBLP BibTeX RDF
16	Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen	Variable-length VLIW encoding for code size reduction in embedded processors.	SoCC	2016	DBLP DOI BibTeX RDF
16	Anderson Luiz Sartor, Stephan Wong, Antonio C. S. Beck	Adaptive ILP control to increase fault tolerance for VLIW processors.	ASAP	2016	DBLP DOI BibTeX RDF
16	Dan Iorga, Razvan Nane, Yi Lu 0004, Edwin van Dalen, Koen Bertels	An Image Processing VLIW Architecture for Real-Time Depth Detection.	SBAC-PAD	2016	DBLP DOI BibTeX RDF
16	Yang Su, Yuechuan Wei, Mingshu Zhang	Research and Design of Dedicated Instruction for Reconfigurable Matrix Multiplication of VLIW Processor.	INCoS	2016	DBLP DOI BibTeX RDF
16	Yong Zhao, Hans G. Kerkhoff	A genetic algorithm based remaining lifetime prediction for a VLIW processor employing path delay and IDDX testing.	DTIS	2016	DBLP DOI BibTeX RDF
16	Boris Hübener	Analyse verschiedener Architekturvarianten des CoreVA-VLIW-Prozessors.		2016	RDF
16	Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart	A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
16	Gorker Alp Malazgirt, Arda Yurdakul, Smaïl Niar	Customizing VLIW processors from dynamically profiled execution traces.	Microprocess. Microsystems	2015	DBLP DOI BibTeX RDF
16	Mostafa I. Soliman	Merging VLIW and vector processing techniques for a simple, high-performance processor architecture.	Microelectron. J.	2015	DBLP DOI BibTeX RDF
16	Xu Yang 0003, Mingbin Zeng, Yanjun Zhang	Implementing and Optimizing of Entire System Toolkit of VLIW DSP Processors for Embedded Sensor-Based Systems.	Sci. Program.	2015	DBLP DOI BibTeX RDF
16	Joost Hoozemans, Stephan Wong, Zaid Al-Ars	Using VLIW softcore processors for image processing applications.	SAMOS	2015	DBLP DOI BibTeX RDF
16	Anderson Luiz Sartor, Arthur Francisco Lorenzon, Luigi Carro, Fernanda Gusmão de Lima Kastensmidt, Stephan Wong, Antonio Carlos Schneider Beck	A Novel Phase-Based Low Overhead Fault Tolerance Approach for VLIW Processors.	ISVLSI	2015	DBLP DOI BibTeX RDF
16	Yong Zhao, Hans G. Kerkhoff	Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW Processor.	DSD	2015	DBLP DOI BibTeX RDF
16	Mitsuru Tomono, Makiko Ito, Yoshitaka Nomura, Makoto Mouri, Yoshio Hirose	An energy-efficient SIMD DSP with multiple VLIW configurations and an advanced memory access unit for LTE-A modem LSIs.	ICMV	2015	DBLP DOI BibTeX RDF
16	Joost Hoozemans, Jens Johansen, Jeroen van Straten, Anthony Brandon, Stephan Wong	Multiple contexts in a multi-ported VLIW register file implementation.	ReConFig	2015	DBLP DOI BibTeX RDF
16	Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Arthur Francisco Lorenzon, Anderson Luiz Sartor, Antonio Carlos Schneider Beck, Stephan Wong	A sparse VLIW instruction encoding scheme compatible with generic binaries.	ReConFig	2015	DBLP DOI BibTeX RDF
16	Maurice Peemen, Wisnu Pramadi, Bart Mesman, Henk Corporaal	VLIW Code Generation for a Convolutional Network Accelerator.	SCOPES	2015	DBLP DOI BibTeX RDF
16	Haoqi Ren, Zhifeng Zhang, Jun Wu 0006	A VLIW DSP for communication applications.	IGSC	2015	DBLP DOI BibTeX RDF
16	Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume	Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture.	ARC	2015	DBLP DOI BibTeX RDF
16	Erkan Diken, Lech Józwiak	A compilation technique and performance profits for VLIW with heterogeneous vectors.	MECO	2015	DBLP DOI BibTeX RDF
16	Lichao Zhang, Xuetao Wu, Yiqiang Zhao	Instruction-Level Instantaneous Power Modeling for VLIW Processor.	UIC/ATC/ScalCom	2015	DBLP DOI BibTeX RDF
16	Juan Sebastian Piedrahita Giraldo, Anderson Luiz Sartor, Luigi Carro, Stephan Wong, Antonio Carlos Schneider Beck	Evaluation of energy savings on a VLIW processor through dynamic issue-width adaptation.	RSP	2015	DBLP DOI BibTeX RDF
16	Guoyue Jiang, Zhaolin Li, Fang Wang, Shaojun Wei	Scheduling stream programs with improving arithmetic unit usage on NoC-based VLIW multi-core architectures.	Conf. Computing Frontiers	2015	DBLP DOI BibTeX RDF
16	Erkan Diken, Martin J. O'Riordan, Roel Jordans, Lech Józwiak, Henk Corporaal, David Moloney	Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths.	ASAP	2015	DBLP DOI BibTeX RDF
16	Yong Zhao, Hans G. Kerkhoff	Application of functional IDDQ testing in a VLIW processor towards detection of aging degradation.	DTIS	2015	DBLP DOI BibTeX RDF
16	Renan Augusto Starke, Andreu Carminati, Rômulo Silva de Oliveira	Investigating a four-issue deterministic VLIW architecture for real-time systems.	INDIN	2015	DBLP DOI BibTeX RDF
16	Samuel J. Parker	An automated OpenCL FPGA compilation framework targeting a configurable, VLIW chip multiprocessor.		2015	RDF
16	Yuanwu Lei, Lei Guo 0029, Yong Dou, Sheng Ma, Jinbo Xu	FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function.	ACM Trans. Reconfigurable Technol. Syst.	2014	DBLP DOI BibTeX RDF
16	Cheng-Yu Lee, Min-Chin Hung, Rong-Guey Chang	Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture.	Concurr. Comput. Pract. Exp.	2014	DBLP DOI BibTeX RDF
16	Davide Sabena, Matteo Sonza Reorda, Luca Sterpone	On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	Shan Cao, Zhaolin Li, Fang Wang, Shaojun Wei	Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW Scheduling.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	Yazhi Huang, Liang Shi, Jianhua Li 0003, Qing'an Li, Chun Jason Xue	WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
16	Ittetsu Taniguchi, Kohei Aoki, Hiroyuki Tomiyama, Praveen Raghavan, Francky Catthoor, Masahiro Fukui	Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2014	DBLP DOI BibTeX RDF
16	Vincent Brost, Fan Yang 0019, Charles Meunier	Flexible VLIW processor based on FPGA for efficient embedded real-time image processing.	J. Real Time Image Process.	2014	DBLP DOI BibTeX RDF
16	Xu Yang 0003	Path-Dividing Based Scheduling Algorithm for Reducing Energy Consumption of Clustered VLIW Architectures.	IEEE Trans. Computers	2014	DBLP DOI BibTeX RDF
16	Erkan Diken, Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal, Felipe Augusto Chies	Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
16	Zhibin Liang, Wei Zhang 0055, Yung-Cheng Ma	Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files.	ACM Trans. Archit. Code Optim.	2014	DBLP DOI BibTeX RDF
16	Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda	Shared-port register file architecture for low-energy VLIW processors.	ACM Trans. Archit. Code Optim.	2014	DBLP DOI BibTeX RDF
16	Jinyong Lee, Jongwon Lee, Jongeun Lee, Yunheung Paek	Improving performance of loops on DIAM-based VLIW architectures.	LCTES	2014	DBLP DOI BibTeX RDF
16	Mounir Bahtat, Said Belkouch, Philippe Elleaume, Phillipe Le Gall	Fast enumeration-based modulo scheduling heuristic for VLIW architectures.	ICM	2014	DBLP DOI BibTeX RDF
16	Davide Sabena, Matteo Sonza Reorda, Luca Sterpone	Soft error effects analysis and mitigation in VLIW safety-critical applications.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
16	Xuemeng Zhang, Hui Wu 0001, Haiyan Sun, Jingling Xue	Lifetime holes aware register allocation for clustered VLIW processors.	DATE	2014	DBLP DOI BibTeX RDF
16	Oliver Stecklina, Michael Methfessel	A Tiny Scale VLIW Processor for Real-Time Constrained Embedded Control Tasks.	DSD	2014	DBLP DOI BibTeX RDF
16	Miguel Tairum Cruz, Pedro Tomás, Nuno Roma	Low-power vectorial VLIW architecture for maximum parallelism exploitation of dynamic programming algorithms.	HPCS	2014	DBLP DOI BibTeX RDF
16	Yangzhao Yang, Naijie Gu, Kaixin Ren, Bingqing Hu	An Approach to Enhance Loop Performance for Multicluster VLIW DSP Processor.	ARCS Workshops	2014	DBLP BibTeX RDF
16	Mona Aghababaeetafreshi, Lasse Lehtonen, Toni Levanen, Mikko Valkama, Jarmo Takala	IEEE 802.11ac MIMO receiver baseband processing on customized VLIW processor.	SiPS	2014	DBLP DOI BibTeX RDF
16	Julian Hartig, Lukas Gerlach 0001, Guillermo Payá Vayá, Holger Blume	Customizing a VLIW-SIMD application-specific instruction-set processor for hearing aid devices.	SiPS	2014	DBLP DOI BibTeX RDF
16	Mona Aghababaeetafreshi, Lasse Lehtonen, Maliheh Soleimani, Mikko Valkama, Jarmo Takala	IEEE 802.11AC MIMO transmitter baseband processing on customized VLIW processor.	ICASSP	2014	DBLP DOI BibTeX RDF
16	Martti Forsell, Jussi Roivainen	REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor.	ACSSC	2014	DBLP DOI BibTeX RDF
16	Roel Jordans, Lech Józwiak, Henk Corporaal	Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm.	MECO	2014	DBLP DOI BibTeX RDF
16	Erkan Diken, Roel Jordans, Lech Józwiak, Henk Corporaal	Construction and exploitation of VLIW asips with multiple vector-widths.	MECO	2014	DBLP DOI BibTeX RDF
16	Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack	27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking.	ISSCC	2014	DBLP DOI BibTeX RDF
16	Boris Hübener, Gregor Sievers, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert 0001	CoreVA: A Configurable Resource-Efficient VLIW Processor Architecture.	EUC	2014	DBLP DOI BibTeX RDF
16	Davide Patti, Maurizio Palesi, Vincenzo Catania	Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems.	CSOC	2014	DBLP DOI BibTeX RDF
16	Taisong Jin, Minwook Ahn, Donghoon Yoo, Dongkwan Suh, Yoonseo Choi, Do Hyung Kim 0002, Shihwa Lee	Nop compression scheme for high speed DSPs based on VLIW architecture.	ICCE	2014	DBLP DOI BibTeX RDF
16	Venkata Ganapathi Puppala	A VLIW-Vector co-processor design for accelerating Basic Linear Algebraic Operations in OpenCV.	VDAT	2014	DBLP DOI BibTeX RDF
16	Christoph W. Kessler	Compiling for VLIW DSPs.	Handbook of Signal Processing Systems	2013	DBLP DOI BibTeX RDF
16	Xuemeng Zhang, Hui Wu 0001, Jingling Xue	Instruction scheduling with k-successor tree for clustered VLIW processors.	Des. Autom. Embed. Syst.	2013	DBLP DOI BibTeX RDF
16	Jongwon Lee, Yohan Ko, Kyoungwoo Lee, Jonghee M. Youn, Yunheung Paek	Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures.	ACM Trans. Archit. Code Optim.	2013	DBLP DOI BibTeX RDF
16	Yuanwu Lei, Yong Dou, Lei Guo 0029, Jinbo Xu, Jie Zhou 0007, Yazhuo Dong, Hongjian Li	VLIW coprocessor for IEEE-754 quadruple-precision elementary functions.	ACM Trans. Archit. Code Optim.	2013	DBLP DOI BibTeX RDF
16	Jongwon Lee, Jonghee M. Youn, Doosan Cho, Yunheung Paek	Reducing instruction bit-width for low-power VLIW architectures.	ACM Trans. Design Autom. Electr. Syst.	2013	DBLP DOI BibTeX RDF
16	Petr Pfeifer, Zdenek Plíva, Mario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus	On performance estimation of a scalable VLIW soft-core in XILINX FPGAs.	DDECS	2013	DBLP DOI BibTeX RDF
16	Davide Sabena, Matteo Sonza Reorda, Luca Sterpone	Partition-Based Faults Diagnosis of a VLIW Processor.	VLSI-SoC (Selected Papers)	2013	DBLP DOI BibTeX RDF
16	Davide Sabena, Matteo Sonza Reorda, Luca Sterpone	On the development of diagnostic test programs for VLIW processors.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
16	Amir Hossein Ashouri, Vittorio Zaccaria, Sotirios Xydis, Gianluca Palermo, Cristina Silvano	A framework for Compiler Level statistical analysis over customized VLIW architecture.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
16	Anthony Brandon, Stephan Wong	Support for dynamic issue width in VLIW processors using generic binaries.	DATE	2013	DBLP DOI BibTeX RDF
16	Mian Muhammad Hamayun, Frédéric Pétrot, Nicolas Fournel	Native simulation of complex VLIW instruction sets using static binary translation and Hardware-Assisted Virtualization.	ASP-DAC	2013	DBLP DOI BibTeX RDF
16	Gregor Sievers, Peter Christ, Julian Einhaus, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert 0001	Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications.	NORCHIP	2013	DBLP DOI BibTeX RDF
16	Kalin Ovtcharov, Ilian Tili, J. Gregory Steffan	TILT: A multithreaded VLIW soft processor family.	FPL	2013	DBLP DOI BibTeX RDF
16	Kalin Ovtcharov, Ilian Tili, J. Gregory Steffan	A Multithreaded VLIW Soft Processor Family.	FCCM	2013	DBLP DOI BibTeX RDF
16	Fakhar Anjam, Stephan Wong	Configurable Fault-Tolerance for a Configurable VLIW Processor.	ARC	2013	DBLP DOI BibTeX RDF
16	Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal	Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs.	MECO	2013	DBLP DOI BibTeX RDF