Search results for "bit-serial"

Found 418 publication records. Showing 418 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Feng Zhou, Peter Kornerup	Computing Moments by Prefix Sums.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
9	Marc Bright, Brian Turton	An Efficient Random Number Generation Architecture for Hardware Parallel Genetic Algorithms.	PPSN	2000	DBLP DOI BibTeX RDF
9	Takashi Komuro, Idaku Ishii, Masatoshi Ishikawa, Atsushi Yoshida	High Speed Target Tracking Vision Chip.	CAMP	2000	DBLP DOI BibTeX RDF	vision chip, chip architecture, high speed target tracking, target tracking, target tracking
9	Tom Chen 0001, Glen Sunada, Jain Jin	COBRA: a 100-MOPS single-chip programmable and expandable FFT.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
9	Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu 0002	An area-efficient versatile Reed-Solomon decoder for ADSL.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
9	Kibum Suh, Kyung Yuk Min, Kyeounsoo Kim, Jong-Seog Koh, Jong-Wha Chong	A design of DPCM hybrid coding loop using single 1-D DCT in MPEG-2 video encoder.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
9	Manoucher Shaditalab, Guy Bois, Mohamad Sawan	Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks.	FCCM	1998	DBLP DOI BibTeX RDF
9	Philippe Thissen, Michel Verleysen, Jean-Didier Legat	An Associative Processor Dedicated to Classification by Neural Methods.	IWANN	1995	DBLP DOI BibTeX RDF
9	Mattias Johannesson	FFTs on a Linear SIMD Arrat.	Euro-Par	1995	DBLP DOI BibTeX RDF
9	V. Hecht, Karsten Rönner, Peter Pirsch	A defect-tolerant systolic array implementation for real time image processing.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
9	Tom Chen 0001, Li Zhu	An expandable column fft architecture using circuit switching networks.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
9	Gordon J. Brebner	Configurable array logic circuits for computing network error detection codes.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
9	Juin-Yeu Lu, Shiu-Kai Chin	Linking HOL to a VLSI CAD System.	HUG	1993	DBLP DOI BibTeX RDF
9	Sanjeev Arora, Frank Thomson Leighton, Bruce M. Maggs	On-line Algorithms for Path Selection in a Nonblocking Network (Extended Abstract)	STOC	1990	DBLP DOI BibTeX RDF
9	Ted H. Szymanski, Chien Fang	Design and analysis of buffered crossbars and banyans with cut-through switching.	SC	1990	DBLP DOI BibTeX RDF
9	Richard I. Hartley, Peter F. Corbett	A Digit-Serial Silicon Compiler.	DAC	1988	DBLP BibTeX RDF
9	Won Kim 0001, Daniel Gajski, David J. Kuck	A Parallel Pipelined Relational Query Processor.	ACM Trans. Database Syst.	1984	DBLP DOI BibTeX RDF
9	Bernhard Quatember	Modular crossbar switch for large-scale multiprocessor systems: structure and implementation.	AFIPS National Computer Conference	1981	DBLP DOI BibTeX RDF

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