Search results for "latches"

Found 414 publication records. Showing 414 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel	Exact calculation of synchronizing sequences based on binary decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
11	Ted E. Williams	Performance of iterative computation in self-timed rings.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
11	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential test generation and synthesis for testability at the register-transfer and logic levels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson	Synchronization of pipelines.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang	An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
11	Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal	The optimistic update theorem for path delay testing in sequential circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	test generation, Fault simulation, timing analysis, path delay faults
11	Hosahalli R. Srinivas, Keshab K. Parhi	High-speed VLSI arithmetic processor architectures using hybrid number representation.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
11	Karen A. Bartlett, Gaetano Borriello, Sitaram Raju	Timing optimization of multiphase sequential logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
11	Sunggu Lee, Kang G. Shin	Design for test using partial parallel scan.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
11	Nicholas Weiner, Alberto L. Sangiovanni-Vincentelli	Timing Analysis in a Logic Synthesis Environment.	DAC	1989	DBLP DOI BibTeX RDF
11	Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton	On the verification of sequential machines at differing levels of abstraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
11	David E. Wallace, Carlo H. Séquin	ATV: An Abstract Timing Verifier.	DAC	1988	DBLP BibTeX RDF
11	Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou	BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping.	DAC	1988	DBLP BibTeX RDF
11	Bill Huston	Practical CMOS microprocessor systems.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF

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