Search results for "layout"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Ming C. Hao, Umeshwar Dayal, Daniel A. Keim, Tobias Schreck	Importance-Driven Visualization Layouts for Large Time Series Data.	INFOVIS	2005	DBLP DOI BibTeX RDF	Space-Filling Layout Generation, Information Visualization, Time Series
23	Victor De La Luz, Mahmut T. Kandemir	Array Regrouping and Its Use in Compiling Data-Intensive Embedded Applications.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Array regrouping, memory energy consumption, embedded systems, cache locality, layout optimizations
23	Hiroshi Hosobe	A high-dimensional approach to interactive graph visualization.	SAC	2004	DBLP DOI BibTeX RDF	general undirected graphs, interactive graph layout, information visualization, multidimensional scaling
23	Yaniv Frishman, Ayellet Tal	Dynamic Drawing of Clustered Graphs.	INFOVIS	2004	DBLP DOI BibTeX RDF	dynamic layout, software visualization, graph drawing, mobile objects
23	Ricardo Reis 0001, Fernanda Lima Kastensmidt, José Luís Almada Güntzel	Physical design methodologies for performance predictability and manufacturability.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	design methodologies, regularity, layout, physical design, DFM
23	Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley	A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.	DAC	2004	DBLP DOI BibTeX RDF	modeling, synthesis, layout, sizing, parasitic, radio frequency
23	Xiaoyu Song, Yuke Wang	On the crossing distribution problem.	ACM Trans. Design Autom. Electr. Syst.	1999	DBLP DOI BibTeX RDF	VLSI layout, crossings
23	Krishna Bharat, Tomonari Kamba, Michael C. Albers	Personalized, Interactive News on the Web.	Multim. Syst.	1998	DBLP DOI BibTeX RDF	On-line newspapers, Community interest, Personalization, Relevance feedback, Customization, Automatic layout
23	Desmond Kirkpatrick, Alberto L. Sangiovanni-Vincentelli	Digital sensitivity: predicting signal interaction using functional analysis.	ICCAD	1996	DBLP DOI BibTeX RDF	layout synthesis, Crosstalk, sensitivity, signal integrity
23	Zhan Chen, Israel Koren	Techniques for Yield Enhancement of VLSI Adders.	ASAP	1995	DBLP DOI BibTeX RDF	VLSI yield, VLSI adder, defect tolerance, VLSI layout
22	Sanjiv Taneja	DFT Aware Layout - Layout Aware DFT.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
22	Chi-Hsiang Yeh, Behrooz Parhami, Emmanouel A. Varvarigos	The Recursive Grid Layout Scheme for VLSI Layout of Hierarchical Networks.	IPPS/SPDP	1999	DBLP DOI BibTeX RDF
22	Dong-Sung Ryu, Woo-Keun Chung, Hwan-Gue Cho	PHOTOLAND: a new image layout system using spatio-temporal information in digital photos.	SAC	2010	DBLP DOI BibTeX RDF	photo management, clustering, visualization, digital photo, EXIF, photo clustering
22	Xiaowen Chu 0001, Kai Ouyang, Xiaolei Chang	FAXtrac: Fast Extraction of Disk Layout.	NAS	2009	DBLP DOI BibTeX RDF
22	Mi Li, Yangyang Song, Shengfu Lu, Ning Zhong 0001	The Layout of Web Pages: A Study on the Relation between Information Forms and Locations Using Eye-Tracking.	AMT	2009	DBLP DOI BibTeX RDF
22	Albert Gordo, Ernest Valveny	A Rotation Invariant Page Layout Descriptor for Document Classification and Retrieval.	ICDAR	2009	DBLP DOI BibTeX RDF
22	Raymond W. Smith	Hybrid Page Layout Analysis via Tab-Stop Detection.	ICDAR	2009	DBLP DOI BibTeX RDF
22	Stefano Ferilli, Marenglen Biba, Floriana Esposito, Teresa Maria Altomare Basile	A Distance-Based Technique for Non-Manhattan Layout Analysis.	ICDAR	2009	DBLP DOI BibTeX RDF
22	Michael R. Fellows, Daniel Lokshtanov, Neeldhara Misra, Frances A. Rosamond, Saket Saurabh 0001	Graph Layout Problems Parameterized by Vertex Cover.	ISAAC	2008	DBLP DOI BibTeX RDF
22	Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao	Design rule optimization of regular layout for leakage reduction in nanoscale design.	ASP-DAC	2008	DBLP DOI BibTeX RDF
22	Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal	Stress aware layout optimization.	ISPD	2008	DBLP DOI BibTeX RDF
22	Mathys C. du Plessis, Lynette Barnard	Incorporating layout managers into an evolutionary programming algorithm to design graphical user interfaces.	SAICSIT	2008	DBLP DOI BibTeX RDF	genetic algorithms, human computer interaction (HCI), evolutionary programming
22	Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen	Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Angelo Di Iorio, Luca Furini, Fabio Vitali, John William Lumley, Tony Wiley	Higher-level layout through topological abstraction.	ACM Symposium on Document Engineering	2008	DBLP DOI BibTeX RDF	DDF, TALL, topological layouts, XSLT, automatic layouts
22	Istvan Beszteri, Petri Vuorimaa	Vertical Navigation of Layout Adapted Web Documents.	World Wide Web	2007	DBLP DOI BibTeX RDF	internet, adaptation, navigation, browsing
22	Michael Baur, Ulrik Brandes	Multi-circular Layout of Micro/Macro Graphs.	GD	2007	DBLP DOI BibTeX RDF
22	Ian Vollick, Daniel Vogel 0001, Maneesh Agrawala, Aaron Hertzmann	Specifying label layout style by example.	UIST	2007	DBLP DOI BibTeX RDF	design, learning, workflows, labeling
22	Ye Chen, Zheng Shi 0002, Xiaolang Yan	An Automated and Fast OPC Algorithm for OPC-Aware Layout Design.	ISQED	2007	DBLP DOI BibTeX RDF
22	Vyas Krishnan, Srinivas Katkoori	A 3D-Layout Aware Binding Algorithm for High-Level Synthesis of Three-Dimensional Integrated Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
22	Ming Hu, Minghua Jiang	FRAID: A Networked Data Storage Layout.	IITA	2007	DBLP DOI BibTeX RDF
22	Claudio Andreatta	Document Layout Substructure Discovery.	SAMT	2007	DBLP DOI BibTeX RDF
22	Sriram Krishnamoorthy, Gerald Baumgartner, Chi-Chung Lam, Jarek Nieplocha, P. Sadayappan	Layout transformation support for the disk resident arrays framework.	J. Supercomput.	2006	DBLP DOI BibTeX RDF
22	Nian Zhang, Donald C. Wunsch II	Speeding up VLSI Layout Verification Using Fuzzy Attributed Graphs Approach.	IEEE Trans. Fuzzy Syst.	2006	DBLP DOI BibTeX RDF
22	David Liu 0001, Datong Chen, Tsuhan Chen	Unsupervised Image Layout Extraction.	ICIP	2006	DBLP DOI BibTeX RDF
22	Minghong Zhou, Rubao Li, Wei Li	Understanding theWeb Page Layout.	ICDM Workshops	2006	DBLP DOI BibTeX RDF
22	Peter Sobe	Adaptations of Block Layout in Distributed Storage Systems.	PDP	2006	DBLP DOI BibTeX RDF
22	Robert Hundt, Sandya Mannarswamy, Dhruva R. Chakrabarti	Practical Structure Layout Optimization and Advice.	CGO	2006	DBLP DOI BibTeX RDF
22	Xinyong Zhang, Xiangshi Ren	CATER: A Framework for the Automated Layout of Transactional Pages.	CIT	2006	DBLP DOI BibTeX RDF
22	Shogo Tokai, Hiroyuki Hase	Attention Navigation by Keeping Screen Layout for Switching Multiple Views.	ICPR (4)	2006	DBLP DOI BibTeX RDF
22	Gengui Zhou, Mujing Ye, Zhenyu Cao, Feng Ye	A Genetic Algorithm Approach on a Facility Layout Design Problem with Aisles.	ICIC (2)	2006	DBLP DOI BibTeX RDF
22	Helen C. Purchase, Eve E. Hoggan, Carsten Görg	How Important Is the "Mental Map"? - An Empirical Investigation of a Dynamic Graph Layout Algorithm.	GD	2006	DBLP DOI BibTeX RDF
22	John M. Winn, Jamie Shotton	The Layout Consistent Random Field for Recognizing and Segmenting Partially Occluded Objects.	CVPR (1)	2006	DBLP DOI BibTeX RDF
22	Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel	Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study.	IOLTS	2006	DBLP DOI BibTeX RDF
22	Muzaffer Kapanoglu, Fehime Utkan	Particle Swarm Optimization for Facility Layout Problems With/Out Department-Specific Restrictions.	ANTS Workshop	2006	DBLP DOI BibTeX RDF
22	Gaurav Gupta, Shobhit Niranjan, Ankit Shrivastava, R. Mahesh K. Sinha	Document Layout Analysis and Classification and Its Application in OCR.	EDOC Workshops	2006	DBLP DOI BibTeX RDF
22	Bikram Baidya, Tamal Mukherjee	Layout verification for mixed-domain integrated MEMS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
22	Puneet Gupta 0001, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma	Layout-aware scan chain synthesis for improved path delay fault coverage.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
22	Shintaro Kajiwara, Hideki Koike, Kentaro Fukuchi, Kenji Oka, Yoichi Sato	Information Layout and Interaction Techniques on an Augmented Round Table.	ICCV-HCI	2005	DBLP DOI BibTeX RDF
22	Wei Zhang 0012, Niraj K. Jha	ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology.	ICCD	2005	DBLP DOI BibTeX RDF
22	Anuradha Agarwal, Ranga Vemuri	Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners.	ICCD	2005	DBLP DOI BibTeX RDF
22	Paula López 0001, Matthias Oberst, Harald Neubauer, Johann Hauer, Diego Cabello	Performance analysis of high-speed MOS transistors with different layout styles.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
22	Yong-Chan Ban, Soo-Han Choi, Ki-Hung Lee, Dong-Hyun Kim, Jisuk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong	A Fast Lithography Verification Framework for Litho-Friendly Layout Design.	ISQED	2005	DBLP DOI BibTeX RDF
22	Kensuke Kawai, Shigeru Matsumoto, Mitsunobu Nakajo, Hirotaka Nakayama, Masao Arakawa	Shinayaka-Systems Design: A Multi-objective Plant-layout Planning for Power Generating Plants.	WSTST	2005	DBLP DOI BibTeX RDF
22	Simone Marinai, Emanuele Marino, Giovanni Soda	Layout based document image retrieval by means of XY tree reduction.	ICDAR	2005	DBLP DOI BibTeX RDF
22	Yusuke Takiguchi, Minoru Okada, Yasuji Miyake	A Fundamental Study of Output Translation from Layout Recognition and Semantic Understanding System for Mathematical Formulae.	ICDAR	2005	DBLP DOI BibTeX RDF
22	Hui Chao, Xiaofan Lin	Capturing the Layout of Electronic Documents for Reuse in Variable Data Printing.	ICDAR	2005	DBLP DOI BibTeX RDF
22	Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis 0001	A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool.	PATMOS	2004	DBLP DOI BibTeX RDF
22	Byoungro So, Mary W. Hall, Heidi E. Ziegler	Custom Data Layout for Memory Parallelism.	CGO	2004	DBLP DOI BibTeX RDF
22	Noriyuki Miura, Naoki Kato, Tadahiro Kuroda	Practical methodology of post-layout gate sizing for 15% more power saving.	ASP-DAC	2004	DBLP DOI BibTeX RDF
22	Valdair Candido Martins, Marco Antônio Barbosa Cândido, Leandro dos Santos Coelho	Solving Facility Layout Problems with a Set of Geometric Hard-constraints using Tabu Search.	WSC	2004	DBLP DOI BibTeX RDF
22	Guofu Ding, Kaiyin Yan, Yong He, Dan Li	Layout of Virtual Flexible Manufacturing System and Machining Simulation.	AsiaSim	2004	DBLP DOI BibTeX RDF
22	Ugur Dogrusöz, Erhan Giral, Ahmet Cetintas, Ali Civril, Emek Demir	A Compound Graph Layout Algorithm for Biological Pathways.	GD	2004	DBLP DOI BibTeX RDF
22	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Post-layout leakage power minimization based on distributed sleep transistor insertion.	ISLPED	2004	DBLP DOI BibTeX RDF	sub-threshold current, leakage power, sleep transistor
22	Fang Fang, Jianwen Zhu	Calligrapher: A New Layout Migration Engine Based on Geometric Closeness.	ISQED	2004	DBLP DOI BibTeX RDF
22	Anat Bremler-Barr, Leah Epstein	Path Layout on Tree Networks: Bounds in Different Label Switching Models.	SIROCCO	2004	DBLP DOI BibTeX RDF
22	Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay	Fast and flexible buffer trees that navigate the physical layout environment.	DAC	2004	DBLP DOI BibTeX RDF	global routing, buffer insertion, physical synthesis
22	Qinghua Liu, Malgorzata Marek-Sadowska	Pre-layout wire length and congestion estimation.	DAC	2004	DBLP DOI BibTeX RDF	prediction, congestion, wire length
22	Alessandro Girardi, Sergio Bampi	LIT - An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks.	DATE	2003	DBLP DOI BibTeX RDF
22	Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis 0001, José Luís Almada Güntzel	A Transistor Sizing Method Applied to an Automatic Layout Generation Tool.	SBCCI	2003	DBLP DOI BibTeX RDF
22	Yoav Zibin, Joseph Gil	Two-Dimensional Bi-directional Object Layout.	ECOOP	2003	DBLP DOI BibTeX RDF
22	Alexandre Casacurta, Marcel Furtado Almeida, Ricardo Augusto da Luz Reis	A Visual Simulation Tool at Layout Level.	MSE	2003	DBLP DOI BibTeX RDF
22	Burkay Genç, Ugur Dogrusöz	A Constrained, Force-Directed Layout Algorithm for Biological Pathways.	GD	2003	DBLP DOI BibTeX RDF
22	Jeyarajan Thiyagalingam, Olav Beckmann, Paul H. J. Kelly	Improving the Performance of Morton Layout by Array Alignment and Loop Unrolling: Reducing the Price of Naivety.	LCPC	2003	DBLP DOI BibTeX RDF
22	Li Xiao, Oleg Shats, Simon Sherman	Grid-Layout Visualization Method in the Microarray Data Analysis Interactive Graphics Toolkit.	HICSS	2003	DBLP DOI BibTeX RDF
22	Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang	Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC.	ISQED	2003	DBLP DOI BibTeX RDF
22	T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar	Optimal Code and Data Layout in Embedded Systems.	VLSI Design	2003	DBLP DOI BibTeX RDF
22	Istvan Beszteri, Petri Vuorimaa	Automatic Layout Generation with XML Wrapping.	APWeb	2003	DBLP DOI BibTeX RDF
22	Rung-Bin Lin	Comments on "Filling algorithms and analyses for layout density control".	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
22	Ke-Bing Zhang, Kang Zhang 0001, Mehmet A. Orgun	Grammar-Based Layout for a Visual Programming Language Generation System.	Diagrams	2002	DBLP DOI BibTeX RDF
22	Roxana Diaconescu	A General Data Layout for Distributed Consistency in Data Parallel Applications.	HiPC	2002	DBLP DOI BibTeX RDF
22	Michael A. Bender, Erik D. Demaine, Martin Farach-Colton	Efficient Tree Layout in a Multilevel Memory Hierarchy.	ESA	2002	DBLP DOI BibTeX RDF
22	Jeyarajan Thiyagalingam, Paul H. J. Kelly	Is Morton Layout Competitive for Large Two-Dimensional Arrays?	Euro-Par	2002	DBLP DOI BibTeX RDF
22	Junhyung Um, Jae-Hoon Kim 0001, Taewhan Kim	Layout-driven resource sharing in high-level synthesis.	ICCAD	2002	DBLP DOI BibTeX RDF
22	Richard Cole 0002	Automated Layout of Concept Lattices Using Layered Diagrams and Additive Diagrams.	ACSC	2001	DBLP DOI BibTeX RDF
22	Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez	A Compact Layout Technique for Reducing Switching Current Effects in High Speed Circuits.	ISQED	2001	DBLP DOI BibTeX RDF
22	Rym M'Hallah, Ahlem Bouziri, Walid Jilani	Layout of Two Dimensional Irregular Shapes Using Genetic Algorithms.	IEA/AIE	2001	DBLP DOI BibTeX RDF
22	Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil D. Dutt	Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique.	VLSI Design	2001	DBLP DOI BibTeX RDF
22	Fei Liu 0017, Yupin Luo, Dongcheng Hu, Masataka Yoshikawa	A New Component Based Algorithm for Newspaper Layout Analysis.	ICDAR	2001	DBLP DOI BibTeX RDF
22	Alan Borning, Richard Kuang-Hsu Lin, Kim Marriott	Constraint-based document layout for the Web.	Multim. Syst.	2000	DBLP DOI BibTeX RDF
22	Gerard A. Allan	Yield prediction by sampling IC layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
22	Zhiwei Guan, Yang Li, Hongan Wang, Guozhong Dai	A Comparison on Free Interaction Models for Mobile Layout System.	HUC	2000	DBLP DOI BibTeX RDF
22	Phillip E. Mitchell, Hong Yan 0001	Document Page Segmentation and Layout Analysis Using Soft Ordering.	ICPR	2000	DBLP DOI BibTeX RDF
22	Toyohide Watanabe, Tsuneo Sobue	Layout Analysis of Complex Documents.	ICPR	2000	DBLP DOI BibTeX RDF
22	Richard Cole 0002	Automated Layout of Concept Lattices Using Force Directed Placement and Genetic Algorithms.	ACSC	2000	DBLP DOI BibTeX RDF
22	Christoph Schlieder, Cornelius Hagen	Interactive Layout Generation with a Diagrammatic Constraint Language.	Spatial Cognition	2000	DBLP DOI BibTeX RDF
22	Tatiana Surazhsky, Gershon Elber	Arbitrary Precise Orientation Specification for Layout of Text.	PG	2000	DBLP DOI BibTeX RDF	free-form parametric curves and surfaces, Composition, digital typography
22	Chi-Hsiang Yeh, Emmanouel A. Varvarigos, Behrooz Parhami	Multilayer VLSI Layout for Interconnection Networks.	ICPP	2000	DBLP DOI BibTeX RDF
22	Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja	The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
22	Peter F. Sweeney, Joseph Gil	Space and Time-Efficient Memory Layout for Multiple Inheritance.	OOPSLA	1999	DBLP DOI BibTeX RDF	C++
22	Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky	New Multilevel and Hierarchical Algorithms for Layout Density Control.	ASP-DAC	1999	DBLP DOI BibTeX RDF