Search results for "slew"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Kenneth L. Shepard, Zhong Tian	Return-limited inductances: a practical approach to on-chipinductance extraction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
12	Tong Xiao, Malgorzata Marek-Sadowska	Worst Delay Estimation in Crosstalk Aware Static Timing Analysis.	ICCD	2000	DBLP DOI BibTeX RDF
12	J. L. Knighten, N. W. Smith, L. O. Hoeft, J. T. DiBene II	EMI Common-Mode Current Dependence on Delay Skew Imbalance in High Speed Differential Transmission Lines Operating at 1 Gigabit/second Data Rates.	ISQED	2000	DBLP DOI BibTeX RDF	radiated emissions, common-mode current, differential transmission line, skew, EMI
12	Rong Lin, Stephan Olariu, James L. Schwing, Biing-Feng Wang	The Mesh with Hybrid Buses: An Efficient Parallel Architecture for Digital Geometry.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	mesh with hybrid buses, cost-optimal algorithms, pattern recognition, image processing, broadcasting, VLSI architectures, digital geometry, cellular systems
12	Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu 0001	Logic Transformation for Low Power Synthesis.	DATE	1999	DBLP DOI BibTeX RDF
12	Ka Nang Leung, Philip K. T. Mok, Wing-Hung Ki	Optimum nested Miller compensation for low-voltage low-power CMOS amplifier design.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
12	Simona Brigati, Fabrizio Francesconi, Piero Malcovati, Davide Tonietto, Andrea Baschirotto, Franco Maloberti	Modeling sigma-delta modulator non-idealities in SIMULINK(R).	ISCAS (2)	1999	DBLP DOI BibTeX RDF
12	Hassan O. Elwan, Weinan Gao, Roberto Sadkowski, Mohammed Ismail 0001	A low voltage CMOS class AB operational transconductance amplifier.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
12	Iyad Rayane, Jaime Velasco-Medina, Michael Nicolaidis	A Digital BIST for Operational Amplifiers Embedded in Mixed-Signal Circuits.	VTS	1999	DBLP DOI BibTeX RDF
12	Andrew B. Kahng, Sudhakar Muddu	Improved Effective Capacitance Computations for Use in Logic and Layout Optimization.	VLSI Design	1999	DBLP DOI BibTeX RDF
12	Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim	Interleaving buffer insertion and transistor sizing into a single optimization.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
12	Tatsuya Hayashi, Koji Nakano, Stephan Olariu	An O((log log n)2) Time Algorithm to Compute the Convex Hull of Sorted Points on Reconfigurable Meshes.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	pattern recognition, mobile computing, image processing, Convex hulls, morphology, reconfigurable meshes
12	Saeid Sadeghi-Emamchaie, Graham A. Jullien, Vassil S. Dimitrov, William C. Miller	Digital Arithmetic Using Analog Arrays.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Cellular Neural Networks, Double-Base Number System, Analog VLSI
12	John Lillis, Premal Buch	Table-Lookup Methods for Improved Performance-Driven Routing.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
12	Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu	Circuit optimization via adjoint Lagrangians.	ICCAD	1997	DBLP DOI BibTeX RDF	Adjoint circuit, Optimization, Circuit simulation, Trust region, Augmented Lagrangian, Circuit tuning
12	Pradip Mandal, V. Visvanathan	A Self-Biased High Performance Folded Cascode CMOS Op-Amp.	VLSI Design	1997	DBLP DOI BibTeX RDF
12	Tatsuya Hayashi, Koji Nakano, Stephan Olariu	Efficient List Ranking on the Reconfigurable Mesh, with Applications.	ISAAC	1996	DBLP DOI BibTeX RDF
12	Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou	A power modeling and characterization method for the CMOS standard cell library.	ICCAD	1996	DBLP DOI BibTeX RDF	power characterization, power consumption, power estimation
12	Daksh Lehther, Sachin S. Sapatnekar	Clock tree synthesis for multi-chip modules.	ICCAD	1996	DBLP DOI BibTeX RDF	Pade' approximants, Interconnect optimization
12	Sudhir Aggarwal	An Enhanced Macromodel for a CMOS Operational Amplifier for HDL Implementation.	VLSI Design	1996	DBLP DOI BibTeX RDF	VHDL-Analog, Non-linear model, Analog IC's, Operational Amplifier, Macromodel
12	Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj	Switch-level timing simulation of bipolar ECL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF