Search results for "switch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Benjamin J. Ewy, Joseph B. Evans, Victor Frost, Gary J. Minden	TCP/ATM Experiences in the MAGIC Testbed.	HPDC	1995	DBLP DOI BibTeX RDF	TCP/ATM, MAGIC testbed, cell level pacing, bandwidth capacity, high performance distributed systems, traffic management infrastructureThe limited applicability of block decomposition in cluster computing - Crandall, P.E. Dept. of Comput, Sci. & Eng., Connecticut Univ., Storrs, USA This Paper Appears in : High Performance Distributed Computing, 1995., Proceedings of the Fourth IEEE International Symposium on on Pages: 102 - 109 This Conference was Held : 2-4 Aug. 1995 1995 ISBN: 0-8186-7088-6 IEEE Catalog Number: 95TB8075 Total Pages: xiv+246 Refer, Mathematical characterizations of the communication costs for contiguous partitioning and block decomposition in both a ring-connected and switched network are presented, Simulations of ring and switch technologies indicate that as network speeds increase and as the effects of message-preparation latency dominate, the advantages claimed for block decomposition diminish, Subject Terms: FDDI, block decomposition, high-speed switch technology, mathematical characterizations, contiguous partitioning, ring-connected networks, simulations, performance evaluation, performance evaluation, performance, asynchronous transfer mode, congestion control, cluster computing, local area networks, transport protocols, performance measurements, wide area networks, CT, switched network, FDDI, congestion avoidance, token networks
21	I-Hsuan Shen, Kong-King Shieh	Effects of Report Order on Identification on Multidimensional Stimulus: Color and Shape.	HCI (17)	2009	DBLP DOI BibTeX RDF	report order, multidimensional stimulus identification, task switch, color coding
21	Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar	Complementary nano-electromechanical switches for ultra-low power embedded processors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	nems, cmos, switch, device, ultra-low power
21	Nick McKeown, Thomas E. Anderson, Hari Balakrishnan, Guru M. Parulkar, Larry L. Peterson, Jennifer Rexford, Scott Shenker, Jonathan S. Turner	OpenFlow: enabling innovation in campus networks.	Comput. Commun. Rev.	2008	DBLP DOI BibTeX RDF	ethernet switch, flow-based, virtualization
21	Jeongmin Park, Joonhoon Lee, Eunseok Lee 0001	Goal graph based performance improvement for self-adaptive modules.	ICUIMC	2008	DBLP DOI BibTeX RDF	activation switch, goal graph, self-adaptive module
21	I-Hsuan Shen, Kong-King Shieh, Shin-Yuan Tsai	Event-Related Potential as a Measure of Effects of Report Order and Compatibility on Identification on Multidimensional Stimulus.	HCI (13)	2007	DBLP DOI BibTeX RDF	report order, multidimensional stimulus identification, task switch, event-related potential
21	Anand Ramalingam, Giri Devarayanadurg, David Z. Pan	Accurate power grid analysis with behavioral transistor network modeling.	ISPD	2007	DBLP DOI BibTeX RDF	RC model of transistor, behavioral modeling of switch, power grid
21	Nianmin Yao, Xiuli Zhao, Huimin Meng, Xinlei Jiang	Optimization of the Switches in Storage Networks.	International Conference on Computational Science (3)	2007	DBLP DOI BibTeX RDF	performance, network, switch, SAN
21	Yossi Azar, Yossi Richter	Management of Multi-Queue Switches in QoS Networks.	Algorithmica	2005	DBLP DOI BibTeX RDF	Multi-queue switch, Quality of Service, Packet switching, Buffer management, Competitiveness, On-line algorithms, Competitive ratio
21	Ding-Jyh Tsaur, Chi-Feng Tang, Chin-Chi Wu, Woei Lin	A Threshold-Based Matching Algorithm for Photonic Clos Network Switches.	HPCC	2005	DBLP DOI BibTeX RDF	MAC, Packet Scheduling, Clos network, optical packet switching, Photonic switch
21	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	A Scalable Communication-Centric SoC Interconnect Architecture.	ISQED	2004	DBLP DOI BibTeX RDF	switch-based interconnect, butterfly fat-tree, global wire delay, System on chip, interconnect architecture, timing closure
21	Constantine E. Steriadis, Philip Constantinou	Designing human-computer interfaces for quadriplegic people.	ACM Trans. Comput. Hum. Interact.	2003	DBLP DOI BibTeX RDF	graphical keyboard, motor-impaired users, mouse simulation, quadriplegic people, scanning selection, single-switch input, wifsid, Accessibility, assistive technology, disability, word-prediction, augmentative communications
21	Isaac Keslassy, Shang-Tse Chuang, Kyoungsik Yu, David A. B. Miller, Mark Horowitz, Olav Solgaard, Nick McKeown	Scaling internet routers using optics.	SIGCOMM	2003	DBLP DOI BibTeX RDF	load-balancing, packet-switch, internet router
21	Yossi Azar, Yossi Richter	Management of multi-queue switches in QoS networks.	STOC	2003	DBLP DOI BibTeX RDF	QoS, competitive, switch, on-line
21	Xiaojun Shen, Fan Yang, Yi Pan 0001	Equivalent permutation capabilities between time-division optical omega networks and non-optical extra-stage omega networks.	IEEE/ACM Trans. Netw.	2001	DBLP DOI BibTeX RDF	crosstalk-free connection, dilated MIN, time-domain approach, optical switch, Omega network, Conflict graph
21	Arjan Durresi, Gojko Babic, Raj Jain	Measurement of ATM Frame Latency.	LCN	2000	DBLP DOI BibTeX RDF	ATM frame latency measurement, MIMO latency, message-in message-out latency, latency metrics, continuous frame technologies, measurement results, switch performance, MIMO aggregation, network element, network interconnections, quality of service, asynchronous transfer mode, MIMO systems, telecommunication networks, QoS parameters, network devices
21	Lluís Ribas, Jordi Carrabina	Digital MOS Circuit Partitioning with Symbolic Modeling.	DATE	1999	DBLP DOI BibTeX RDF	switch-level circuit analysis, symbolic circuit traversal, circuit partitioning, symbolic modeling
21	David B. Stewart, Pradeep K. Khosla	Policy-independent real-time operating system mechanisms for timing error detection, handling and monitoring.	HASE	1996	DBLP DOI BibTeX RDF	supervisory programs, policy independent real time operating system mechanisms, timing error detection, estimated worst case execution times, missed deadline, policy independent mechanisms, real time task monitoring, reschedule operation, monitoring mechanism, 6 ms, 1 Kbyte, hard real time systems, scheduling policies, context switch, error handling
21	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	On Design of Fail-Safe Cellular Arrays.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	fail-safe logic system, Binary Decision Diagram and switch cell, cellular array
21	Victor C. S. Lee, Joseph Kee-Yin Ng, Kam-yiu Lam, Sheung-lun Hung	Performance Studies of Transmitting Real-Time MPEG-I Video in ATM Networks.	LCN	1996	DBLP DOI BibTeX RDF	real-time MPEG-I video, real video programmes, workload characteristics, cell miss ratio, deadline missing, burst loss ratio, first-come-first-serve scheduling algorithm, virtual path bandwidth, simulation, asynchronous transfer mode, ATM networks, buffer overflow, ATM switch, gateways, performance studies, video data, video clips, cell loss ratio
21	Young-Wook Cha, Jong-Oh Kim, Kyou-Ho Lee, Ki Jun Han	Multiaccess ATM Network for Residential and Small Business Subscribers.	LCN	1996	DBLP DOI BibTeX RDF	OAM reference model, small business subscribers, residential subscribers, shared medium-based multiaccess technology, switch port granularity, multiaccess ATM customer network, asynchronous transfer mode, switches, network architecture, connection management, connection control
21	Zhaohui Yan 0002, Yih-Chyun Jenq	Performance Analysis of a Banyan-Based ATM Switching Fabric with Packet Priority.	LCN	1996	DBLP DOI BibTeX RDF	Banyan based ATM switching fabric, packet priority, single-buffered Banyan network, three-state Markov chain model, uniform traffic, blocked packet routing, fully loaded six-stage switch, simulation, performance analysis, asynchronous transfer mode, delay, statistical analysis, throughput, analytical model, contention, delay variation
21	Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	A cellular array designed from a Multiple-valued Decision Diagram and its fault tests.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	multiple-valued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuck-at faults
21	Qiang Li, David B. Gustavson	Fat-tree for local area multiprocessors.	IPPS	1995	DBLP DOI BibTeX RDF	local area multiprocessors, LAMP, high-performance low-cost parallel computing, LAN-size area, remote data cache, high performance multiprocessor, point-to-point physical connections, high system throughput, fat-tree topology, cable length, link clock speeds, biCMOS chips, performance evaluation, parallel architectures, parallel architecture, multiprocessor interconnection networks, local area networks, latency, packet switching, packet switch, CMOS, shared memory systems, distributed memory systems, simulation results, cache storage, system buses, SCI, buffer requirements, distributed-shared-memory multiprocessor, scalable coherent interface
21	Yakov Rekhter, Dilip D. Kandlur	Phasing ATM technology into an IP environment.	ICCCN	1995	DBLP DOI BibTeX RDF	logical IP subnetworks, ATM technology, ATM deployment, TCP/IP environment, address mapping servers, LAN Emulation, switch based infrastructure, router based overlay, asynchronous transfer mode, routing protocols, SVC, DNS, backward compatibility, IP over ATM
21	Amr Elsaadany, Mukesh Singhal, Ming T. Liu	Performance study of buffering within switches in local area networks.	ICCCN	1995	DBLP DOI BibTeX RDF	switch performance, network transfer rates, output ports, input ports, LAN performance, multimedia, delay, throughput, local area networks, local area networks, buffering, queueing model, buffer size, performance study, output buffer, packet loss rate
21	Yann-Hang Lee, Randy Chow, Sandra E. Cheung	Circular window control schemes in fast packet switches.	ICCCN	1995	DBLP DOI BibTeX RDF	circular window control scheme, fast packet switches, packet switch fabrics, fixed length window, circular transmission sequences, contentions minimisation, maximal throughput, nonblocking switches, banyan-based blocking switches, performance analysis, packet switching, scheduling algorithm, queueing, simulation results
21	Peter A. Franaszek, Christos J. Georgiou, Chung-Sheng Li	Adaptive routing in Clos networks.	ICCD	1995	DBLP DOI BibTeX RDF	three-stage Clos nonblocking switch, control network, heavily nonuniform traffic conditions, multiprocessor interconnection networks, adaptive routing, Clos networks
21	R. Gopalakrishnan, Guru M. Parulkar	RMDP-a real-time CPU scheduling algorithm to provide QoS guarantees for protocol processing.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	RMDP real-time CPU scheduling algorithm, processing guarantees, reduced contest switch operations, bandwidth guarantees, protocol session, NetBSD operating system, simulation, simulation, scheduling, real-time systems, protocols, delays, multimedia applications, processor scheduling, operating systems (computers), multimedia computing, QoS guarantees, delay guarantees, schedulability test, protocol processing
21	Phyllis Crandall	The Limited Applicability of Block Decomposition in Cluster Computing.	HPDC	1995	DBLP DOI BibTeX RDF	block decomposition, high-speed switch technology, mathematical characterizations, contiguous partitioning, ring-connected networks, simulations, performance evaluation, cluster computing, switched network, FDDI, FDDI, token networks
21	Steven Emerson	Performance evaluation of switched fibre channel I/O system using-FCP for SCSI.	LCN	1995	DBLP DOI BibTeX RDF	peripheral interfaces, switched fibre channel, FCP for SCSI, mixed mode protocol, Ancor switch, 46 to 65 Mbyte/s, 1.0625 Gbit/s, performance evaluation, performance evaluation, protocols
21	Hideaki Yamashita	Discrete-time analysis of a classified multi-server queue with burst arrivals and a shared buffer.	Queueing Syst. Theory Appl.	1994	DBLP DOI BibTeX RDF	burst arrival, Markov chain, ATM switch, Discrete-time queue, shared buffer
21	Anant Agarwal	Limits on Interconnection Network Performance.	IEEE Trans. Parallel Distributed Syst.	1991	DBLP DOI BibTeX RDF	buffered networks, interconnection network performance, wiredelays, two-dimensionalnetwork, switch delays, four-dimensional networks, networkbandwidth requirements, multiprocessor interconnection networks, latency, direct networks, network contention, performanceevaluation, closed-form expression, packet size, communication locality
21	Antoni Roca 0001, Carles Hernández 0001, José Flich, Federico Silla, José Duato	A Distributed Switch Architecture for On-Chip Networks.	ICPP	2011	DBLP DOI BibTeX RDF	switch implementation, network-on-chip
21	Sahin Cem Geyik, Boleslaw K. Szymanski, Petros Zerfos, Abbe Mowshowitz	Sensor Service Selection through Switch Options.	IEEE SCC	2011	DBLP DOI BibTeX RDF	switch options, sensor networks, service-oriented architecture, service selection, service modeling, real options
21	Nanli Zhu, Meng Cheng, Jianbo Fan, Rina Shu	Applying Role-Switch Model in College Information Technology Course.	CIT	2010	DBLP DOI BibTeX RDF	Teaching Model, Role-Switch, Teaching Effect
21	Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer	Using SMT to Hide Context Switch Times of Large Real-Time Tasksets.	RTCSA	2010	DBLP DOI BibTeX RDF	hardware scheduler, in-order multithreading, hard real-time, SMT, context switch
21	Chang-yong Zhang, Gui-he Hao	Design of Mine LV Switch Protector Based on Dual-CPU of ARM and DSP.	MVHI	2010	DBLP DOI BibTeX RDF	Feed switch, Protector, DS, Real-time data acquisition, ARM
21	Shyam Parthasarathy, Amit Ranjan Trivedi, Saurabh Sirohi, Robert A. Groves, Michael Olsen, Yogesh Singh Chauhan, Michael Carroll, Dan Kerr, Ali Tombak, Phil Mason	RF SOI Switch FET Design and Modeling Tradeoffs for GSM Applications.	VLSI Design	2010	DBLP DOI BibTeX RDF	RF Switch, SPDT, GSM
21	Yang Li, Chen Ying, Xiao Qianhua	A Small Power Switching Mode Power Supply Based on TOP Switch.	JCAI	2009	DBLP DOI BibTeX RDF	switching mode power supply, tech-parameter, TOP Switch, fly-back converter
21	Giuliano Casale, Amir S. Kalbasi, Diwakar Krishnamurthy, Jerry Rolia	Automatic Stress Testing of Multi-tier Systems by Dynamic Bottleneck Switch Generation.	Middleware	2009	DBLP DOI BibTeX RDF	bottleneck switch, performance, Benchmarking, burstiness
21	Erik Forsberg	The electron waveguide y-branch switch: a review and arguments for its use as a base for reversible logic.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	electron waveguide devices, y-branch switch, reversible computing
21	Sung Hyuk Byun, Dan Keun Sung	The UniMIN switch architecture for large-scale ATM switches.	IEEE/ACM Trans. Netw.	2000	DBLP DOI BibTeX RDF	UniMIN, fair virtual FIFO, general expansion architecture, distribution network, ATM switch
21	Jae-Hyun Park, Hyunsoo Yoon, Heung-Kyu Lee	The deflection self-routing Banyan network: a large-scale ATM switch using the fully adaptive self-routing and its performance analyses.	IEEE/ACM Trans. Netw.	1999	DBLP DOI BibTeX RDF	algecraic formalism, deflection self-routing Banyan network, unbuffered Banyan network, performance evaluation, ATM switch, topological properties
21	Radu Negulescu	Event-Driven Verification of Switch-Level Correctness Concerns.	ACSD	1998	DBLP DOI BibTeX RDF	switch-level, Verification, concurrency, safety, deadlock, asynchronous, event-driven, speed-independence, process spaces
21	Feihong Chen, Bülent Yener, Ali N. Akansu, Sirin Tekinay	A Novel Performance Analysis for the Copy Network in a Multicast ATM Switch.	ICCCN	1998	DBLP DOI BibTeX RDF	Copy Network, Multicast, ATM switch
21	Hiroyuki Ohsaki, Naoki Wakamiya, Masayuki Murata 0001, Hideo Miyahara	Performance of an input/output buffered-type ATM LAN switch with back-pressure function.	IEEE/ACM Trans. Netw.	1997	DBLP DOI BibTeX RDF	back-pressure function, input/output buffered type switch, bursty traffic, ATM LAN
21	Peter Dahlgren	Switch-level modeling of feedback faults using global oscillation control.	VTS	1997	DBLP DOI BibTeX RDF	global oscillation control, asynchronous behavior, fault diagnosis, fault diagnosis, bridging fault, logic simulation, feedback loop, switch-level model
21	Randal E. Bryant	A Switch-Level Model and Simulator for MOS Digital Systems.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	MOS logic simulation, VLSI, switch-level model
20	Dmitry G. Korzun, Andrei V. Gurtov	A local equilibrium model for P2P resource ranking.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
20	Bill Lin 0001, Jun (Jim) Xu, Nan Hua, Hao Wang 0006, Haiquan (Chuck) Zhao	A randomized interleaved DRAM architecture for the maintenance of exact statistics counters.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
20	Sipat Triukose, Zhihua Wen, Michael Rabinovich	Content delivery networks: how big is big enough?	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
20	Alma Riska, Erik Riedel	Evaluation of disk-level workloads at different time scales.	SIGMETRICS Perform. Evaluation Rev.	2009	DBLP DOI BibTeX RDF
20	Xiangrong Zhou, Peter Petrov	Cross-layer customization for rapid and low-cost task preemption in multitasked embedded systems.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF
20	Yu-Hsun Lin, Xuan-Yi Lin, Yeh-Ching Chung	Reducing Leakage Power of JPEG Image on Asymmetric SRAM.	CSE (2)	2009	DBLP DOI BibTeX RDF
20	Simin He 0001, Shutao Sun, Hong-Tao Guan, Qiang Zheng, Youjian Zhao, Wen Gao 0001	On guaranteed smooth switching for buffered crossbar switches.	IEEE/ACM Trans. Netw.	2008	DBLP DOI BibTeX RDF	scheduling, smoothness, switches, buffered crossbar
20	Marios S. Andreou, Aad P. A. van Moorsel	Logging based IP Traceback in switched ethernets.	EUROSEC	2008	DBLP DOI BibTeX RDF	IP
20	Rubén Arteaga, Félix Tobajas, Roberto Esper-Chaín, V. de Armas, Roberto Sarmiento	GMDS: Hardware implementation of novel real output queuing architecture.	DATE	2008	DBLP DOI BibTeX RDF
20	Choonho Son, Junsuk Oh, Kyoung-Ho Lee, Kieung Kim, Jaehyung Yoo	Efficient physical topology discovery for large OSPF networks.	NOMS	2008	DBLP DOI BibTeX RDF
20	Hong Cheng, Yaohui Jin, Yu Gao, Ying Di Yu, Weisheng Hu, Nirwan Ansari	Per-Flow Re-Sequencing in Load-Balanced Switches by Using Dynamic Mailbox Sharing.	ICC	2008	DBLP DOI BibTeX RDF
20	Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wladek Olesinski, Hans Eberle, Nils Gura	Backlog Aware Scheduling for Large Buffered Crossbar Switches.	ICC	2008	DBLP DOI BibTeX RDF
20	Jiun-Shiou Deng, Ming-Feng Lu, Yang-Tung Huang	High performance rearrangeable nonblocking networks with polarization selective elements.	ICON	2008	DBLP DOI BibTeX RDF
20	Jorge C. S. Castro, João Manuel Ferreira Pedro, Paulo P. Monteiro	Routing and buffer placement optimization in optical burst switched networks.	LCN	2008	DBLP DOI BibTeX RDF
20	Harry Chia-Hung Hsu, Alan Liu	A Flexible Architecture for Navigation Control of a Mobile Robot.	IEEE Trans. Syst. Man Cybern. Part A	2007	DBLP DOI BibTeX RDF
20	Jay Cheng	Constructions of Fault-Tolerant Optical 2-to-1 FIFO Multiplexers.	IEEE Trans. Inf. Theory	2007	DBLP DOI BibTeX RDF
20	Marwan H. Abu-Amara, Sadiq M. Sait, Abdul Subhan	A heuristics based approach for cellular mobile network planning.	IWCMC	2006	DBLP DOI BibTeX RDF	cell assignment, optimization, wireless networks, heuristics, network design
20	Shun-Ichi Azuma, Magnus Egerstedt, Yorai Wardi	Output-Based Optimal Timing Control of Switched Systems.	HSCC	2006	DBLP DOI BibTeX RDF
20	Francisco Gilabert Villamón, María Engracia Gómez, Pedro López 0001, José Duato	On the Influence of the Selection Function on the Performance of Fat-Trees.	Euro-Par	2006	DBLP DOI BibTeX RDF	selection function, interconnection networks, adaptive routing, fat-tree
20	Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota	Evaluation of SEU and crosstalk effects in network-on-chip switches.	SBCCI	2006	DBLP DOI BibTeX RDF	network-on-chip, crosstalk, single-event upset
20	Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis	Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications.	IPDPS	2006	DBLP DOI BibTeX RDF
20	Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis	A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Yossi Azar, Nir Levy	Multiplexing Packets with Arbitrary Deadlines in Bounded Buffers.	SWAT	2006	DBLP DOI BibTeX RDF
20	Gerry Moschopoulos, Wannian Huang	A New Family of Auxiliary Circuits for ZVT-PWM Converters: Synthesis, Circuits, Results.	CCECE	2006	DBLP DOI BibTeX RDF
20	Wilson Eberle, Yan-Fei Liu, Paresh C. Sen	A Simple Large Signal Model for Isolated DC-DC Converters.	CCECE	2006	DBLP DOI BibTeX RDF
20	Mahesh Sivakumar, Krishna M. Sivalingam	Limited Grooming Architectures and Groomer-port Placement in Optical WDM Mesh Networks.	BROADNETS	2006	DBLP DOI BibTeX RDF
20	Hwa-Chun Lin, Shyh-Arng Ding, Show-Shiow Tzeng	Slanted Frame Arrangement on Multiple Frequency Carriers in TDD Based PRMA.	Int. J. Wirel. Inf. Networks	2005	DBLP DOI BibTeX RDF	Dynamic TDD, frame arrangement, multiple frequency carriers, PRMA
20	Isaac Keslassy, Cheng-Shang Chang, Nick McKeown, Duan-Shin Lee	Optimal load-balancing.	INFOCOM	2005	DBLP DOI BibTeX RDF
20	David N. Abramson, Jordan D. Gray, Christopher M. Twigg, Paul E. Hasler	Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
20	Jordi Madrenas, Daniel Fernández, Jordi Cosp, Eduard Alarcón, Eva Vidal, Gerard Villar	Selective similarity function for VLSI analog signal processing.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
20	John Shalf, Shoaib Kamil 0001, Leonid Oliker, David Skinner	Analyzing Ultra-Scale Application Communication Requirements for a Reconfigurable Hybrid Interconnect.	SC	2005	DBLP DOI BibTeX RDF
20	Hagit Attiya, David Hay	Randomization does not reduce the average delay in parallel packet switches.	SPAA	2005	DBLP DOI BibTeX RDF	oblivious adversary, load balancing, packet switching, randomization, clos networks, queuing delay, inverse multiplexing, adaptive adversary
20	Saad Mneimneh	An Iterative Switching Algorithm With (Possibly) One Iteration.	NCA	2004	DBLP DOI BibTeX RDF	number of iterations, matching, Switching, speedup
20	Claus Bauer	Stable Local Scheduling Algorithms With Low Complexity and Without Speedup for a Network of Input-Buffered Switches.	CAAN	2004	DBLP DOI BibTeX RDF
20	Hagit Attiya, David Hay	The inherent queuing delay of parallel packet switches.	SPAA	2004	DBLP DOI BibTeX RDF	leaky-bucket traffic, load balancing, packet switching, clos networks, queuing delay, delay jitter, inverse multiplexing
20	Ming Hao, Mark A. Heinrich	Active I/O Switches in System Area Networks.	HPCA	2003	DBLP DOI BibTeX RDF
20	Renqiu Huang, Tommy Cheung, Ted Chi-Wah Kok	A Statistical Analysis Tool for FPLD Architectures.	FPL	2003	DBLP DOI BibTeX RDF
20	María Engracia Gómez, José Flich, Antonio Robles, Pedro López 0001, José Duato	VOQSW: A Methodology to Reduce HOL Blocking in InfiniBand Networks.	IPDPS	2003	DBLP DOI BibTeX RDF	InfiniBand network, virtual lanes, irregular topologies, head-of-line blocking
20	YoungWook Cha, TaeHyun Kwon, Choon Hee Kim, Jun Kyun Choi	Network Management Services in GSMP Open Interface.	Human.Society@Internet 2003	2003	DBLP DOI BibTeX RDF
20	Oleg Gusak, Neal Oliver, Khosrow Sohraby	Performance Analysis of Packet Schedulers in High-Speed Serial Switches.	ISCIS	2003	DBLP DOI BibTeX RDF
20	Peng Yi, Yuguo Dong, Yuntao Li, Yunfei Guo	Stability Analysis of the PPS with Bufferless in Input De-Multiplexers.	AINA	2003	DBLP DOI BibTeX RDF
20	Arun Saha, Mart L. Molle	Thinking Outside the Box: Extending 802.1x Authentication to Remote "Splitter" Ports by Combining Physical and Data Link Layer Techniques.	LCN	2003	DBLP DOI BibTeX RDF
20	Guy G. Lemieux, David M. Lewis	Circuit design of routing switches.	FPGA	2002	DBLP DOI BibTeX RDF
20	Nils Gura, Hans Eberle	The Least Choice First Scheduling Method for High-Speed Network Switche.	IPDPS	2002	DBLP DOI BibTeX RDF
20	Federico Silla, José Duato	High-Performance Routing in Networks of Workstations with Irregular Topology.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	adaptive routing, Networks of workstations, wormhole switching, deadlock avoidance, irregular topologies
20	James Holt, Wuxu Peng	Improving the PIM Routing Protocol with Adaptive Switching Mechanism between Its Two Sparse Sub-Modes.	ICCCN	1998	DBLP DOI BibTeX RDF	Multicast, Routing Protocols, Adaptive Routing
20	Slobodan S. Petrovic	ABR Service in ATM Networks: Performance Comparison Between BECN and Adaptive Stochastic Congestion Control Schemes with Guaranteed Minimum Cell Rate.	Multimedia Information Systems	1998	DBLP DOI BibTeX RDF
20	Federico Silla, Manuel P. Malumbres, Antonio Robles, Pedro López 0001, José Duato	Efficient Adaptive Routing in Networks of Workstations with Irregular Topology.	CANPC	1997	DBLP DOI BibTeX RDF
20	Yi-Shing Chang, Sandeep K. Gupta 0001, Melvin A. Breuer	Analysis of Ground Bounce in Deep Sub-Micron Circuits.	VTS	1997	DBLP DOI BibTeX RDF	deep sub-micron technology, ground bounce
20	Paul Shipley, Sherif Sayed, Magdy A. Bayoumi	A High Speed VLSI Architecture for Scaleable ATM Switches.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
20	Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou	An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors.	EDCC	1994	DBLP DOI BibTeX RDF