Search results for "ARC"

Hits ?▲	Authors	Title	Venue	Year	Link
28	Enrique Sedano, Daniel Ménard, Juan A. López	Automated Data Flow Graph Partitioning for a Hierarchical Approach to Wordlength Optimization.	ARC	2014	DBLP DOI BibTeX RDF
28	Tobias Kenter, Gavin Vaz, Christian Plessl	Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.	ARC	2014	DBLP DOI BibTeX RDF
28	Ali Asghar, Husain Parvez	Diffusion-Based Placement Algorithm for Reducing High Interconnect Demand in Congested Regions of FPGAs.	ARC	2014	DBLP DOI BibTeX RDF
28	José Gabriel F. Coutinho, Oliver Pell, Eoghan O'Neill, Peter Sanders 0002, John McGlone, Paul Grigoras, Wayne Luk, Carmelo Ragusa	HARNESS Project: Managing Heterogeneous Computing Resources for a Cloud Platform.	ARC	2014	DBLP DOI BibTeX RDF
28	Sebastian Meisner, Marco Platzner	Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection.	ARC	2014	DBLP DOI BibTeX RDF
28	Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton	Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry.	ARC	2014	DBLP DOI BibTeX RDF
28	Jalal Khalifat, Ali Ebrahim, Tughrul Arslan	An Efficient Implementation of the Adams-Hamilton's Demosaicing Algorithm in FPGAs.	ARC	2014	DBLP DOI BibTeX RDF
28	Gianluca Durelli, Marcello Coppola, Karim Djafarian, George Kornaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, Cristiana Bolchini	SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.	ARC	2014	DBLP DOI BibTeX RDF
28	Ioannis Sourdis, Christos Strydis, Antonino Armato, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Sebastián Isaza, Alirad Malek, R. Mariani, Samuel N. Pagliarini, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Robert M. Seepers, Rishad Ahmed Shafik, Georgios Smaragdos, Dimitris Theodoropoulos, Stavros Tzilis, Michalis Vavouras	DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCs.	ARC	2014	DBLP DOI BibTeX RDF
28	Carsten Tradowsky, Martin Schreiber 0001, Malte Vesper, Ivan Domladovec, Maximilian Braun, Hans-Joachim Bungartz, Jürgen Becker 0001	Towards Dynamic Cache and Bandwidth Invasion.	ARC	2014	DBLP DOI BibTeX RDF
28	Pablo Calleja, Gabriel Caffarena, Ana Iriarte	FPGA Design of Delay-Based Digital Effects for Electric Guitar.	ARC	2014	DBLP DOI BibTeX RDF
28	Zdravko Panjkov, Juergen Haas, Martin Aigner 0002, Herbert Rosmanith, Tianlun Liu, Roland Poppenreiter, Andreas Wasserbauer, Richard Hagelauer	OCP2XI Bridge: An OCP to AXI Protocol Bridge.	ARC	2014	DBLP DOI BibTeX RDF
28	Alexander Wold, Andreas Agne, Jim Tørresen	Relocatable Hardware Threads in Run-Time Reconfigurable Systems.	ARC	2014	DBLP DOI BibTeX RDF
28	Joonseok Park, Pedro C. Diniz	Evaluating High-Level Program Invariants Using Reconfigurable Hardware.	ARC	2014	DBLP DOI BibTeX RDF
28	Jürgen Becker 0001, Thomas Bruckschlögl, Oliver Oey, Timo Stripf, George Goulas, Nick Raptis, Christos Valouxis, Panayiotis Alefragis, Nikolaos S. Voros, Christos Gogos	Profile-Guided Compilation of Scilab Algorithms for Multiprocessor Systems.	ARC	2014	DBLP DOI BibTeX RDF
28	Taimour Wehbe, Xiaofang Wang	Efficient Buffer Design and Implementation for Wormhole Routers on FPGAs.	ARC	2014	DBLP DOI BibTeX RDF
28	Karim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez	FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm.	ARC	2014	DBLP DOI BibTeX RDF
28	Dionisios N. Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Georgi Nedeltchev Gaydadjiev, Wayne Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, Danilo Pau, Oliver Pell, Christian Pilato, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt	Effective Reconfigurable Design: The FASTER Approach.	ARC	2014	DBLP DOI BibTeX RDF
28	Karel Heyse, Dirk Stroobandt, Oliver Kadlcek, Oliver Pell	On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA's Configuration Infrastructure.	ARC	2014	DBLP DOI BibTeX RDF
28	Andreas Engel 0003, Andreas Koch 0001	Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks.	ARC	2014	DBLP DOI BibTeX RDF
28	Max Ferger, Michael Hübner 0001	Instruction Set Optimization for Application Specific Processors.	ARC	2014	DBLP DOI BibTeX RDF
28	Pascal Schleuniger, Sven Karlsson	A Synthesizable Multicore Platform for Microwave Imaging.	ARC	2014	DBLP DOI BibTeX RDF
28	Anja Niedermeier, Jan Kuper, Gerard J. M. Smit	A Dataflow Inspired Programming Paradigm for Coarse-Grained Reconfigurable Arrays.	ARC	2014	DBLP DOI BibTeX RDF
28	Philip Brisk, José Gabriel F. Coutinho, Pedro C. Diniz (eds.)	Reconfigurable Computing: Architectures, Tools and Applications - 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings	ARC	2013	DBLP DOI BibTeX RDF
28	Kiran Kumar Matam, Viktor K. Prasanna	Algorithm Design Methodology for Embedded Architectures.	ARC	2013	DBLP DOI BibTeX RDF
28	Shane T. Fleming, David B. Thomas	Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields.	ARC	2013	DBLP DOI BibTeX RDF
28	Youenn Corre, Jean-Philippe Diguet, Loïc Lagadec, Dominique Heller, Dominique Blouin	Fast Template-Based Heterogeneous MPSoC Synthesis on FPGA.	ARC	2013	DBLP DOI BibTeX RDF
28	Gabriel Nunez, Evan Tsai, Airs Lin, Aleksander Milshteyn, Garth Herman, Helen Boussalis, Charles Liu	High Level FPGA Modeling of an JPEG Encoder.	ARC	2013	DBLP DOI BibTeX RDF
28	Vitor Gomes 0001, Haroldo Fraga de Campos Velho, Andrea Charão	A Fast Poisson Solver for Hybrid Reconfigurable System.	ARC	2013	DBLP DOI BibTeX RDF
28	Geoffrey Ottoy, Bart Preneel, Jean-Pierre Goemaere, Lieven De Strycker	Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms.	ARC	2013	DBLP DOI BibTeX RDF
28	Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez	Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist.	ARC	2013	DBLP DOI BibTeX RDF
28	Uli Kretzschmar, Armando Astarloa, Jesús Lázaro 0001	SEU Resilience of DES, AES and Twofish in SRAM-Based FPGA.	ARC	2013	DBLP DOI BibTeX RDF
28	Christopher J. Martinez	Teaching SoC Using Video Games to Improve Student Engagement.	ARC	2013	DBLP DOI BibTeX RDF
28	Fakhar Anjam, Stephan Wong	Configurable Fault-Tolerance for a Configurable VLIW Processor.	ARC	2013	DBLP DOI BibTeX RDF
28	Qi Guo, Chao Wang 0003, Xuehai Zhou, Xi Li 0003	Pipeline Optimization for Loops on Reconfigurable Platform.	ARC	2013	DBLP DOI BibTeX RDF
28	Stephan Wong	Embedded Reconfigurable Architectures.	ARC	2013	DBLP DOI BibTeX RDF
28	Sam Skalicky, Sonia López, Marcin Lukowiak, James Letendre, Matthew Ryan	Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs.	ARC	2013	DBLP DOI BibTeX RDF
28	Li Zhou, Dongpei Liu, Botao Zhang, Hengzhu Liu	Ant Colony Optimization for Application Mapping in Coarse-Grained Reconfigurable Array.	ARC	2013	DBLP DOI BibTeX RDF
28	Christos P. Antonopoulos, George Krikis, Nikolaos S. Voros	Efficient Hardware Based Security Algorithm Implementation for WSN Medical Applications: The ARMOR Perspective.	ARC	2013	DBLP DOI BibTeX RDF
28	Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso	Architecture for Transparent Binary Acceleration of Loops with Memory Accesses.	ARC	2013	DBLP DOI BibTeX RDF
28	Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto	Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-Based Custom Computing.	ARC	2013	DBLP DOI BibTeX RDF
28	Takuya Kuhara, Takaaki Miyajima, Masato Yoshimi, Hideharu Amano	An FPGA Acceleration for the Kd-tree Search in Photon Mapping.	ARC	2013	DBLP DOI BibTeX RDF
28	Yuya Shirahashi, Minoru Watanabe	Dependability-Increasing Method of Processors under a Space Radiation Environment.	ARC	2013	DBLP DOI BibTeX RDF
28	James Arram, Kuen Hung Tsoi, Wayne Luk, Peiyong Jiang	Hardware Acceleration of Genetic Sequence Alignment.	ARC	2013	DBLP DOI BibTeX RDF
28	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura	An Architecture for IPv6 Lookup Using Parallel Index Generation Units.	ARC	2013	DBLP DOI BibTeX RDF
28	Mohammed A. S. Abdallah	FPGA-Based Adaptive Data Acquisition Scheduler-on-Chip (SchoC) for Heterogeneous Signals.	ARC	2013	DBLP DOI BibTeX RDF
28	Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez	Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA.	ARC	2013	DBLP DOI BibTeX RDF
28	Maciej Kurek, Tobias Becker, Wayne Luk	Parametric Optimization of Reconfigurable Designs Using Machine Learning.	ARC	2013	DBLP DOI BibTeX RDF
28	Jingfei Jiang, Rongdong Hu, Mikel Luján, Yong Dou	Empirical Evaluation of Fixed-Point Arithmetic for Deep Belief Networks.	ARC	2013	DBLP DOI BibTeX RDF
28	Aurelio Morales-Villanueva, Ann Gordon-Ross	HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs.	ARC	2013	DBLP DOI BibTeX RDF
28	José Gabriel F. Coutinho, João M. P. Cardoso, Tiago Carvalho, Ricardo Nobre, Sujit Bhattacharya 0002, Pedro C. Diniz, Liam Fitzpatrick, Razvan Nane	Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract).	ARC	2013	DBLP DOI BibTeX RDF
28	Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura	C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join.	ARC	2013	DBLP DOI BibTeX RDF
28	Debora Matos, Cezar Reinbrecht, Márcio Eduardo Kreutz, Gianluca Palermo, Luigi Carro, Altamiro Amadeu Susin	Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability.	ARC	2013	DBLP DOI BibTeX RDF
28	George Goulas, Christos Gogos, Christos Valouxis, Panayiotis Alefragis, Nikolaos S. Voros	Coarse Grained Parallelism Optimization for Multicore Architectures: The ALMA Project Approach.	ARC	2013	DBLP DOI BibTeX RDF
28	Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski	Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications.	ARC	2013	DBLP DOI BibTeX RDF
28	Jon T. Butler, Tsutomu Sasao	Hardware Index to Set Partition Converter.	ARC	2013	DBLP DOI BibTeX RDF
28	Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid	Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform.	ARC	2013	DBLP DOI BibTeX RDF
28	Oliver C. S. Choy, Ray C. C. Cheung, Peter M. Athanas, Kentaro Sano (eds.)	Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings	ARC	2012	DBLP DOI BibTeX RDF
28	Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano	Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration.	ARC	2012	DBLP DOI BibTeX RDF
28	Fakhar Anjam, Quan Kong, Roel Seedorf, Stephan Wong	A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor.	ARC	2012	DBLP DOI BibTeX RDF
28	Xuan You Tan, David Boland, George A. Constantinides	FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores.	ARC	2012	DBLP DOI BibTeX RDF
28	Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang 0002, Jinian Bian	PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs.	ARC	2012	DBLP DOI BibTeX RDF
28	Qiang Liu 0011, Wayne Luk	Heterogeneous Systems for Energy Efficient Scientific Computing.	ARC	2012	DBLP DOI BibTeX RDF
28	Yongjoo Kim, Jongeun Lee, Jinyong Lee, Toan X. Mai, Ingoo Heo, Yunheung Paek	Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture.	ARC	2012	DBLP DOI BibTeX RDF
28	Grigorios Mingas, Christos-Savvas Bouganis	Parallel Tempering MCMC Acceleration Using Reconfigurable Hardware.	ARC	2012	DBLP DOI BibTeX RDF
28	Kashif Latif, M. Muzaffar Rao, Athar Mahboob, Arshad Aziz	Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms.	ARC	2012	DBLP DOI BibTeX RDF
28	Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt	Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration.	ARC	2012	DBLP DOI BibTeX RDF
28	Tassadaq Hussain, Muhammad Shafiq 0003, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé	PPMC: A Programmable Pattern Based Memory Controller.	ARC	2012	DBLP DOI BibTeX RDF
28	Yarkin Doröz, Erkay Savas	Constructing Cluster of Simple FPGA Boards for Cryptologic Computations.	ARC	2012	DBLP DOI BibTeX RDF
28	Ehsan Zadkhosh, Sepide Fatahi, Mahmood Ahmadi	Performance Analysis of Reconfigurable Processors Using MVA Analysis.	ARC	2012	DBLP DOI BibTeX RDF
28	Geoffrey Ndu, Jim D. Garside	Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration.	ARC	2012	DBLP DOI BibTeX RDF
28	Takahiro Watanabe, Minoru Watanabe	Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays.	ARC	2012	DBLP DOI BibTeX RDF
28	Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas, Wayne Luk	Optimising Performance of Quadrature Methods with Reduced Precision.	ARC	2012	DBLP DOI BibTeX RDF
28	Shinya Takamaeda-Yamazaki, Shintaro Sano, Yoshito Sakaguchi, Naoki Fujieda, Kenji Kise	ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs.	ARC	2012	DBLP DOI BibTeX RDF
28	Sayyed Arash Ostadzadeh, Roel Meeuws, Imran Ashraf, Carlo Galuzzi, Koen Bertels	The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms.	ARC	2012	DBLP DOI BibTeX RDF
28	Sen Ma, Miaoqing Huang, Eugene Cartwright, David Andrews 0001	Scalable Memory Hierarchies for Embedded Manycore Systems.	ARC	2012	DBLP DOI BibTeX RDF
28	Tannous Frangieh, Richard Stroop, Peter Athanas, Teresa Cervero	A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems.	ARC	2012	DBLP DOI BibTeX RDF
28	Hongbing Fan, Yue-Ang Chen, Yu-Liang Wu	R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip.	ARC	2012	DBLP DOI BibTeX RDF
28	Annie Avakian, Natwar Agrawal, Ranga Vemuri	Reconfigurable Multicore Architecture for Dynamic Processor Reallocation.	ARC	2012	DBLP DOI BibTeX RDF
28	Chao Wang 0003, Xi Li 0003, Xuehai Zhou, Xiaojing Feng	CRAIS: A Crossbar Based Adaptive Interconnection Scheme.	ARC	2012	DBLP DOI BibTeX RDF
28	Kizheppatt Vipin, Suhaib A. Fahmy	Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration.	ARC	2012	DBLP DOI BibTeX RDF
28	Markus Weinhardt	Teaching Hardware/Software Codesign on a Reconfigurable Computing Platform.	ARC	2012	DBLP DOI BibTeX RDF
28	Tim Güneysu, Igor L. Markov, André Weimerskirch	Securely Sealing Multi-FPGA Systems.	ARC	2012	DBLP DOI BibTeX RDF
28	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura	A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU.	ARC	2012	DBLP DOI BibTeX RDF
28	Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt	A Connection Router for the Dynamic Reconfiguration of FPGAs.	ARC	2012	DBLP DOI BibTeX RDF
28	Stewart Denholm, Kuen Hung Tsoi, Peter R. Pietzuch, Wayne Luk	Efficient Communication for FPGA Clusters.	ARC	2012	DBLP DOI BibTeX RDF
28	Gang Zhou, Li Li 0027, Harald Michalik	Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs.	ARC	2012	DBLP DOI BibTeX RDF
28	Abid Rafique, Nachiket Kapre, George A. Constantinides	A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem.	ARC	2012	DBLP DOI BibTeX RDF
28	Florent de Dinechin, Laurent-Stéphane Didier	Table-Based Division by Small Integer Constants.	ARC	2012	DBLP DOI BibTeX RDF
28	Manish Kumar Jaiswal, Ray C. C. Cheung	High Performance Reconfigurable Architecture for Double Precision Floating Point Division.	ARC	2012	DBLP DOI BibTeX RDF
28	Luzhou Wang, Kentaro Sano, Satoru Yamamoto	Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array.	ARC	2012	DBLP DOI BibTeX RDF
28	Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary Chun Tak Chow, David B. Thomas, Wayne Luk, Stephen Weston	Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations.	ARC	2012	DBLP DOI BibTeX RDF
28	Wei Ting Loke, Yajun Ha	A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters.	ARC	2012	DBLP DOI BibTeX RDF
28	Andreas Koch 0001, Ram Krishnamurthy 0001, John McAllister, Roger F. Woods, Tarek A. El-Ghazawi (eds.)	Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings	ARC	2011	DBLP DOI BibTeX RDF
28	Umer Farooq 0001, Husain Parvez, Zied Marrakchi, Habib Mehrez	Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA.	ARC	2011	DBLP DOI BibTeX RDF
28	Kevin Cunningham, Prawat Nagvajara	Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers.	ARC	2011	DBLP DOI BibTeX RDF
28	Francisco Barranco, Matteo Tomasi, Javier Díaz 0001, Eduardo Ros 0001	Hierarchical Optical Flow Estimation Architecture Using Color Cues.	ARC	2011	DBLP DOI BibTeX RDF
28	Ming Liu 0011, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch	FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments.	ARC	2011	DBLP DOI BibTeX RDF
28	Hironobu Morita, Minoru Watanabe	MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays.	ARC	2011	DBLP DOI BibTeX RDF
28	Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk	FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design.	ARC	2011	DBLP DOI BibTeX RDF