Search results for "DFT"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Luca Amati, Cristiana Bolchini, Laura Frigerio, Fabio Salice, William Eklow, Arnold Suvatne, Eugenio Brambilla, Federico Franzoso, Michele Martin	An Incremental Approach to Functional Diagnosis.	DFT	2009	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences.	DFT	2009	DBLP DOI BibTeX RDF
1	David Wolpert 0001, Paul Ampadu	A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits.	DFT	2009	DBLP DOI BibTeX RDF
1	Yueran Gao, Haibo Wang 0005	A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault Tolerance.	DFT	2009	DBLP DOI BibTeX RDF
1	Yehua Su, Wenjing Rao	Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis.	DFT	2009	DBLP DOI BibTeX RDF
1	Qiaoyan Yu, Paul Ampadu	Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip.	DFT	2009	DBLP DOI BibTeX RDF
1	Jianwei Dai, Lei Wang 0003	A Study of Side-Channel Effects in Reliability-Enhancing Techniques.	DFT	2009	DBLP DOI BibTeX RDF
1	Takumi Hoshi, Kazuteru Namba, Hideo Ito	Testing of Switch Blocks in Three-Dimensional FPGA.	DFT	2009	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Maria K. Michael, Kyriakos Christou	Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning.	DFT	2009	DBLP DOI BibTeX RDF
1	Aaron Dingler, M. Jafar Siddiq, Michael T. Niemier, Xiaobo Sharon Hu, M. Tanvir Alam, Gary H. Bernstein, Wolfgang Porod	Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power.	DFT	2009	DBLP DOI BibTeX RDF
1	Martin Omaña 0001, Daniele Rossi 0001, Cecilia Metra	Novel High Speed Robust Latch.	DFT	2009	DBLP DOI BibTeX RDF
1	Syed Zafar Shazli, Mehdi Baradaran Tahoori	Transient Error Detection and Recovery in Processor Pipelines.	DFT	2009	DBLP DOI BibTeX RDF
1	Adit D. Singh	A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS.	DFT	2009	DBLP DOI BibTeX RDF
1	Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	Improving the Detectability of Resistive Open Faults in Scan Cells.	DFT	2009	DBLP DOI BibTeX RDF
1	Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue	Reliability and Performance Analysis of FPGA-Based Fault Tolerant System.	DFT	2009	DBLP DOI BibTeX RDF
1	Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici	Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR).	DFT	2009	DBLP DOI BibTeX RDF
1	Yuu Maeda, Haruhiko Kaneko	Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check Codes.	DFT	2009	DBLP DOI BibTeX RDF
1	Martin Omaña 0001, Marcin Marzencki, Roberto Specchia, Cecilia Metra, Bozena Kaminska	Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors.	DFT	2009	DBLP DOI BibTeX RDF
1	Yu Liu, Kaijie Wu 0001	An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level.	DFT	2009	DBLP DOI BibTeX RDF
1	Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud	Complementary Formal Approaches for Dependability Analysis.	DFT	2009	DBLP DOI BibTeX RDF
1	George J. Starr, Jie Qin, Bradley F. Dutton, Charles E. Stroud, Foster F. Dai, Victor P. Nelson	Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems.	DFT	2009	DBLP DOI BibTeX RDF
1	Jenny Leung, Glenn H. Chapman, Israel Koren, Zahava Koren	Characterization of Gain Enhanced In-Field Defects in Digital Imagers.	DFT	2009	DBLP DOI BibTeX RDF
1	Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano	Error Correction Codes for SEU and SEFI Tolerant Memory Systems.	DFT	2009	DBLP DOI BibTeX RDF
1	Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Mark Hampton, Florian Letombe	On the Functional Qualification of a Platform Model.	DFT	2009	DBLP DOI BibTeX RDF
1	Bo Fu, Paul Ampadu	Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects.	DFT	2009	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Susumu Horiguchi, Spyros Tragoudas, Mohammad Tehranipoor (eds.)	24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009	DFT	2009	DBLP BibTeX RDF
1	Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang	Analysis of Resistive Open Defects in a Synchronizer.	DFT	2009	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Fabrizio Castro, Antonio Miele	A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems.	DFT	2009	DBLP DOI BibTeX RDF
1	Nader Alawadhi, Ozgur Sinanoglu	Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments.	DFT	2009	DBLP DOI BibTeX RDF
1	Unni Chandran, Dan Zhao	Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip.	DFT	2009	DBLP DOI BibTeX RDF
1	Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba	Improving Memory Repair by Selective Row Partitioning.	DFT	2009	DBLP DOI BibTeX RDF
1	Sandeep P. Kumar	Low DPM: Why Do We Need it and What Does it Cost!	DFT	2009	DBLP DOI BibTeX RDF
1	Meng Zhang 0017, Anita Lungu, Daniel J. Sorin	Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms.	DFT	2009	DBLP DOI BibTeX RDF
1	Nor Zaidi Haron, Said Hamdioui	Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories.	DFT	2009	DBLP DOI BibTeX RDF
1	Yusuke Fukushima, Masaru Fukushi, Susumu Horiguchi	Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels.	DFT	2009	DBLP DOI BibTeX RDF
1	Hans-Joachim Wunderlich	Software-Based Hardware Fault Tolerance for Many-Core Architectures.	DFT	2009	DBLP DOI BibTeX RDF
1	Yiorgos Makris	Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors.	DFT	2009	DBLP DOI BibTeX RDF
1	Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba	Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points.	DFT	2009	DBLP DOI BibTeX RDF
1	Michael Campbell	The Future of Test - Product Integration and its Impact on Test.	DFT	2009	DBLP DOI BibTeX RDF
1	Bradley F. Dutton, Charles E. Stroud	Soft Core Embedded Processor Based Built-In Self-Test of FPGAs.	DFT	2009	DBLP DOI BibTeX RDF
1	Mingjing Chen, Alex Orailoglu	Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience.	DFT	2009	DBLP DOI BibTeX RDF
1	Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto, Alessandro Savino	System Level Testing via TLM 2.0 Debug Transport Interface.	DFT	2009	DBLP DOI BibTeX RDF
1	Zahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi	Coded DNA Self-Assembly for Error Detection/Location.	DFT	2009	DBLP DOI BibTeX RDF
1	Rui Gong, Kui Dai, Zhiying Wang 0003	A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
1	Manoj Kumar Goparaju, Ashok Kumar Palaniswamy, Spyros Tragoudas	A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks.	DFT	2008	DBLP DOI BibTeX RDF
1	Yukiya Miura, Jiro Kato	Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling.	DFT	2008	DBLP DOI BibTeX RDF
1	Jae-Young Choi, Yoon-Hwa Choi	Fault Detection of Bloom Filters for Defect Maps.	DFT	2008	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Antonio Miele	Design Space Exploration for the Design of Reliable.	DFT	2008	DBLP DOI BibTeX RDF
1	Waleed K. Al-Assadi, Sindhu Kakarla	A BIST Technique for Crosstalk Noise Detection in FPGAs.	DFT	2008	DBLP DOI BibTeX RDF
1	Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.	DFT	2008	DBLP DOI BibTeX RDF
1	Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker 0001	On Reducing Circuit Malfunctions Caused by Soft Errors.	DFT	2008	DBLP DOI BibTeX RDF
1	Rajsekhar Adapa, Spyros Tragoudas	Prioritization of Paths for Diagnosis.	DFT	2008	DBLP DOI BibTeX RDF
1	David Wolpert 0001, Paul Ampadu	A Low-Power Safety Mode for Variation Tolerant Systems-on-Chip.	DFT	2008	DBLP DOI BibTeX RDF
1	Nimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, Duncan Walker	Built-In Proactive Tuning System for Circuit Aging Resilience.	DFT	2008	DBLP DOI BibTeX RDF
1	Hamed Tabkhi, Seyed Ghassem Miremadi, Alireza Ejlali	An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors.	DFT	2008	DBLP DOI BibTeX RDF
1	Vikas Chandra, Robert C. Aitken	Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS.	DFT	2008	DBLP DOI BibTeX RDF
1	Osnat Keren, Ilya Levin, Vladimir Ostrovsky, Beni Abramov	Arbitrary Error Detection in Combinational Circuits by Using Partitioning.	DFT	2008	DBLP DOI BibTeX RDF
1	Abhisek Pan, James W. Tschanz, Sandip Kundu	A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit.	DFT	2008	DBLP DOI BibTeX RDF
1	Kazuteru Namba, Hideo Ito	Delay Fault Testability on Two-Rail Logic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
1	Franco Fummi, Davide Quaglia, Francesco Stefanni	Network Fault Model for Dependability Assessment of Networked Embedded Systems.	DFT	2008	DBLP DOI BibTeX RDF
1	Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone	Material Fatigue and Reliability of MEMS Accelerometers.	DFT	2008	DBLP DOI BibTeX RDF
1	Kevin Sliech, Martin Margala	A Digital BIST for Phase-Locked Loops.	DFT	2008	DBLP DOI BibTeX RDF
1	Francesco Abate, Massimo Violante	Coping with Obsolescence of Processor Cores in Critical Applications.	DFT	2008	DBLP DOI BibTeX RDF
1	Michail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti	Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller.	DFT	2008	DBLP DOI BibTeX RDF
1	Nilanjan Mukherjee 0001	Targeting "Zero DPPM" - Can we ever get there?	DFT	2008	DBLP DOI BibTeX RDF
1	Laura Frigerio, Matteo Alan Radaelli, Fabio Salice	A Generalized Approach for the Use of Convolutional Coding in SEU Mitigation.	DFT	2008	DBLP DOI BibTeX RDF
1	Zahi S. Abuhamdeh	A Case Study of ATPG Delay Path Performance Based on Measured Power Rail Integrity.	DFT	2008	DBLP DOI BibTeX RDF
1	Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano	A Novel Error Detection and Correction Technique for RNS Based FIR Filters.	DFT	2008	DBLP DOI BibTeX RDF
1	Carlos Arthur Lang Lisbôa, Luigi Carro	XOR-based Low Cost Checkers for Combinational Logic.	DFT	2008	DBLP DOI BibTeX RDF
1	Yoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi	A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory.	DFT	2008	DBLP DOI BibTeX RDF
1	Prashant D. Joshi	Error Detect Logic Resulting in Faster Address Generate and Decode for Caches.	DFT	2008	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Yong-Bin Kim, Dimitris Gizopoulos, Mohammad Tehranipoor (eds.)	23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA	DFT	2008	DBLP BibTeX RDF
1	Francesco Regazzoni 0001, Thomas Eisenbarth 0001, Luca Breveglieri, Paolo Ienne, Israel Koren	Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?.	DFT	2008	DBLP DOI BibTeX RDF
1	Shuangyu Ruan, Kazuteru Namba, Hideo Ito	Soft Error Hardened FF Capable of Detecting Wide Error Pulse.	DFT	2008	DBLP DOI BibTeX RDF
1	Xiaoxiao Wang 0001, Hassan Salmani, Mohammad Tehranipoor, James F. Plusquellic	Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis.	DFT	2008	DBLP DOI BibTeX RDF
1	Kamran Zarrineh	Design for Test Challenges of High Performance/Low Power Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
1	Cecilia Metra, Martin Omaña 0001, T. M. Mak, Asifur Rahman, Simon Tam 0001	Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
1	Stephen Frechette, Yong-Bin Kim, Fabrizio Lombardi	Checkpointing of Rectilinear Growth in DNA Self-Assembly.	DFT	2008	DBLP DOI BibTeX RDF
1	Hongbin Sun 0001, Nanning Zheng 0001, Tong Zhang 0002	Realization of L2 Cache Defect Tolerance Using Multi-bit ECC.	DFT	2008	DBLP DOI BibTeX RDF
1	Saurabh Jain, W. Robert Daasch, David Armbrust	Analyzing the Impact of Fault Tolerant BIST for VLSI Design.	DFT	2008	DBLP DOI BibTeX RDF
1	Muhammad Ibrahim, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu	Minimization of CTS of k-CNOT Circuits for SSF and MSF Model.	DFT	2008	DBLP DOI BibTeX RDF
1	Hyunbean Yi, Sandip Kundu	Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing.	DFT	2008	DBLP DOI BibTeX RDF
1	Timothy J. Dysart, Peter M. Kogge	System Reliabilities When Using Triple Modular Redundancy in Quantum-Dot Cellular Automata.	DFT	2008	DBLP DOI BibTeX RDF
1	Jenny Leung, Glenn H. Chapman, Israel Koren, Zahava Koren	Automatic Detection of In-field eld Defect Growth in Image Sensors.	DFT	2008	DBLP DOI BibTeX RDF
1	Joon-Sung Yang, Nur A. Touba	Enhancing Silicon Debug via Periodic Monitoring.	DFT	2008	DBLP DOI BibTeX RDF
1	Michael T. Niemier, Michael Crocker, Xiaobo Sharon Hu	Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA.	DFT	2008	DBLP DOI BibTeX RDF
1	Julien Vial, Alberto Bosio, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Using TMR Architectures for Yield Improvement.	DFT	2008	DBLP DOI BibTeX RDF
1	Konstantin Likharev	Defect-Tolerant Hybrid CMOS/Nanoelectronic Circuits.	DFT	2008	DBLP DOI BibTeX RDF
1	Ilia Polian, Wenjing Rao	Selective Hardening of NanoPLA Circuits.	DFT	2008	DBLP DOI BibTeX RDF
1	Mahdi Fazeli, Seyed Ghassem Miremadi	A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET.	DFT	2008	DBLP DOI BibTeX RDF
1	Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi	A Tile-Based Error Model for Forward Growth of DNA Self-Assembly.	DFT	2008	DBLP DOI BibTeX RDF
1	Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz	ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.	DFT	2008	DBLP DOI BibTeX RDF
1	John E. Savage	Computing at the Nanoscale.	DFT	2008	DBLP DOI BibTeX RDF
1	Fan Yang 0060, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz	Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.	DFT	2008	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Charles Augustine, Kaushik Roy 0001	Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems.	DFT	2008	DBLP DOI BibTeX RDF
1	Zachary D. Patitz, Nohpill Park	Modeling and Evaluation of Threshold Defect Tolerance.	DFT	2008	DBLP DOI BibTeX RDF
1	Qiaoyan Yu, Paul Ampadu	Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment.	DFT	2008	DBLP DOI BibTeX RDF
1	Shubu Mukherjee	Architectural Vulnerability Factor (or, does a soft error matter?).	DFT	2008	DBLP DOI BibTeX RDF
1	Xiaojun Ma, Fabrizio Lombardi	Fault Tolerant Schemes for QCA Systems.	DFT	2008	DBLP DOI BibTeX RDF
1	Yiwen Shi, Kellie DiPalma, Jennifer Dworak	Efficient Determination of Fault Criticality for Manufacturing Test Set Optimization.	DFT	2008	DBLP DOI BibTeX RDF

Publications at "DFT"( http://dblp.L3S.de/Venues/DFT )