Search results for "FCCM"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Carlos Rodriguez-Donate, Guillermo Botella, Carlos García 0001, Eduardo Cabal-Yepez, Manuel Prieto-Matías	Early Experiences with OpenCL on FPGAs: Convolution Case Study.	FCCM	2015	DBLP DOI BibTeX RDF
1	Marco Rabozzi, Antonio Miele, Marco D. Santambrogio	Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements Detection.	FCCM	2015	DBLP DOI BibTeX RDF
1	Yu-Ting Chen, Jason Cong, Jie Lei 0001, Peng Wei 0004	A Novel High-Throughput Acceleration Engine for Read Alignment.	FCCM	2015	DBLP DOI BibTeX RDF
1	Brice Colombier, Lilian Bossuet	Functional Locking Modules for Design Protection of Intellectual Property Cores.	FCCM	2015	DBLP DOI BibTeX RDF
1		23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015, Vancouver, BC, Canada, May 2-6, 2015	FCCM	2015	DBLP BibTeX RDF
1	Luca Bochi Saldanha, Christophe Bobda	A System on Reconfigurable Chip for Handwritten Digit Recognition.	FCCM	2015	DBLP DOI BibTeX RDF
1	John W. Lockwood	Scalable Key/Value Search in Datacenters.	FCCM	2015	DBLP DOI BibTeX RDF
1	Pawel Swierczynski, Marc Fyrbiak, Christof Paar, Christophe Huriaux, Russell Tessier	Protecting against Cryptographic Trojans in FPGAs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Thiem Van Chu, Shimpei Sato, Kenji Kise	Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA.	FCCM	2015	DBLP DOI BibTeX RDF
1	Lesley Shannon, Veronica Cojocaru, Cong Nguyen Dao, Philip Heng Wai Leong	Technology Scaling in FPGAs: Trends in Applications and Architectures.	FCCM	2015	DBLP DOI BibTeX RDF
1	Azamat Mametjanov, Prasanna Balaprakash, Chekuri Choudary, Paul D. Hovland, Stefan M. Wild, Gerald Sabin	Autotuning FPGA Design Parameters for Performance and Power.	FCCM	2015	DBLP DOI BibTeX RDF
1	Jason Kane, Robert Hernandez, Qing Yang 0001	A Reconfigurable Multiclass Support Vector Machine Architecture for Real-Time Embedded Systems Classification.	FCCM	2015	DBLP DOI BibTeX RDF
1	Cheng Liu, Hayden Kwok-Hay So	Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Liucheng Guo, Ce Guo, David B. Thomas, Wayne Luk	Pipelined Genetic Propagation.	FCCM	2015	DBLP DOI BibTeX RDF
1	Mohamed W. Hassan, Ahmed E. Helal, Yasser Y. Hanafy	High Performance Sparse LU Solver FPGA Accelerator Using a Static Synchronous Data Flow Model.	FCCM	2015	DBLP DOI BibTeX RDF
1	Oriol Arcas-Abella, Adrián Cristal, Osman S. Unsal	High-Level Debugging and Verification for FPGA-Based Multicore Architectures.	FCCM	2015	DBLP DOI BibTeX RDF
1	Roger Moussalli, Mudhakar Srivatsa, Sameh W. Asaad	Fast and Flexible Conversion of Geohash Codes to and from Latitude/Longitude Coordinates.	FCCM	2015	DBLP DOI BibTeX RDF
1	Alban Bourge, Olivier Muller, Frédéric Rousseau 0001	Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems.	FCCM	2015	DBLP DOI BibTeX RDF
1	Yuteng Zhou, Wei Wang 0053, Xinming Huang 0001	FPGA Design for PCANet Deep Learning Network.	FCCM	2015	DBLP DOI BibTeX RDF
1	Paul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk	Accelerating SpMV on FPGAs by Compressing Nonzero Values.	FCCM	2015	DBLP DOI BibTeX RDF
1	Jeremy Fowers, Joo-Young Kim 0001, Doug Burger, Scott Hauck	A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Santhosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman S. Unsal, Adrián Cristal	Heterogeneous Platform to Accelerate Compute Intensive Applications.	FCCM	2015	DBLP DOI BibTeX RDF
1	Ze-ke Wang, Bingsheng He, Wei Zhang 0012	Improving Data Partitioning Performance on OpenCL-Based FPGAs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Xabier Iturbe, Didier Keymeulen, Patrick Yiu, Dan Berisford, Kevin P. Hand, Robert Carlson, Emre Ozer 0001	A Highly-Efficient, Adaptive and Fault-Tolerant SoC Implementation of a Fourier Transform Spectrometer Data Processing.	FCCM	2015	DBLP DOI BibTeX RDF
1	Jeevan Sirkunan, Chia Yee Ooi, Muhammad N. Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono	Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms.	FCCM	2015	DBLP DOI BibTeX RDF
1	Mohammed Alawad, Mingjie Lin	FIR Filter Based on Stochastic Computing with Reconfigurable Digital Fabric.	FCCM	2015	DBLP DOI BibTeX RDF
1	Dongyang Li, Qing Yang 0001, Qingbo Wang, Cyril Guyot, Ashwin Narasimha, Dejan Vucinic, Zvonimir Bandic	A Parallel and Pipelined Architecture for Accelerating Fingerprint Computation in High Throughput Data Storages.	FCCM	2015	DBLP DOI BibTeX RDF
1	Bo Peng, Xi Jin 0002, Tianqi Wang, Xueliang Du	Design of a Distributed Compressor for Astronomy SSD.	FCCM	2015	DBLP DOI BibTeX RDF
1	Sunil Shukla, David F. Bacon	Cycle-Accurate Replay and Debugging of Running FPGA Systems.	FCCM	2015	DBLP DOI BibTeX RDF
1	Bita Darvish Rouhani, Ebrahim M. Songhori, Azalia Mirhoseini, Farinaz Koushanfar	SSketch: An Automated Framework for Streaming Sketch-Based Analysis of Big Data on FPGA.	FCCM	2015	DBLP DOI BibTeX RDF
1	Behzad Salami 0001, Oriol Arcas-Abella, Nehir Sönmez	HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA.	FCCM	2015	DBLP DOI BibTeX RDF
1	Aaron Wood, Scott Hauck	Offset Pipelined Scheduling: Conditional Branching for CGRAs.	FCCM	2015	DBLP DOI BibTeX RDF
1	Heinrich Riebler, Tobias Kenter, Christian Plessl, Christoph Sorge	Reconstructing AES Key Schedules from Decayed Memory with FPGAs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Eduardo Aguilar-Pelaez, Samuel Bayliss, Alex I. Smith, Felix Winterstein, Dan R. Ghica, David B. Thomas, George A. Constantinides	Compiling Higher Order Functional Programs to Composable Digital Hardware.	FCCM	2014	DBLP DOI BibTeX RDF
1	David B. Thomas	FPGA Gaussian Random Number Generators with Guaranteed Statistical Accuracy.	FCCM	2014	DBLP DOI BibTeX RDF
1	Muhsen Owaida, Christos D. Antonopoulos, Nikolaos Bellas	A Grammar Induction Method for Clustering of Operations in Complex FPGA Designs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Girish Venkataramani, Yongfeng Gu	System-Level Retiming and Pipelining.	FCCM	2014	DBLP DOI BibTeX RDF
1	Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk	SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications.	FCCM	2014	DBLP DOI BibTeX RDF
1	Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan	Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array.	FCCM	2014	DBLP DOI BibTeX RDF
1	Pham Nam Khanh, Amit Kumar Singh 0002, Akash Kumar 0001, Khin Mi Mi Aung	Design Space Exploration to Accelerate Nelder-Mead Algorithm Using FPGA.	FCCM	2014	DBLP DOI BibTeX RDF
1	Felix Winterstein, Samuel Bayliss, George A. Constantinides	Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis.	FCCM	2014	DBLP DOI BibTeX RDF
1	Wenlai Zhao, Haohuan Fu, Guangwen Yang	A Fully-Pipelined FPGA Design for Tree-Reweighted Message Passing Algorithm.	FCCM	2014	DBLP DOI BibTeX RDF
1	Jason Cong, Hui Huang 0001, Chiyuan Ma, Bingjun Xiao, Peipei Zhou 0001	A Fully Pipelined and Dynamically Composable Architecture of CGRA.	FCCM	2014	DBLP DOI BibTeX RDF
1	Edin Kadric, Kunal Mahajan, André DeHon	Kung Fu Data Energy - Minimizing Communication Energy in FPGA Computations.	FCCM	2014	DBLP DOI BibTeX RDF
1	Shiming Li, Miaoqing Huang, Hongyuan Ding, Sen Ma	A Hierarchical Memory Architecture with NoC Support for MPSoC on FPGAs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Christophe Huriaux, Olivier Sentieys, Russell Tessier	FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions.	FCCM	2014	DBLP DOI BibTeX RDF
1	Swathi T. Gurumani, Jacob Tolar, Yao Chen 0008, Yun Liang 0001, Kyle Rupnow, Deming Chen	Integrated CUDA-to-FPGA Synthesis with Network-on-Chip.	FCCM	2014	DBLP DOI BibTeX RDF
1	Kaveh Aasaraai, Andreas Moshovos	An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor Design.	FCCM	2014	DBLP DOI BibTeX RDF
1	Fumito Yamaguchi, Hiroaki Nishi	High-Throughput and Low-Cost Hardware Accelerator for Privacy Preserving Publishing.	FCCM	2014	DBLP DOI BibTeX RDF
1	Eriko Nurvitadhi, Gabriel Weisz, Yu Wang 0110, Skand Hurkat, Marie Nguyen, James C. Hoe, José F. Martínez, Carlos Guestrin	GraphGen: An FPGA Framework for Vertex-Centric Graph Computation.	FCCM	2014	DBLP DOI BibTeX RDF
1	Jonathon Pendlum, Miriam Leeser, Kaushik R. Chowdhury	Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework.	FCCM	2014	DBLP DOI BibTeX RDF
1	Jeremy Fowers, Kalin Ovtcharov, Karin Strauss, Eric S. Chung, Greg Stitt	A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication.	FCCM	2014	DBLP DOI BibTeX RDF
1	Xiaoyin Ma, Walid A. Najjar, Amit K. Roy-Chowdhury	High-Throughput Fixed-Point Object Detection on FPGAs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Brandon Kyle Hamilton, Michael Inggs, Hayden Kwok-Hay So	Scheduling Mixed-Architecture Processes in Tightly Coupled FPGA-CPU Reconfigurable Computers.	FCCM	2014	DBLP DOI BibTeX RDF
1	Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada	Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Xinying Wang 0004, Joseph Zambreno	An Efficient Architecture for Floating-Point Eigenvalue Decomposition.	FCCM	2014	DBLP DOI BibTeX RDF
1	Young Kyu Choi, Jason Cong, Di Wu 0010	FPGA Implementation of EM Algorithm for 3D CT Reconstruction.	FCCM	2014	DBLP DOI BibTeX RDF
1	Tian Xiang, Lei Zhao, Xi Jin 0002, Tianqi Wang, Shaoping Chu, Cong Ma, Shubin Liu, Qi An, Xue Ben	A Multi-phase Clock Time-to-Digital Convertor Based on ISERDES Architecture.	FCCM	2014	DBLP DOI BibTeX RDF
1	Deheng Ye, Nachiket Kapre	MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations.	FCCM	2014	DBLP DOI BibTeX RDF
1	Marco Rabozzi, John Lillis, Marco D. Santambrogio	Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming.	FCCM	2014	DBLP DOI BibTeX RDF
1	Bajaj Ronak, Suhaib A. Fahmy	Experiments in Mapping Expressions to DSP Blocks.	FCCM	2014	DBLP DOI BibTeX RDF
1	Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer	LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories.	FCCM	2014	DBLP DOI BibTeX RDF
1	Kizheppatt Vipin, Suhaib A. Fahmy	Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq.	FCCM	2014	DBLP DOI BibTeX RDF
1	Sven Hager, Frank Winkler, Björn Scheuermann 0001, Klaus Reinhardt	Building Optimized Packet Filters with COFFi.	FCCM	2014	DBLP DOI BibTeX RDF
1	Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv	Using Multi-op Instructions as a Way to Generate ASIPs with Optimized Pipeline Structure.	FCCM	2014	DBLP DOI BibTeX RDF
1	Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima	Better-Than-DMR Techniques for Yield Improvement.	FCCM	2014	DBLP DOI BibTeX RDF
1	Edin Kadric, Kunal Mahajan, André DeHon	Energy Reduction through Differential Reliability and Lightweight Checking.	FCCM	2014	DBLP DOI BibTeX RDF
1	Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado	Fast and Power Efficient Heapsort IP for Image Compression Application.	FCCM	2014	DBLP DOI BibTeX RDF
1	Gang Chen 0023, Biao Hu 0001, Kai Huang 0001, Alois C. Knoll, Di Liu 0002	Abstract: Shared L2 Cache Management in Multicore Real-Time System.	FCCM	2014	DBLP DOI BibTeX RDF
1	Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien, Christophe Huriaux	Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes.	FCCM	2014	DBLP DOI BibTeX RDF
1	Robért Glein, Bernhard Schmidt, Florian Rittner, Jürgen Teich, Daniel Ziener	A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor.	FCCM	2014	DBLP DOI BibTeX RDF
1	Benjamin Humphries, Hansen Zhang, Jiayi Sheng, Raphael Landaverde, Martin C. Herbordt	3D FFTs on a Single FPGA.	FCCM	2014	DBLP DOI BibTeX RDF
1	Benjamin Gojman, André DeHon	GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction.	FCCM	2014	DBLP DOI BibTeX RDF
1		22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, Boston, MA, USA, May 11-13, 2014	FCCM	2014	DBLP BibTeX RDF
1	Maciej Kurek, Tobias Becker, Thomas C. P. Chau, Wayne Luk	Automating Optimization of Reconfigurable Designs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Hamed Tabkhi, Majid Sabbagh, Gunar Schirner	A Power-Efficient FPGA-Based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution.	FCCM	2014	DBLP DOI BibTeX RDF
1	Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre	Timing Fault Detection in FPGA-Based Circuits.	FCCM	2014	DBLP DOI BibTeX RDF
1	Matthew Jacobsen, Pingfan Meng, Siddarth Sampangi, Ryan Kastner	FPGA Accelerated Online Boosting for Multi-target Tracking.	FCCM	2014	DBLP DOI BibTeX RDF
1	Laurent Gantel, Mohamed El Amine Benkhelifa, François Verdier, Fabrice Lemonnier	MRAPI Implementation for Heterogeneous Reconfigurable Systems-on-Chip.	FCCM	2014	DBLP DOI BibTeX RDF
1	Stuart Byma, J. Gregory Steffan, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow	FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack.	FCCM	2014	DBLP DOI BibTeX RDF
1	Roland Christian Gamom Ngounou Ewo, Andréa Pinna 0001, Bertrand Granado, Martin Mbouenda, Hilaire Bertrand Fotsin	A Hardware MPI Spawn for Distributed Multiprocessing Reconfigurable System on Chip (MP-RSoC).	FCCM	2014	DBLP DOI BibTeX RDF
1	Brad L. Hutchings, Jared Keeley	Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Jeffrey Cassidy, Lothar Lilge, Vaughn Betz	Fast, Power-Efficient Biophotonic Simulations for Cancer Treatment Using FPGAs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Yu Tanabe, Tsutomu Maruyama	FPGA Implementation of Optical Flow Algorithm Based on Cost Aggregation.	FCCM	2014	DBLP DOI BibTeX RDF
1	Chad D. Kersey, Sudhakar Yalamanchili, Hyojong Kim, Nimit Nigania, Hyesoon Kim	Harmonica: An FPGA-Based Data Parallel Soft Core.	FCCM	2014	DBLP DOI BibTeX RDF
1	Joo-Young Kim 0001, Scott Hauck, Doug Burger	A Scalable Multi-engine Xpress9 Compressor with Asynchronous Data Transfer.	FCCM	2014	DBLP DOI BibTeX RDF
1	Umer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar	Memory Optimized Re-gridding for Non-uniform Fast Fourier Transform on FPGAs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Siddhartha 0001, Nachiket Kapre	Breaking Sequential Dependencies in FPGA-Based Sparse LU Factorization.	FCCM	2014	DBLP DOI BibTeX RDF
1	Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz	On Hard Adders and Carry Chains in FPGAs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen	Customizable Compression Architecture for Efficient Configuration in CGRAs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Hendrik Noll, Sebastian Siegert, Johannes Hiltscher, Wolfgang Rehm	UTOPIA: Generic User-Level Access to the Physical Memory Address Space for IP Core Debugging and Validation on FPGA Based PCIe Extension Cards.	FCCM	2014	DBLP DOI BibTeX RDF
1	Yanbiao Li, Dafang Zhang, Xian Yu, Jing Long, Wei Liang 0005	From GPU to FPGA: A Pipelined Hierarchical Approach to Fast and Memory-Efficient NDN Name Lookup.	FCCM	2014	DBLP DOI BibTeX RDF
1	Monther Abusultan, Sunil P. Khatri	Look-up Table Design for Deep Sub-threshold through Full-Supply Operation.	FCCM	2014	DBLP DOI BibTeX RDF
1	Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei	Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures.	FCCM	2014	DBLP DOI BibTeX RDF
1	Lu He, Yan Luo, Yu Cao 0002	Accelerator of Stacked Convolutional Independent Subspace Analysis for Deep Learning-Based Action Recognition.	FCCM	2014	DBLP DOI BibTeX RDF
1	Qingshan Tang, Matthieu Tuna, Habib Mehrez	Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling, and Custom.	FCCM	2014	DBLP DOI BibTeX RDF
1	Shuo Li 0002, Ahmed Hemani	Accurate and Efficient Three Level Design Space Exploration Based on Constraints Satisfaction Optimization Problem Solver.	FCCM	2014	DBLP DOI BibTeX RDF
1	Matthew An, J. Gregory Steffan, Vaughn Betz	Speeding Up FPGA Placement: Parallel Algorithms and Methods.	FCCM	2014	DBLP DOI BibTeX RDF
1	Di Wu, Andreas Moshovos	Image Signal Processors on FPGAs.	FCCM	2014	DBLP DOI BibTeX RDF
1	Klaus Schneider 0001, Adrian Willenbücher	A New Algorithm for Carry-Free Addition of Binary Signed-Digit Numbers.	FCCM	2014	DBLP DOI BibTeX RDF

Publications at "FCCM"( http://dblp.L3S.de/Venues/FCCM )