Search results for "Hardware"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Shengchao Qin, Zongyan Qiu, Jifeng He 0001	Constructing Hardware/Software Interface Using Protocol Converters.	APAQS	2001	DBLP DOI BibTeX RDF	protocol converter, program algebra, Hardware/software partition
21	Pun H. Shiu, Yudong Tan, Vincent John Mooney III	A novel parallel deadlock detection algorithm and architecture.	CODES	2001	DBLP DOI BibTeX RDF	parallel algorithm, hardware/software codesign, real-time operating system, deadlock detection
21	Rong Lin, Koji Nakano, Stephan Olariu, Maria Cristina Pinotti, James L. Schwing, Albert Y. Zomaya	Scalable Hardware-Algorithms for Binary Prefix Sums.	IEEE Trans. Parallel Distributed Syst.	2000	DBLP DOI BibTeX RDF	shift switching, binary prefix sums, binary counting, pipelining, scalable architectures, Hardware-algorithms
21	Annette Muth, Thomas Kolloch, Thomas Maier-Komor, Georg Färber	An Evaluation of Code Generation Strategies Targeting Hardware for the Rapid Prototyping of SDL-Specifications.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	asynchronous modeling language, decomposition strategies, level of concurrency, code generation, VHDL, rapid prototyping, SDL, implementation model, application specific hardware
21	Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang	Scalable Hardware-Algorithm for Mark-Sweep Garbage Collection.	EUROMICRO	2000	DBLP DOI BibTeX RDF	dynamic memory management algorithms, mark and sweep garbage collection, Hardware algorithms, VLSI system
21	Michael Eisenring, Jürgen Teich	Interfacing Hardware and Software.	FPL	1998	DBLP DOI BibTeX RDF	automatic interface synthesis, low power design, rapid prototyping, hardware/software codesign
21	Holger Scherl, Stefan Hoppe, Markus Kowarschik, Joachim Hornegger	Design and implementation of the software architecture for a 3-D reconstruction system in medical imaging.	ICSE	2008	DBLP DOI BibTeX RDF	hardware abstraction layer, software design and architecture, parallel programming, patterns, medical imaging, hardware acceleration, 3-d reconstruction
21	David E. Taylor, Andreas Herkersdorf, Andreas C. Döring, Gero Dittmann	Robust header compression (ROHC) in next-generation network processors.	IEEE/ACM Trans. Netw.	2005	DBLP DOI BibTeX RDF	ROHC, hardware assist, FPGA, ASIC, network processor, ASIP, reconfigurable hardware, header compression
21	Stephen A. Edwards, Olivier Tardieu	SHIM: a deterministic model for heterogeneous embedded systems.	EMSOFT	2005	DBLP DOI BibTeX RDF	deterministic model of computation, hardware/software codesign, software synthesis, hardware synthesis
21	Rusty Hunt, Gregory Hornby, Jason D. Lohn	Toward evolved flight.	GECCO	2005	DBLP DOI BibTeX RDF	flapping flight, hardware-in-the-loop evolution, ornithopter, evolutionary algorithm, evolvable hardware
21	Samir Bouaziz, Michel Fan, Roger Reynaud, Thierry Maurin	Multi-Sensors and Environment Simulator for Collision Avoidance Applications.	CAMP	2000	DBLP DOI BibTeX RDF	multisensors, environment simulator, PICAR project, Prometheus Prochip, PC hardware computer, CAN/sup 2/ network, dedicated software, AI expert system, designed environment software, physical embedded hardware, virtual world simulator, data fusion, collision avoidance, collision avoidance, real time constraints, video camera, ultrasonic sensors
21	George Baciu, Wingo Sai-Keung Wong	Rendering in object interference detection on conventional graphics workstations.	PG	1997	DBLP DOI BibTeX RDF	object interference detection, conventional graphics workstations, rasterizing graphics hardware, interference detection algorithms, graphics rendering hardware, rendering rates, animation, collision detection, complex objects, rendering (computer graphics)
21	Christian Mandl, Adolfo Fucci	A fast FPGA based coprocessor supporting hard real-time search.	EUROMICRO	1997	DBLP DOI BibTeX RDF	fast FPGA based coprocessor, hard real time search, dual port memories, programmable message driven multi port memories, sequential requests, data acquisition systems, hard real time requirements, DAC systems, coprocessor architectures, file descriptor table, implementation costs, TI DSP C40, hardware strategy, dual port memory, generic searching coprocessor, field programmable gate arrays, hardware implementation, computer systems, high throughput, searching strategy, design approach, DPMs
21	Cezary Dubnicki, Liviu Iftode, Edward W. Felten, Kai Li 0001	Software Support for Virtual Memory-Mapped Communication.	IPPS	1996	DBLP DOI BibTeX RDF	virtual memory-mapped communication, virtual address space, full protection, user-level buffer management, zero-copy protocols, software communication overhead, SHRIMP project, hardware performance, Pentium personal computer, user-to-user latency, peak hardware bandwidth, 23 MB/s, performance evaluation, software architecture, operating system, application program interfaces, application program interface, client-server systems, operating systems (computers), data transfer, network interfaces, network interfaces, communication model, virtual storage, microcomputers, data handling
21	Dimitrios Kagaris, Spyros Tragoudas	A multiseed counter TPG with performance guarantee.	ICCD	1996	DBLP DOI BibTeX RDF	built-in test pattern generators, multiseed counter test pattern generator, low hardware overhead, fast CAD tool, ISCAS'85 benchmarks, hardware/time overhead, built-in self test, performance guarantee, test set generation
21	Noé Lopez-Benitez	Dependability Modeling and Analysis of Distributed Programs.	IEEE Trans. Software Eng.	1994	DBLP DOI BibTeX RDF	program reliability, program availability, distributed computing system environment, repair actions, global repair mode, centralized repair team, system status restoration, failure state, local repair model, program interruption, Petri nets, distributed algorithms, software reliability, distributed programs, stochastic processes, programming theory, dependability analysis, system recovery, stochastic Petri nets, program diagnostics, hardware support, multiprocessing programs, program execution, file distribution, dependability modeling, hardware faults
21	A. P. Wim Böhm, John R. Gurd	Iterative Instructions in the Manchester Dataflow Computer.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	Manchester Dataflow Computer, iterative instructions, program execution times, function unit array, hardware speedup curves, fine-grain instructions, parallel programming, parallel architectures, iterative methods, parallel machines, tokens, instruction sets, instruction sets, hardware configuration
21	Laura Frigerio, Fabio Salice	A performance-oriented hardware/software partitioning for datapath applications.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	hardware/software systems, performance oriented patitioning
21	Dai Yamamoto, Jun Yajima, Kouichi Itoh	A Very Compact Hardware Implementation of the MISTY1 Block Cipher.	CHES	2008	DBLP DOI BibTeX RDF	MISTY1, Compact Implementation, Block cipher, Hardware, ASIC
21	Antonello Monti, Salvatore D'Arco, A. Deshmukh, Y. Work, Antonio Lentini	From simulation to hardware testing: a low-cost platform for power-hardware-in-the-loop experiments.	SCSC	2007	DBLP BibTeX RDF	electromechanical systems, power hardware in the loop, virtual prototyping, power electronics
21	Min Xie, Youren Wang, Li Wang, Yuan Zhang	Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit.	ICES	2007	DBLP DOI BibTeX RDF	Operator-based programmable cell circuit, FPGA, Reconfigurable computing, Reconfigurable hardware, Information processing
21	Adriano Sarmento, Lobna Kriaa, Arnaud Grasset, Mohamed-Wassim Youssef, Aimen Bouchhima, Frédéric Rousseau 0001, Wander O. Cesário, Ahmed Amine Jerraya	Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC design.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	interface design automation, service-based model, systems-on-chip, hardware/software interfaces
21	Jaehwan Lee 0002, Vincent John Mooney III	A novel deadlock avoidance algorithm and its hardware implementation.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	deadlock avoidance hardware IP design
21	Paul Kohout, Brinda Ganesh, Bruce L. Jacob	Hardware support for real-time operating systems.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	RTOS, hardware-software codesign
21	Wei Ming Lim, Mohammed Benaissa	Design space exploration of a hardware-software co-designed GF(2m) galois field processor for forward error correction and cryptography.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	GF(2m) arithmetic, forward error control coding, galois field processor, cryptography, advanced encryption standard, elliptic curve cryptography, design space exploration, Reed-Solomon code, hardware-software co-design, BCH code
21	Christophe Clavier, Jean-Sébastien Coron, Nora Dabbous	Differential Power Analysis in the Presence of Hardware Countermeasures.	CHES	2000	DBLP DOI BibTeX RDF	hardware countermeasure, random process interrupt, smart card, Power analysis
21	Laurent Freund, Denis Dupont, Michel Israël, Frédéric Rousseau 0001	Interface Optimization During Hardware-Software Partitioning.	CODES	1997	DBLP DOI BibTeX RDF	Interface Optimization, Hardware-Software Partitioning
21	Hannah Badier, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat	Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
21	Steffen Peter, Tony Givargis	Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
21	Mike Borowczak, Ranga Vemuri	S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
21	Wei Hu 0008, Armaiti Ardeshiricham, Lingjuan Wu, Ryan Kastner	Integrating Information Flow Tracking into High-Level Synthesis Design Flow.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
21	Srinivas Katkoori, Sheikh Ariful Islam	Introduction and Background.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
21	Nandeesha Veeranna, Benjamin Carrion Schafer	Source Code Obfuscation of Behavioral IPs: Challenges and Solutions.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
21	Sheikh Ariful Islam, Srinivas Katkoori	Behavioral Synthesis of Key-Obfuscated RTL IP.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
21	Matthew Lewandowski, Srinivas Katkoori	State Encoding Based Watermarking of Sequential Circuits Using Hybridized Darwinian Genetic Algorithm.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
21	S. T. Choden Konigsmark, Wei Ren, Martin D. F. Wong, Deming Chen	High-Level Synthesis for Minimizing Power Side-Channel Information Leakage.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
21	Richa Agrawal, Ranga Vemuri	Encoding of Finite-State Controllers for Graded Security and Power.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
21	Jacopo Panerati, Donatella Sciuto, Giovanni Beltrame	Optimization Strategies in Design Space Exploration.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Kees Goossens, Martijn Koedam, Andrew Nelson 0001, Shubhendu Sinha, Sven Goossens, Yonghui Li 0002, Gabriela Breaban, Reinier van Kampenhout, Rasool Tavakoli, Juan Valencia, Hadi Ahmadi Balef, Benny Akesson, Sander Stuijk, Marc Geilen, Dip Goswami, Majid Nabi	NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Peter Marwedel, Heiko Falk, Olaf Neugebauer	Memory-Aware Optimization of Embedded Software for Multiple Objectives.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Soonhoi Ha, Hanwoong Jung	HOPES: Programming Platform Approach for Embedded Systems Design.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Joachim Falk, Christian Haubelt, Jürgen Teich, Christian Zebelein	SysteMoC: A Data-Flow Programming Language for Codesign.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Ingo Sander, Axel Jantsch, Seyed-Hosein Attarzadeh-Niaki	ForSyDe: System Design Using a Functional Language and Models of Computation.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Shuoxin Lin, Yanzhou Liu 0001, Kyunghun Lee, Lin Li 0029, William Plishker, Shuvra S. Bhattacharyya	The DSPCAD Framework for Modeling and Synthesis of Signal Processing Systems.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Michael Glaß, Jürgen Teich, Martin Lukasiewycz, Felix Reimann	Hybrid Optimization Techniques for System-Level Design Space Exploration.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Santiago Pagani, Muhammad Shafique 0001, Jörg Henkel	Design Space Exploration and Run-Time Adaptation for Multicore Resource Management Under Performance and Power Constraints.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Jarmo Takala, Pekka Jääskeläinen, Teemu Pitkänen	Codesign Case Study on Transport-Triggered Architectures.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Todor P. Stefanov, Andy D. Pimentel, Hristo Nikolov	DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Tulika Mitra	Application-Specific Processors.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Rainer Leupers, Miguel Angel Aguilar, Juan Fernando Eusse, Jerónimo Castrillón, Weihua Sheng	MAPS: A Software Development Environment for Embedded Multicore Applications.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Marilyn Wolf	Embedded Computer Vision.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Wanli Chang 0001, Licong Zhang, Debayan Roy, Samarjit Chakraborty	Control/Architecture Codesign for Cyber-Physical Systems.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Chun Jason Xue	Emerging and Nonvolatile Memory.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Gunar Schirner, Andreas Gerstlauer, Rainer Dömer	SCE: System-on-Chip Environment.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Young-Hwan Park, Amin Khajeh, Jun Yong Shin, Fadi J. Kurdahi, Ahmed M. Eltawil, Nikil D. Dutt	Microarchitecture-Level SoC Design.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Santanu Sarma, Nikil D. Dutt	Architecture and Cross-Layer Design Space Exploration.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Mihai Teodor Lazarescu, Luciano Lavagno	Wireless Sensor Networks.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Mansureh Shahraki Moghaddam, Jae-Min Cho, Kiyoung Choi	Reconfigurable Architectures.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Oliver Bringmann 0001, Christoph Gerum, Sebastian Ottlik	Timing Models for Fast Embedded Software Performance Analysis.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Klaus Schneider 0001, Jens Brandt 0001	Quartz: A Synchronous Language for Model-Based Design of Reactive Embedded Systems.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Oliver Bringmann 0001, Sebastian Ottlik, Alexander Viehl	Precise Software Timing Simulation Considering Execution Contexts.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Frédéric Pétrot, Luc Michel, Clément Deschamps	Multiprocessor System-on-Chip Prototyping Using Dynamic Binary Translation.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Preeti Ranjan Panda	Memory Architectures.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Andy D. Pimentel, Peter van Stralen	Scenario-Based Design Space Exploration.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Haseeb Bokhari, Sri Parameswaran	Network-on-Chip Design.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Tim Kogel	Synopsys Virtual Prototyping for Software Development and Early Architecture Analysis.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Haibo Zeng 0001, Prachi Joshi, Daniel Thiele, Jonas Diemer, Philip Axer, Rolf Ernst, Petru Eles	Networked Real-Time Embedded Systems.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Daniel Mueller-Gritschneder, Andreas Gerstlauer	Host-Compiled Simulation.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Rainer Dömer, Guantao Liu, Tim Schmidt	Parallel Simulation.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Ali Pahlevan, Maurizio Rossi 0001, Pablo García Del Valle, Davide Brunelli, David Atienza	Joint Computing and Electric Systems Optimization for Green Datacenters.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Robin Hofmann, Leonie Ahrendts, Rolf Ernst	CPA: Compositional Performance Analysis.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
21	Andy M. Tyrrell	Fault Tolerant Applications.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
21	Andy M. Tyrrell, Martin A. Trefzer	Representations and Algorithms.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
21	Lukás Sekanina	Principles and Applications of Polymorphic Circuits.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
21	Lukás Sekanina, Zdenek Vasícek	Functional Equivalence Checking for Evolution of Complex Digital Circuits.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
21	Martin A. Trefzer	A Developmental Image Compression Technique Using Gene Regulatory Networks.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
21	Garrison W. Greenwood, Andy M. Tyrrell	Metamorphic Systems: A Schema for Adaptive Autonomous Systems.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
21	Martin A. Trefzer, Andy M. Tyrrell	Measurement and Fitness Function.	Evolvable Hardware	2015	DBLP DOI BibTeX RDF
21	Edward K. Blum	Operating Systems (OS).	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Edward K. Blum, Walter J. Savitch	The Software Side of Computer Science - Computer Programming.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Todd A. Brun	Quantum Computing.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Alfred V. Aho	Complexity Theory.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Frances A. Rosamond	Statistics of the Field.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Edward K. Blum	Introduction and Prologue.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Michael Benedikt, Pierre Senellart	Databases.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Christian Scheideler, Kalman Graffi	Programming for Distributed Computing: From Physical to Logical Networks.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Wayne Raskind, Edward K. Blum	Computer Security and Public Key Cryptography.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Shang-Hua Teng	Numerical Thinking in Algorithm Design and Analysis.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Edward K. Blum	Computation: Brief History Prior to the 1900s.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Michael R. Fellows, Serge Gaspers, Frances A. Rosamond	Multivariate Complexity Theory.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	James M. Pepin	High Performance Computing and Communication (HPCC).	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Radim Belohlávek, Rudolf Kruse, Christian Moewes	Fuzzy Logic in Computer Science.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Edward K. Blum	The Heart of Computer Science.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Fan Chung Graham, Edward K. Blum	Computer Networks.	Computer Science, The Hardware, Software and Heart of It	2011	DBLP DOI BibTeX RDF
21	Nikolaj S. Bjørner, Robert Nieuwenhuis, Helmut Veith, Andrei Voronkov (eds.)	Decision Procedures in Software, Hardware and Bioware, 18.04. - 23.04.2010	Decision Procedures in Software, Hardware and Bioware	2010	DBLP BibTeX RDF
21	Ulrich Rührmair, Heike Busch, Stefan Katzenbeisser 0001	Strong PUFs: Models, Constructions, and Security Proofs.	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF
21	Loïc Duflot, Olivier Grumelard, Olivier Levillain, Benjamin Morin	On the Limits of Hypervisor- and Virtual Machine Monitor-Based Isolation.	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF
21	François-Xavier Standaert, Olivier Pereira, Yu Yu 0001, Jean-Jacques Quisquater, Moti Yung, Elisabeth Oswald	Leakage Resilient Cryptography in Practice.	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF
21	Markus G. Kuhn	Signal Authentication in Trusted Satellite Navigation Receivers.	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF
21	Jorge Guajardo, Muhammad Asim 0007, Milan Petkovic	Towards Reliable Remote Healthcare Applications Using Combined Fuzzy Extraction.	Towards Hardware-Intrinsic Security	2010	DBLP DOI BibTeX RDF