Search results for "MRAM"

Hits ?▲	Authors	Title	Venue	Year	Link
16	Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang 0001, Youguang Zhang, Dijun Liu, Ying Wang 0001, Weisheng Zhao	Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.	ICCAD	2017	DBLP DOI BibTeX RDF
16	Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu	NoC-MRAM architecture for memory-based computing: Database-search case study.	NEWCAS	2017	DBLP DOI BibTeX RDF
16	Zhezhi He, Shaahin Angizi, Farhana Parveen, Deliang Fan	High performance and energy-efficient in-memory computing architecture based on SOT-MRAM.	NANOARCH	2017	DBLP DOI BibTeX RDF
16	Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit	A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance.	NANOARCH	2017	DBLP DOI BibTeX RDF
16	Armin Haj Aboutalebi, Lide Duan	Enabling reliable main memory using STT-MRAM via restore-aware memory management: work-in-progress.	CASES	2017	DBLP DOI BibTeX RDF
16	Kwangmyoung Rho, Kenji Tsuchida, Dongkeun Kim, Yutaka Shirai, Jihyae Bae, Tsuneo Inaba, Hiromi Noro, Hyunin Moon, Sungwoong Chung, Kazumasa Sunouchi, Jinwon Park, Kiseon Park, Akihito Yamamoto, Seoungju Chung, Hyeongon Kim, Hisato Oyamatsu, Jonghoon Oh	23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture.	ISSCC	2017	DBLP DOI BibTeX RDF
16	Takefumi Yoshikawa, Seung-Jun Bae, Leland Chang	Session 23 overview: DRAM, MRAM & DRAM interfaces.	ISSCC	2017	DBLP DOI BibTeX RDF
16	Amir Mahdi Hosseini Monazzah, Majid Shoushtari, Seyed Ghassem Miremadi, Amir M. Rahmani, Nikil D. Dutt	QuARK: Quality-configurable approximate STT-MRAM cache by fine-grained tuning of reliability-energy knobs.	ISLPED	2017	DBLP DOI BibTeX RDF
16	Farhana Parveen, Shaahin Angizi, Zhezhi He, Deliang Fan	Low power in-memory computing based on dual-mode SOT-MRAM.	ISLPED	2017	DBLP DOI BibTeX RDF
16	Zhezhi He, Shaahin Angizi, Deliang Fan	Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction.	ICCD	2017	DBLP DOI BibTeX RDF
16	Wen Wen, Youtao Zhang, Jun Yang 0002	Read Error Resilient MLC STT-MRAM Based Last Level Cache.	ICCD	2017	DBLP DOI BibTeX RDF
16	Armin Haj Aboutalebi, Lide Duan	RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read Disturbance.	ICCD	2017	DBLP DOI BibTeX RDF
16	Deliang Fan, Shaahin Angizi	Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM.	ICCD	2017	DBLP DOI BibTeX RDF
16	Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi	Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic Switching.	ICCD	2017	DBLP DOI BibTeX RDF
16	Manu Komalan, Sushil Sakhare, Trong Huynh Bao, Siddharth Rao, Woojin Kim, Christian Tenllado, José Ignacio Gómez, Gouri Sankar Kar, Arnaud Furnémont, Francky Catthoor	Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems.	ISCAS	2017	DBLP DOI BibTeX RDF
16	Artur Antonyan, Suk-Soo Pyo, Hyuntaek Jung, Gwanhyeob Koh, Taejoong Song	28-nm 1T-1MTJ 8Mb 64 I/O STT-MRAM with symmetric 3-section reference structure and cross-coupled sensing amplifier.	ISCAS	2017	DBLP DOI BibTeX RDF
16	Wang Kang 0001, Zhaohao Wang, He Zhang 0011, Sai Li, Youguang Zhang, Weisheng Zhao	Advanced Low Power Spintronic Memories beyond STT-MRAM.	ACM Great Lakes Symposium on VLSI	2017	DBLP DOI BibTeX RDF
16	Jin Yan, Dongsheng Liu, Xuecheng Zou, Bangdi Xu	A novel positive-feedback read scheme with tail current source of STT-MRAM.	ASICON	2017	DBLP DOI BibTeX RDF
16	Abhishek Chakraborty 0001, Ankit Mondal, Ankur Srivastava 0001	Correlation power analysis attack against STT-MRAM based cyptosystems.	HOST	2017	DBLP DOI BibTeX RDF
16	Saranyu Chattopadhyay, Kaustav Brahma, Arkaprova Ray, Mrigank Sharad	STT-MRAM for Low Power Access for Read-Intensive Parallel Deep-Learning Architectures.	iNIS	2017	DBLP DOI BibTeX RDF
16	Insik Yoon, Arijit Raychowdhury	Test challenges in embedded STT-MRAM arrays.	ISQED	2017	DBLP DOI BibTeX RDF
16	Seungjin Lee, Taegun Yim, Choong Keun Lee, Kyungseon Cho, Hongil Yoon	Energy-efficient write circuit in STT-MRAM based look-up table (LUT) using comparison write scheme.	ISOCC	2017	DBLP DOI BibTeX RDF
16	Nour Sayed, Fabian Oboril, Rajendra Bishnoi, Mehdi Baradaran Tahoori	Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache.	VTS	2017	DBLP DOI BibTeX RDF
16	Guohan Hu, J. J. Nowak, G. Lauer, J. H. Lee, J. Z. Sun, J. Harms, A. Annunziata, S. Brown, W. Chen, Y. H. Kim, N. Marchack, S. Murthy, Chandrasekharan Kothandaraman, Eugene J. O'Sullivan, J. H. Park, M. Reuter, R. P. Robertazzi, Philip Louis Trouilloud, Y. Zhu, Daniel Christopher Worledge	Low-current Spin Transfer Torque MRAM.	VLSI-DAT	2017	DBLP DOI BibTeX RDF
16	Massimo Alioto	STT-MRAM memories for IoT applications: Challenges and opportunities at circuit level and above.	VLSI-DAT	2017	DBLP DOI BibTeX RDF
16	Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe	Novel memory hierarchy with e-STT-MRAM for near-future applications.	VLSI-DAT	2017	DBLP DOI BibTeX RDF
16	Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi	Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics.	VDAT	2017	DBLP DOI BibTeX RDF
16	Qi Zeng 0006, Rakesh Jha, Jih-Kwon Peir	Towards Energy-Efficient Multi-Level Cell STT-MRAM Caches with Content Awareness.	PDCAT	2017	DBLP DOI BibTeX RDF
16	Guillaume Prenat, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Nathalie Lamard, Olivier Boulle, Kevin Garello, Juergen Langer, Berthold Ocker, Marie Claire Cyrille, Pietro Gambardella, Mehdi Baradaran Tahoori, Gilles Gaudin	Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.	IEEE Trans. Multi Scale Comput. Syst.	2016	DBLP DOI BibTeX RDF
16	Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001, Koji Tsunoda, Toshihiro Sugii	A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM.	IPSJ Trans. Syst. LSI Des. Methodol.	2016	DBLP DOI BibTeX RDF
16	Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori	Self-Timed Read and Write Operations in STT-MRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
16	Jianxiao Yang, Benoit Geller, Meng Li 0012, Tong Zhang 0002	An Information Theory Perspective for the Binary STT-MRAM Cell Operation Channel.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
16	Xuanyao Fong, Rangharajan Venkatesan, Dongsoo Lee, Anand Raghunathan, Kaushik Roy 0001	Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
16	Ravi Patel 0001, Xiaochen Guo, Qing Guo 0004, Engin Ipek, Eby G. Friedman	Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
16	Jianlei Yang 0001, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen 0001, Hai (Helen) Li	Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2016	DBLP DOI BibTeX RDF
16	Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié	Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
16	Elena Ioana Vatajelu, Giorgio Di Natale, Mario Barbareschi, Lionel Torres, Marco Indaco, Paolo Prinetto	STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
16	Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié, Bruno Mussard	Exploring MRAM Technologies for Energy Efficient Systems-On-Chip.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2016	DBLP DOI BibTeX RDF
16	Ashwin Chintaluri, Helia Naeimi, Suriyaprakash Natarajan, Arijit Raychowdhury	Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2016	DBLP DOI BibTeX RDF
16	Yeongkyo Seo, Kon-Woo Kwon, Xuanyao Fong, Kaushik Roy 0001	High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2016	DBLP DOI BibTeX RDF
16	Kien Trinh Quang, Sergio Ruocco, Massimo Alioto	Novel Boosted-Voltage Sensing Scheme for Variation-Resilient STT-MRAM Read.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
16	Haoyue Tang, Zhenyu Zhao, Lianhua Qu, Quan Deng, Huan Li, Wei Guo	Mitigate erroneous operations of 2T-2MTJ STT-MRAM based on dynamic voltage threshold.	IEICE Electron. Express	2016	DBLP DOI BibTeX RDF
16	Yi Ran, Kang Wang 0001, Youguang Zhang, Jacques-Olivier Klein, Weisheng Zhao	Read disturbance issue and design techniques for nanoscale STT-MRAM.	J. Syst. Archit.	2016	DBLP DOI BibTeX RDF
16	Pierre-Yves Peneau, Rabab Bouziane, Abdoulaye Gamatié, Erven Rohou, Florent Bruguier, Gilles Sassatelli, Lionel Torres, Sophiane Senni	Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs.	PATMOS	2016	DBLP DOI BibTeX RDF
16	Yousra Alkabani, Zach Koopmans, Haifeng Xu, Alex K. Jones, Rami G. Melhem	Write Pulse Scaling for Energy Efficient STT-MRAM.	ISVLSI	2016	DBLP DOI BibTeX RDF
16	Lei Jiang 0001, Wujie Wen, Danghui Wang, Lide Duan	Improving read performance of STT-MRAM based main memories through Smash Read and Flexible Read.	ASP-DAC	2016	DBLP DOI BibTeX RDF
16	Xiangteng Zang, Xin Li, Yuqing Sun 0001, Mengying Zhao, Lei Dou	Energy Optimization for Multi-level Cell STT-MRAM Using State Remapping.	HPCC/SmartCity/DSS	2016	DBLP DOI BibTeX RDF
16	Kazi Asifuzzaman, Milan Pavlovic, Milan Radulovic, David Zaragoza, Ohseong Kwon, Kyung-Chang Ryoo, Petar Radojkovic	Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC.	MEMSYS	2016	DBLP DOI BibTeX RDF
16	Liang Chang 0002, Zhaohao Wang, Yuqian Gao, Wang Kang 0001, Youguang Zhang, Weisheng Zhao	Evaluation of spin-Hall-assisted STT-MRAM for cache replacement.	NANOARCH	2016	DBLP DOI BibTeX RDF
16	Qian Shi, Zhaohao Wang, Yuqian Gao, Liang Chang 0002, Wang Kang 0001, Youguang Zhang, Weisheng Zhao	A spin Hall effect-based multi-level cell for MRAM.	NANOARCH	2016	DBLP DOI BibTeX RDF
16	He Zhang 0011, Wang Kang 0001, Tingting Pang, Weifeng Lv, Youguang Zhang, Weisheng Zhao	Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM.	NANOARCH	2016	DBLP DOI BibTeX RDF
16	Soroush Khaleghi, Paolo Vinella, Soumya Banerjee 0004, Wenjing Rao	An STT-MRAM based strong PUF.	NANOARCH	2016	DBLP DOI BibTeX RDF
16	Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura	7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.	ISSCC	2016	DBLP DOI BibTeX RDF
16	Fabian Oboril, Fazal Hameed, Rajendra Bishnoi, Ali Ahari, Helia Naeimi, Mehdi Baradaran Tahoori	Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches.	ISLPED	2016	DBLP DOI BibTeX RDF
16	Zheng Li, Xiuyuan Bi, Hai (Helen) Li, Yiran Chen 0001, Jianying Qin, Peng Guo, Wenjie Kong, Wenshan Zhan, Xiufeng Han, Hong Zhang, Lingling Wang, Guanping Wu, Hanming Wu	Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ.	ISLPED	2016	DBLP DOI BibTeX RDF
16	Mustafa M. Shihab, Jie Zhang 0048, Shuwen Gao, Josep Sloan, Myoungsoo Jung	Couture: Tailoring STT-MRAM for Persistent Main Memory.	INFLOW@OSDI	2016	DBLP BibTeX RDF
16	Jie Zhang 0048, Miryeong Kwon, Chanyoung Park, Myoungsoo Jung, Songkuk Kim	ROSS: A Design of Read-Oriented STT-MRAM Storage for Energy-Efficient Non-Uniform Cache Architecture.	INFLOW@OSDI	2016	DBLP BibTeX RDF
16	Xin Shi, Fei Wu 0005, Xidong Guan, Changsheng Xie	Error behaviors testing with temperature and magnetism dependency for MRAM.	ICCD	2016	DBLP DOI BibTeX RDF
16	Kien Trinh Quang, Sergio Ruocco, Massimo Alioto	STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling.	ISCAS	2016	DBLP DOI BibTeX RDF
16	Liuyang Zhang, Aida Todri-Sanial, Wang Kang 0001, Youguang Zhang, Lionel Torres, Yuanqing Cheng, Weisheng Zhao	Quantitative evaluation of reliability and performance for STT-MRAM.	ISCAS	2016	DBLP DOI BibTeX RDF
16	Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto	Security primitives (PUF and TRNG) with STT-MRAM.	VTS	2016	DBLP DOI BibTeX RDF
16	Insik Yoon, Ashwin Chintaluri, Arijit Raychowdhury	EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays.	ITC	2016	DBLP DOI BibTeX RDF
16	Huan Li, Zhenyu Zhao, Quan Deng, Peng Li, Haoyue Tang, Lianhua Qu	A Novel Separated Pre-discharging Sense Amplifier for STT-MRAM.	NCCET	2016	DBLP DOI BibTeX RDF
16	Shaodi Wang, Hochul Lee, Cecile Grezes, Pedram Khalili, Kang L. Wang, Puneet Gupta 0001	MTJ variation monitor-assisted adaptive MRAM write.	DAC	2016	DBLP DOI BibTeX RDF
16	Wang Kang 0001, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun 0003, Weisheng Zhao	PDS: pseudo-differential sensing scheme for STT-MRAM.	DAC	2016	DBLP DOI BibTeX RDF
16	Efrem Yuan-Fu Huang	L10-Ordered Thin Films with High Perpendicular Magnetic Anisotropy for STT-MRAM Applications.		2016	DOI RDF
16	Seunghan Lee, Kyungsu Kang, Chong-Min Kyung	Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
16	Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori	Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2015	DBLP DOI BibTeX RDF
16	Lei Jiang 0001, Bo Zhao 0007, Jun Yang 0002, Youtao Zhang	Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology.	ACM Trans. Design Autom. Electr. Syst.	2015	DBLP DOI BibTeX RDF
16	Wang Kang 0001, Liuyang Zhang, Weisheng Zhao, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona, Claude Chappert	Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2015	DBLP DOI BibTeX RDF
16	Kyungmin Kim 0003, Changsik Yoo	Variation-Tolerant Sensing Circuit for Spin-Transfer Torque MRAM.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
16	Aynaz Vatankhahghadim, W. Song, Ali Sheikholeslami	A Variation-Tolerant MRAM-Backed-SRAM Cell for a Nonvolatile Dynamically Reconfigurable FPGA.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
16	Liuyang Zhang, Wang Kang 0001, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein, Weisheng Zhao	Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM.	ISVLSI	2015	DBLP DOI BibTeX RDF
16	Jeremy Lopes, Gregory di Pendina, Eldar Zianbetov, Edith Beigné, Lionel Torres	Radiative Effects on MRAM-Based Non-Volatile Elementary Structures.	ISVLSI	2015	DBLP DOI BibTeX RDF
16	Elena Ioana Vatajelu, Giorgio Di Natale, Lionel Torres, Paolo Prinetto	STT-MRAM-Based Strong PUF Architecture.	ISVLSI	2015	DBLP DOI BibTeX RDF
16	Simon Van Beek, Koen Martens, Philippe Roussel, Gabriele Luca Donadio, Johan Swerts, Sofie Mertens, Gouri Sankar Kar, Tai Min, Guido Groeseneken	Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions.	IRPS	2015	DBLP DOI BibTeX RDF
16	Elena Ioana Vatajelu, Giorgio Di Natale, Marco Indaco, Paolo Prinetto	STT MRAM-Based PUFs.	DATE	2015	DBLP BibTeX RDF
16	Zoha Pajouhi, Xuanyao Fong, Kaushik Roy 0001	Device/circuit/architecture co-design of reliable STT-MRAM.	DATE	2015	DBLP BibTeX RDF
16	Manu Perumkunnil Komalan, Christian Tenllado, José Ignacio Gómez Pérez, Francisco Tirado Fernández, Francky Catthoor	System level exploration of a STT-MRAM based level 1 data-cache.	DATE	2015	DBLP BibTeX RDF
16	Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras	Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell.	DATE	2015	DBLP BibTeX RDF
16	Raf Appeltans, Stefan Cosemans, Praveen Raghavan, Diederik Verkest, Liesbet Van der Perre, Wim Dehaene	STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance.	NVMSA	2015	DBLP DOI BibTeX RDF
16	Yi Ran, Wang Kang 0001, Youguang Zhang, Jacques-Olivier Klein, Weisheng Zhao	Read disturbance issue for nanoscale STT-MRAM.	NVMSA	2015	DBLP DOI BibTeX RDF
16	Alessandro Grossi, Cristian Zambelli, Piero Olivo, Jérémy Alvarez-Herault, Ken Mackay	Reliability and cell-to-cell variability of TAS-MRAM arrays under cycling conditions.	NVMTS	2015	DBLP DOI BibTeX RDF
16	Alexander Makarov, Thomas Windbacher, Viktor Sverdlov, Siegfried Selberherr	SOT-MRAM based on 1Transistor-1MTJ-cell structure.	NVMTS	2015	DBLP DOI BibTeX RDF
16	Elena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras	Power-aware voltage tuning for STT-MRAM reliability.	ETS	2015	DBLP DOI BibTeX RDF
16	Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi 0001, Koji Tsunoda, Toshihiro Sugii	A negative-resistance sense amplifier for low-voltage operating STT-MRAM.	ASP-DAC	2015	DBLP DOI BibTeX RDF
16	Ashwin Chintaluri, Abhinav Parihar, Suriyaprakash Natarajan, Helia Naeimi, Arijit Raychowdhury	A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays.	ATS	2015	DBLP DOI BibTeX RDF
16	Xiaobin Liu, Tedy Thomas, Alan Boguslawski, Russell Tessier	Adaptive MRAM-based CGRAs.	FPL	2015	DBLP DOI BibTeX RDF
16	Ali Ahari, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori	Energy efficient partitioning of dynamic reconfigurable MRAM-FPGAs.	FPL	2015	DBLP DOI BibTeX RDF
16	Hongyuan Ding, Miaoqing Huang	Performance and Energy Optimization on MPSoCs by Enabling STT-MRAM LUTs.	FCCM	2015	DBLP DOI BibTeX RDF
16	Bi Wu, Yuanqing Cheng, Ying Wang 0001, Aida Todri-Sanial, Guangyu Sun 0003, Lionel Torres, Weisheng Zhao	An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.	NANOARCH	2015	DBLP DOI BibTeX RDF
16	John K. DeBrosse, Thomas M. Maffitt, Yutaka Nakamura, Guenole Jan, Po-Kang Wang	A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing.	CICC	2015	DBLP DOI BibTeX RDF
16	Jongyeon Kim, An Chen, Behtash Behin-Aein, Saurabh Kumar 0003, Jianping Wang 0006, Chris H. Kim	A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies.	CICC	2015	DBLP DOI BibTeX RDF
16	Aynaz Vatankhahghadim, Ali Sheikholeslami	A Multi-level Cell for STT-MRAM with Biaxial Magnetic Tunnel Junction.	ISMVL	2015	DBLP DOI BibTeX RDF
16	Chankyung Kim, Keewon Kwon, Chulwoo Park, Sungjin Jang, Joosun Choi	7.4 A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array.	ISSCC	2015	DBLP DOI BibTeX RDF
16	Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita	7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.	ISSCC	2015	DBLP DOI BibTeX RDF
16	Hiroaki Yoda, E. Kitagawa, Naoharu Shimomura, S. Fujita, Minoru Amano	The progresses of MRAM as a memory to save energy consumption and its potential for further reduction.	VLSIC	2015	DBLP DOI BibTeX RDF
16	Ali Ahari, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori	Improving reliability, performance, and energy efficiency of STT-MRAM with dynamic write latency.	ICCD	2015	DBLP DOI BibTeX RDF
16	Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura	Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches.	ICCD	2015	DBLP DOI BibTeX RDF
16	Kaveh Shamsi, Yu Bi, Yier Jin, Pierre-Emmanuel Gaillardon, Michael T. Niemier, Xiaobo Sharon Hu	Reliable and high performance STT-MRAM architectures based on controllable-polarity devices.	ICCD	2015	DBLP DOI BibTeX RDF