Search results for "RISC"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Miroslav N. Velev	Automatic Formal Verification of RISC-V Pipelined Microprocessors with Fault Tolerance by Spatial Redundancy at a High Level of Abstraction.	iFM	2023	DBLP DOI BibTeX RDF
13	Yichuan Gao, Ziang Liu 0015, Shanshan Li, Weidong Liu	Enhancing Evaluation and Feedback in Computer Organization Labs with an Automated RISC-V Processor Verification Framework.	FIE	2023	DBLP DOI BibTeX RDF
13	Tobias Kaiser, Friedel Gerfers	A 2.41-μW/MHz, 437-PE/mm2 CGRA in 22 nm FD-SOI With RISC-Like Code Generation.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
13	Jan Wichelmann, Christopher Peredy, Florian Sieck, Anna Pätschke, Thomas Eisenbarth 0001	MAMBO-V: Dynamic Side-Channel Leakage Analysis on RISC-V.	DIMVA	2023	DBLP DOI BibTeX RDF
13	P. Haribabu, G. V. K. Sasirekha, Madhav Rao, Jyotsna Bapat, Debabrata Das	RISC-V Core for Ethical Intelligent IoT Edge: Analysis & Design Choice.	CCGridW	2023	DBLP DOI BibTeX RDF
13	Seon Ha, Hyungon Moon	Protecting Kernel Code Integrity with PMP on RISC-V.	WISA	2023	DBLP DOI BibTeX RDF
13	Francesco Conti 0001, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini	A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing.	ISSCC	2023	DBLP DOI BibTeX RDF
13	Hyun Woo Oh, Seongmo An, Won Sik Jeong, Seung Eun Lee	RF2P: A Lightweight RISC Processor Optimized for Rapid Migration from IEEE-754 to Posit.	ISLPED	2023	DBLP DOI BibTeX RDF
13	Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram	Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU.	ISLPED	2023	DBLP DOI BibTeX RDF
13	Jung Gyu Min, Dongyun Kam, Younghoon Byun, Gunho Park, Youngjoo Lee	Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers.	ISLPED	2023	DBLP DOI BibTeX RDF
13	Bruno Sá, Francisco Marques, Manuel Rodriguez, José Martins, Sandro Pinto 0001	Holistic RISC-V Virtualization: CVA6-based SoC.	CF	2023	DBLP DOI BibTeX RDF
13	Ravi Sahita, Vedvyas Shanbhogue, Andrew Bresticker, Atul Khare, Atish Patra, Samuel Ortiz, Dylan Reid, Rajnesh Kanwal	CoVE: Towards Confidential Computing on RISC-V Platforms.	CF	2023	DBLP DOI BibTeX RDF
13	Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, Guido Masera	Implementation and integration of Keccak accelerator on RISC-V for CRYSTALS-Kyber.	CF	2023	DBLP DOI BibTeX RDF
13	Muhammad Ijaz, Fatima Saleem, Umer Shahid, Saad Waheed, Jean-Roch Coulon	Implementation and Performance Evaluation of Bit Manipulation Extension on CVA6 RISC-V.	CF	2023	DBLP DOI BibTeX RDF
13	César Fuguet Tortolero	HPDcache: Open-Source High-Performance L1 Data Cache for RISC-V Cores.	CF	2023	DBLP DOI BibTeX RDF
13	Gianluca Mittone, Nicolò Tonci, Robert Birke, Iacopo Colonnelli, Doriana Medic, Andrea Bartolini, Roberto Esposito, Emanuele Parisi, Francesco Beneventi, Mirko Polato, Massimo Torquati, Luca Benini, Marco Aldinucci	Experimenting with Emerging RISC-V Systems for Decentralised Machine Learning.	CF	2023	DBLP DOI BibTeX RDF
13	David Mallasén, Raul Murillo 0001, Alberto A. Del Barrio, Guillermo Botella, Luis Piñuel, Manuel Prieto-Matías	PERCIVAL: Deploying Posits and Quire Arithmetic into the CVA6 RISC-V Core.	CF	2023	DBLP DOI BibTeX RDF
13	Pasquale Davide Schiavone, Simone Machetti, Miguel Peón Quirós, Jose Miranda, Benoît W. Denkinger, Thomas Christoph Müller, Ruben Rodríguez, Saverio Nasturzio, David Atienza Alonso	X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller.	CF	2023	DBLP DOI BibTeX RDF
13	Cosmin-Andrei Popovici, Andrei Stan, Vasile-Ion Manta	RISC-V Extension for Optimized PWM Control.	ICSTCC	2023	DBLP DOI BibTeX RDF
13	Niko Zurstraßen, Nils Bosbach, Jan Moritz Joseph, Lukas Jünger 0001, Jan Henrik Weinstock, Rainer Leupers	Efficient RISC-V-on-x64 Floating Point Simulation.	ICCD	2023	DBLP DOI BibTeX RDF
13	David Schrammel, Moritz Waser, Lukas Lamster, Martin Unterguggenberger, Stefan Mangard	SPEAR-V: Secure and Practical Enclave Architecture for RISC-V.	AsiaCCS	2023	DBLP DOI BibTeX RDF
13	Daniel R. Mendat, Jonah P. Sengupta, Gaspar Tognetti, Martin Villemur, Philippe O. Pouliquen, Sergio Montano, Kayode Sanni, Jamal Lottier Molin, Nishant Zachariah, Isidoros Doxas, Andreas G. Andreou	A RISC-V Neuromorphic Micro-Controller Unit (vMCU) with Event-Based Physical Interface and Computational Memory for Low-Latency Machine Perception and Intelligence at the Edge.	ISCAS	2023	DBLP DOI BibTeX RDF
13	Graham Gobieski, Oguz Atli, Cagri Erbagci, Ken Mai, Nathan Beckmann, Brandon Lucia	MANIC: A $19\mu\mathrm{W}$ @ 4MHz, 256 MOPS/mW, RISC-V microcontroller with embedded MRAM main memory and vector-dataflow co-processor in 22nm bulk finFET CMOS.	ISCAS	2023	DBLP DOI BibTeX RDF
13	Jonathan Saussereau, Camille Leroux, Jean-Baptiste Bégueret, Christophe Jégo	AsteRISC: A Size-Optimized RISC-V Core for Design Space Exploration.	ISCAS	2023	DBLP DOI BibTeX RDF
13	MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David	Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference.	ISCAS	2023	DBLP DOI BibTeX RDF
13	Kai Li, Wei Yin, Qiang Liu 0011	A Portable DSP Coprocessor Design Using RISC-V Packed-SIMD Instructions.	ISCAS	2023	DBLP DOI BibTeX RDF
13	Georg Rutishauser, Robin Hunziker, Alfio Di Mauro, Sizhen Bian, Luca Benini, Michele Magno	ColibriES: A Milliwatts RISC-V Based Embedded System Leveraging Neuromorphic and Neural Networks Hardware Accelerators for Low-Latency Closed-loop Control Applications.	ISCAS	2023	DBLP DOI BibTeX RDF
13	Pegdwende Romaric Nikiema, Alessandro Palumbo, Allan Aasma, Luca Cassano, Angeliki Kritikakou, Ari Kulmala, Jari Lukkarila, Marco Ottavi, Rafail Psiakis, Marcello Traiola	Towards Dependable RISC-V Cores for Edge Computing Devices.	IOLTS	2023	DBLP DOI BibTeX RDF
13	Marcel Sarraseca, Sergi Alcaide, Francisco Fuentes, Juan Carlos Rodriguez, Feng Chang, Ilham Lasfar, Ramon Canal, Francisco J. Cazorla, Jaume Abella 0001	SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core.	IOLTS	2023	DBLP DOI BibTeX RDF
13	Seyedeh Maryam Ghasemi, Sergej Meschkov, Jonas Krautter, Dennis R. E. Gnad, Mehdi B. Tahoori	SLM ISA and Hardware Extensions for RISC-V Processors.	IOLTS	2023	DBLP DOI BibTeX RDF
13	Hardi Selg, Maksim Jenihhin, Peeter Ellervee, Jaan Raik	ML-Based Online Design Error Localization for RISC-V Implementations.	IOLTS	2023	DBLP DOI BibTeX RDF
13	Bin Zhang, Ye Cai, Zhiheng He, Sen Liang, Wei He	Structured DFT Development Approach for Chisel-Based High Performance RISC-V Processors.	ITC-Asia	2023	DBLP DOI BibTeX RDF
13	Odysseas Chatzopoulos, George Papadimitriou 0001, Wing Shek Wong, Dimitris Gizopoulos	Energy Efficiency of Out-of-Order CPUs: Comparative Study and Microarchitectural Hotspot Characterization of RISC-V Designs.	IISWC	2023	DBLP DOI BibTeX RDF
13	Yimin Gao, Sergiu Mosanu, Mohammad Nazmus Sakib, Vaibhav Verma, Xinfei Guo, Mircea Stan	LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores.	SOCC	2023	DBLP DOI BibTeX RDF
13	Daniele Rossi 0001, Nicasio Canino, Stefano Di Matteo, Sergio Saponara, Vasileios Tenentes	Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures.	SEEDA-CECNSM	2023	DBLP DOI BibTeX RDF
13	Luca Benini	From Nano-Drones to Cars - A RISC-V Open Platform for next-generation Vehicles.	IWASI	2023	DBLP DOI BibTeX RDF
13	Yanzhi Lan, Qi Hu, Gen Niu, Xinyu Li, Liangpu Wang, Fuxin Zhang	LAST: An Efficient In-place Static Binary Translator for RISC Architectures.	ICA3PP (2)	2023	DBLP DOI BibTeX RDF
13	Peiran Du, Zhaohui Cai	A Time Series Data Compression Co-processor Based on RISC-V Custom Instructions.	ICA3PP (1)	2023	DBLP DOI BibTeX RDF
13	Florian Meisel, David Volz, Christoph Spang 0001, Dat Tran, Andreas Koch 0001	TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing.	DASIP	2023	DBLP DOI BibTeX RDF
13	Sam Rogan, Yoshihito Kondo	RISC-V Is Inevitable.	ICICDT	2023	DBLP DOI BibTeX RDF
13	Yen-Fu Liu, Chou-Ying Hsieh, Sy-Yen Kuo	Boomerang: Physical-Aware Design Space Exploration Framework on RISC-V SonicBOOM Microarchitecture.	ASAP	2023	DBLP DOI BibTeX RDF
13	Shijie Jiang, Yi Zou, Hao Wang, Wanwan Li	An FFT Accelerator Using Deeply-coupled RISC-V Instruction Set Extension for Arbitrary Number of Points.	ASAP	2023	DBLP DOI BibTeX RDF
13	Joao Mario Domingos, Tiago Rocha, Nuno Neves 0002, Nuno Roma, Pedro Tomás, Leonel Sousa	Supporting RISC-V Performance Counters Through Linux Performance Analysis Tools.	ASAP	2023	DBLP DOI BibTeX RDF
13	Yifan Zhao, Honglin Kuang, Yi Sun, Zhen Yang, Chen Chen, Jianyi Meng, Jun Han 0003	Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography.	ASAP	2023	DBLP DOI BibTeX RDF
13	Manfred Schlägl, Daniel Große	GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive Graphical Application Development.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
13	Wenqiang Gong, Fang Zhou 0001, Fen Ge	A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture.	ASICON	2023	DBLP DOI BibTeX RDF
13	Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre	CIFER: Code Integrity and control Flow verification for programs Executed on a RISC-V core.	HOST	2023	DBLP DOI BibTeX RDF
13	Théophile Gousselot, Olivier Thomas, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud	Lightweight Countermeasures Against Original Linear Code Extraction Attacks on a RISC-V Core.	HOST	2023	DBLP DOI BibTeX RDF
13	Kevin Böhmer, Bruno Forlin, Carlo Cazzaniga, Paolo Rech, Gianluca Furano, Nikolaos Alachiotis 0001, Marco Ottavi	Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs.	DFT	2023	DBLP DOI BibTeX RDF
13	Carolina Imianosky, Douglas A. dos Santos, Douglas R. Melo, Felipe Viel, Luigi Dilillo	Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit.	DFT	2023	DBLP DOI BibTeX RDF
13	Douglas A. dos Santos, André Martins Pio de Mattos, Douglas R. Melo, Luigi Dilillo	Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments.	DFT	2023	DBLP DOI BibTeX RDF
13	Benjamin W. Mezger, Douglas A. dos Santos, Luigi Dilillo, Douglas R. Melo	Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip.	DFT	2023	DBLP DOI BibTeX RDF
13	Utsav Banerjee	Energy-Efficient Cryptographic Acceleration using Hardware-Software Co-Design with RISC-V.	iSES	2023	DBLP DOI BibTeX RDF
13	Keerthija Puli, Vikramkumar Pudi	Design of Low Power ALU for RISC-VISA.	iSES	2023	DBLP DOI BibTeX RDF
13	Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler	Polynomial Formal Verification of a Processor: A RISC-V Case Study.	ISQED	2023	DBLP DOI BibTeX RDF
13	Luo Jiahui, Tomoyuki Morimoto, Tadahiro Ogita, Ryota Kawamata, Zi-Ming Wang, Toshiyuki Tsutsumi	Microprocessor Instruction Design Tool for RISC-V Architecture.	ISCIT	2023	DBLP DOI BibTeX RDF
13	Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr 0001, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich	A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI.	ISOCC	2023	DBLP DOI BibTeX RDF
13	Md. Ashraful Islam, Kenji Kise	Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators.	HEART	2023	DBLP DOI BibTeX RDF
13	Kuan-Lin Chiu, Guy Eichler, Biruk B. Seyoum, Luca P. Carloni	EigenEdge: Real-Time Software Execution at the Edge with RISC-V and Hardware Accelerators.	CPS-IoT Week Workshops	2023	DBLP DOI BibTeX RDF
13	Xing Liu 0002, Qing Wang, Wenjie Zhu, Xinyi Zhang, Menglin Chen	Teaching Reform to Computer System Fundamentals (RISC-V Version) for Developing Students' Computer System Capabilities.	ICCSE (2)	2023	DBLP DOI BibTeX RDF
13	Hadrien Barral, Georges-Axel Jaloyan, David Naccache	Emoji shellcoding in RISC-V.	SP (Workshops)	2023	DBLP DOI BibTeX RDF
13	Ba-Anh Dao, Ngoc-Quynh Nguyen, Chung-Tien Nguyen	A High-Throughput and Compact GOST-28147-89 Accelerator for RISC-V System-on-Chip.	KSE	2023	DBLP DOI BibTeX RDF
13	Abbas Haghi, Lluc Alvarez, Jordi Fornt, Juan Miguel De Haro Ruiz, Roger Figueras, Max Doblas, Santiago Marco-Sola, Miquel Moretó	WFAsic: A High-Performance ASIC Accelerator for DNA Sequence Alignment on a RISC-V SoC.	ICPP	2023	DBLP DOI BibTeX RDF
13	Seyedeh Maryam Ghasemi, Sergej Meschkov, Jonas Krautter, Dennis R. E. Gnad, Mehdi B. Tahoori	Enabling In-Field Parametric Testing for RISC-V Cores.	ITC	2023	DBLP DOI BibTeX RDF
13	Patrick Diehl, Gregor Daiß, Steven R. Brandt, Alireza Kheirkhahan, Hartmut Kaiser, Christopher Taylor, John Leidel	Evaluating HPX and Kokkos on RISC-V using an astrophysics application Octo-Tiger.	SC Workshops	2023	DBLP DOI BibTeX RDF
13	Pablo Vizcaino, Georgios Ieronymakis, Nikolaos Dimou, Vassilis Papaefstathiou, Jesús Labarta, Filippo Mantovani	Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V.	SC Workshops	2023	DBLP DOI BibTeX RDF
13	Sonia Rani Gupta, Nikela Papadopoulou, Miquel Pericàs	Challenges and Opportunities in the Co-design of Convolutions and RISC-V Vector Processors.	SC Workshops	2023	DBLP DOI BibTeX RDF
13	Francisco D. Igual, Luis Piñuel, Sandra Catalán, Héctor Martínez, Adrián Castelló 0001, Enrique S. Quintana-Ortí	Automatic Generation of Micro-kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors.	SC Workshops	2023	DBLP DOI BibTeX RDF
13	Daniel Weaver, Simon McIntosh-Smith	An Empirical Comparison of the RISC-V and AArch64 Instruction Sets.	SC Workshops	2023	DBLP DOI BibTeX RDF
13	Ankita Tiwari, Prithwijit Guha, Gaurav Trivedi, Nitesh Gupta, Navneeth Jayaraj, Jan Pidanic	IndiRA: Design and Implementation of a Pipelined RISC-V Processor.	RADIOELEKTRONIKA	2023	DBLP DOI BibTeX RDF
13	Sajin S, Shubham Sunil Garag, Anuj Phegade, Deepshikha Gusain, Kuruvilla Varghese	Design of a Multi-Core Compatible Linux Bootable 64-bit Out-of-Order RISC-V Processor Core.	VLSID	2023	DBLP DOI BibTeX RDF
13	Francesco Barchi, Giacomo Pasini, Emanuele Parisi, Giuseppe Tagliavini, Andrea Bartolini, Andrea Acquaviva	RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper).	PARMA-DITAM	2023	DBLP DOI BibTeX RDF
13	Francesco Lumpp, Francesco Barchi, Andrea Acquaviva, Nicola Bombieri	On the Containerization and Orchestration of RISC-V architectures for Edge-Cloud computing.	eSAAM	2023	DBLP DOI BibTeX RDF
13	David Castells-Rufas, Xavier Martorell, Aleix Roca, Alexander Kropotov, Xavier Teruel, Teresa Cervero, John D. Davis	Ethernet Emulation over PCIe for RISC-V Software Development Vehicles.	DCIS	2023	DBLP DOI BibTeX RDF
13	Lorién López-Villellas, Esteve Pineda-Sánchez, Asaf Badouh, Santiago Marco-Sola, Pablo Ibáñez, Jesús Alastruey-Benedé, Miquel Moretó	RISC-V for Genome Data Analysis: Opportunities and Challenges.	DCIS	2023	DBLP DOI BibTeX RDF
13	Apurba Karmakar, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Piedad Brox	HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip.	DCIS	2023	DBLP DOI BibTeX RDF
13	Max Doblas, Gerard Candón, Xavier Carril, Marc Domínguez, Enric Erra, Alberto González 0004, César Hernández, Víctor Jiménez, Vatistas Kostalampros, Rubén Langarita, Neiel Leyva, Guillem López-Paradís, Jonnatan Mendoza, Josep Oltra, Julián Pavón, Cristóbal Ramírez, Narcís Rodas, Enrico Reggiani, Mario Rodríguez, Carlos Rojas, Abraham Ruiz, Hugo Safadi, Víctor Soria 0001, Alejandro Suanes, Iván Vargas, Fernando Arreza, Roger Figueras, Pau Fontova-Musté, Joan Marimon, Ricardo Martínez, Sergio Moreno, Jordi Sacristán, Oscar Alonso, Xavier Aragonès, Adrián Cristal, Ángel Diéguez, Manuel López, Diego Mateo, Francesc Moll, Miquel Moretó, Oscar Palomar, Marco A. Ramírez, Francisco Serra-Graells, Nehir Sönmez, Lluís Terés, Osman S. Unsal, Mateo Valero, Luis Villa	Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology.	DCIS	2023	DBLP DOI BibTeX RDF
13	Jiaming Zhang, Jiahao Lu, Dongsheng Liu, Aobo Li, Xiang Li, Shuo Yang, Ang Hu, Xuecheng Zou	Flexible and Efficient Implementation of CRYSTALS-KYBER SIMD RISC-V Coprocessor Based on Customized Vector Instruction-Set Extension.	A-SSCC	2023	DBLP DOI BibTeX RDF
13	Jimin Lee, Jae Min Kim, Junho Huh, Jungwoo Kim 0001	Software-driven Debug Framework for Embedded RISC-V, that Transparently Emulates the Industry Standard Debug Framework.	ICCE	2023	DBLP DOI BibTeX RDF
13	Michael A. Doran, Nabeeh Kandalaft	Embedded Virtualization on RISC-V with seL4.	UEMCON	2023	DBLP DOI BibTeX RDF
13	Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Cooper, Hyesoon Kim	Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs.	ASPLOS (3)	2023	DBLP DOI BibTeX RDF
13	Seunghyun Lee, Jeik Choi, Seock-Hwan Noh, Jahyun Koo 0002, Jaeha Kung	DBPS: Dynamic Block Size and Precision Scaling for Efficient DNN Training Supported by RISC-V ISA Extensions.	DAC	2023	DBLP DOI BibTeX RDF
13	Xinchao Zhong, Chiu-Wing Sham	A RISC-V Based SoC with Configurable CPK Sensor Interface for ECU on Motorcycle.	GCCE	2023	DBLP DOI BibTeX RDF
13	Jia-Yu Li, Yi-Kai Chen, Wai-Chi Fang	An Edge AI Accelerator Design Based on LRCN Model for Real-time EEG-based Emotion Detection System on the RISC-V FPGA Platform.	GCCE	2023	DBLP DOI BibTeX RDF
13	Giorgos Dimitrakopoulos, E. Kallitsounakis, Z. Takakis, A. Stefanidis, Chrysostomos Nicopoulos	Multi-Armed Bandits for Autonomous Test Application in RISC-V Processor Verification.	MOCAST	2023	DBLP DOI BibTeX RDF
13	Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha 0001, Frank Sill Torres, Rolf Drechsler	Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core.	COINS	2023	DBLP DOI BibTeX RDF
13	Mehrdad Poorhosseini	A hybrid RISC-V architecture supporting mixed timing-critical and high performance workloads.		2023	RDF
13	Kenny Dow	Memory Safety Acceleration on RISC-V for C Programming Language.		2023	RDF
13	Mostafa Khamis, Sameh El-Ashry, Mohamed Abdelsalam, M. Watheq El-Kharashi, Ahmed Shalaby 0001	Emulation and verification framework for MPSoC based on NoC and RISC-V.	Des. Autom. Embed. Syst.	2022	DBLP DOI BibTeX RDF
13	Yu-Ling He, Yang Wang, Hong-Chun Jiang, Peng Gao, Xinghua Yuan, David Gerada, Xiang-Yu Liu	A Novel Universal Model Considering SAGE for MFD-Based Faulty Property Analysis Under RISC in Synchronous Generators.	IEEE Trans. Ind. Electron.	2022	DBLP DOI BibTeX RDF
13	Colin Schmidt 0001, John Charles Wright, Zhongkai Wang, Eric Chang, Albert J. Ou, Woorham Bae, Sean Huang, Vladimir M. Milovanovic, Anita Flynn, Brian C. Richards, Krste Asanovic, Elad Alon, Borivoje Nikolic	An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
13	Görkem Nisanci, Paul G. Flikkema, Tolga Yalçin	Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms.	Cryptogr.	2022	DBLP DOI BibTeX RDF
13	Donald E. Owen, Jithin Joseph, Jim Plusquellic, Tom J. Mannos, Brian Dziki	Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor.	Cryptogr.	2022	DBLP DOI BibTeX RDF
13	Neil Adit, Adrian Sampson	Performance Left on the Table: An Evaluation of Compiler Autovectorization for RISC-V.	IEEE Micro	2022	DBLP DOI BibTeX RDF
13	David R. Ditzel	Accelerating ML Recommendation With Over 1, 000 RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip.	IEEE Micro	2022	DBLP DOI BibTeX RDF
13	Ruohua Shi, Wenyao Wang, Zhixuan Li, Liuyuan He, Kaiwen Sheng, Lei Ma 0008, Kai Du, Tingting Jiang 0001, Tiejun Huang 0001	U-RISC: An Annotated Ultra-High-Resolution Electron Microscopy Dataset Challenging the Existing Deep Learning Algorithms.	Frontiers Comput. Neurosci.	2022	DBLP DOI BibTeX RDF
13	Gianfranco Mariotti, Roberto Giorgi	WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool.	SoftwareX	2022	DBLP DOI BibTeX RDF
13	Hyeokdong Kwon, Hyunjun Kim, Siwoo Eum, Minjoo Sim, Hyunji Kim, Wai-Kong Lee, Zhi Hu, Hwajeong Seo	Optimized Implementation of SM4 on AVR Microcontrollers, RISC-V Processors, and ARM Processors.	IEEE Access	2022	DBLP DOI BibTeX RDF
13	Benjamin W. Mezger, Douglas A. dos Santos, Luigi Dilillo, Cesar A. Zeferino, Douglas R. Melo	A Survey of the RISC-V Architecture Software Support.	IEEE Access	2022	DBLP DOI BibTeX RDF
13	Daniel J. Koranek, Scott R. Graham, Brett J. Borghetti, Wayne C. Henry	Identification of Return-Oriented Programming Attacks Using RISC-V Instruction Trace Data.	IEEE Access	2022	DBLP DOI BibTeX RDF