Search results for "ReConFig"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Wei He 0015, Andrés Otero, Eduardo de la Torre, Teresa Riesgo	Automatic generation of identical routing pairs for FPGA implemented DPL logic.	ReConFig	2012	DBLP DOI BibTeX RDF
1	Eric Sivertson	Keynote 2 - "Reconfigurable Computing and Trust: Foundational technologies to enable trusted reconfigurable platforms".	ReConFig	2012	DBLP DOI BibTeX RDF
1	Victor Silva 0001, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto	A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory.	ReConFig	2012	DBLP DOI BibTeX RDF
1	Nikolaos Alachiotis 0001, Simon A. Berger, Alexandros Stamatakis	A versatile UDP/IP based PC ↔ FPGA communication platform.	ReConFig	2012	DBLP DOI BibTeX RDF
1	Andres Upegui, Julien Izui, Gilles Curchod	Fault mitigation by means of dynamic partial reconfiguration of Virtex-5 FPGAs.	ReConFig	2012	DBLP DOI BibTeX RDF
1	Marc Reichenbach, Ralf Seidler, Dietmar Fey	Heterogeneous computer architectures: An image processing pipeline for optical metrology.	ReConFig	2012	DBLP DOI BibTeX RDF
1	Grant Martin	Keynote 1 - The once and future FPGA: The confluence of configurable processing and reconfigurable technology.	ReConFig	2012	DBLP DOI BibTeX RDF
1	Frederik Grüll, Michael Kunz, Michael Hausmann, Udo Kebschull	An implementation of 3D Electron Tomography on FPGAs.	ReConFig	2012	DBLP DOI BibTeX RDF
1	Uli Kretzschmar, Armando Astarloa, Jesús Lázaro 0001, Mikel Garay, Javier Del Ser	Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA.	ReConFig	2012	DBLP DOI BibTeX RDF
1	Michael Schmidt 0004, Dietmar Fey	Akers's wavefront planner - One of the fastest stencil-based path planners on FPGAs.	ReConFig	2012	DBLP DOI BibTeX RDF
1	Uli Kretzschmar, Armando Astarloa, Jesús Lázaro 0001, Unai Bidarte, Jaime Jimenez	Robustness Analysis of Different AES Implementations on SRAM Based FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Thomas Schweizer, Philipp Schlicker, Sven Eisenhardt, Tommy Kuhn, Wolfgang Rosenstiel	Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Patrick S. Ostler, Michael J. Wirthlin, Joshua E. Jensen	FPGA Bootstrapping on PCIe Using Partial Reconfiguration.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Xabier Iturbe, Khaled Benkrid, Ali Ebrahim, Chuan Hong, Tughrul Arslan, Imanol Martinez	Snake: An Efficient Strategy for the Reuse of Circuitry and Partial Computation Results in High-Performance Reconfigurable Computing.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Luis Andrés Cardona, Jharna Agrawal, Yi Guo, Joan Oliver, Carles Ferrer 0001	Performance-Area Improvement by Partial Reconfiguration for an Aerospace Remote Sensing Application.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Peter M. Athanas, Jürgen Becker 0001, René Cumplido (eds.)	2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011	ReConFig	2011	DBLP BibTeX RDF
1	Alexander Pacholik, Johannes Klöckner, Marcus Müller 0002, Irina Gushchina, Wolfgang Fengler 0001	LiSARD: LabVIEW Integrated Softcore Architecture for Reconfigurable Devices.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Benjamin Thielmann, Thorsten Wink, Jens Huthmann, Andreas Koch 0001	RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive Computers.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Alexander Pacholik, Marcus Müller 0002, Wolfgang Fengler 0001, Torsten Machleidt, Karl-Heinz Franke	GPU vs FPGA: Example Application on White Light Interferometry.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Zoltan Endre Rakosi, Zheng Wang 0020, Anupam Chattopadhyay	Adaptive Energy-Efficient Architecture for WCDMA Channel Estimation.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Neal Oliver, Rahul R. Sharma, Stephen Chang 0003, Bhushan Chitlur, Elkin Garcia, Joseph Grecco, Aaron Grier, Nelson Ijih, Yaping Liu, Pratik Marolia, Henry Mitchel, Suchit Subhaschandra, Arthur Sheiman, Tim Whisonant, Prabhat Gupta	A Reconfigurable Computing System Based on a Cache-Coherent Fabric.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Naveed Imran, Ronald F. DeMara	Heterogeneous Concurrent Error Detection (hCED) Based on Output Anticipation.	ReConFig	2011	DBLP DOI BibTeX RDF
1	John Aylward, Catherine H. Crawford, Ken Inoue, Scott Lekuch, Kay Müller, Mark Nutter, Hartmut Penner, Kai Schleupen, Jimi Xenidis	Reconfigurable Systems and Flexible Programming for Hardware Design, Verification and Software Enablement for System-on-a-Chip Architectures.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Carl Ahlberg, Jörgen Lidholm, Fredrik Ekstrand, Giacomo Spampinato, Mikael Ekström, Lars Asplund	GIMME - A General Image Multiview Manipulation Engine.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Kazuei Hironaka, Hideharu Amano	Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Hanaa M. Hussain, Khaled Benkrid, Ahmet T. Erdogan, Huseyin Seker	Highly Parameterized K-means Clustering on FPGAs: Comparative Results with GPPs and GPUs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada	Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Elif Bilge Kavun, Tolga Yalçin	RAM-Based Ultra-Lightweight FPGA Implementation of PRESENT.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Surya Narayanan, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis	Hardware OS Communication Service and Dynamic Memory Management for RSoCs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Suvarna Mane, Lyndon Judge, Patrick Schaumont	An Integrated Prime-Field ECDLP Hardware Accelerator with High-Performance Modular Arithmetic Units.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Bernhard Jungk, Jürgen Apfelbeck	Area-Efficient FPGA Implementations of the SHA-3 Finalists.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Michael Schaeferling, Gundolf Kiefer	Object Recognition on a Chip: A Complete SURF-Based System on a Single FPGA.	ReConFig	2011	DBLP DOI BibTeX RDF
1	João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira	From Instruction Traces to Specialized Reconfigurable Arrays.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Teresa Cervero, Sebastián López, Roberto Sarmiento, Tannous Frangieh, Peter Athanas	Scalable Models for Autonomous Self-Assembled Reconfigurable Systems.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Andrew G. Schmidt, Ron Sass	Improving FPGA Design and Evaluation Productivity with a Hardware Performance Monitoring Infrastructure.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Wei He 0015, Eduardo de la Torre, Teresa Riesgo	A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Lu Sun, Hoang Le, Viktor K. Prasanna	Optimizing Decomposition-Based Packet Classification Implementation on FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Dimitris Bekiaris, George Economakos, Efstathios Sotiriou-Xanthopoulos, Dimitrios Soudris	Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Ameer Abdelhadi, Guy G. F. Lemieux	Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Naveed Imran, Ronald F. DeMara	A Self-Configuring TMR Scheme Utilizing Discrepancy Resolution.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Tobias Becker, Qiwei Jin, Wayne Luk, Stephen Weston	Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Drausio Linardi Rossi, Vanderlei Bonato, Eduardo Marques, João Miguel Gago Pontes de Brito Lima	A PID Controller Applied to the Gain Control of a CMOS Camera Using Reconfigurable Computing.	ReConFig	2011	DBLP DOI BibTeX RDF
1	R. Zarate-Martïnez, Fernando Peña-Campos, J. Vazquez Castillo, Ramón Parra-Michel	Arbitrary Distribution Random Variable Generator for Channel Emulators.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Eduardo Romero-Aguirre, Ramón Parra-Michel, Roberto Carrasco-Alvarez, Aldo G. Orozco-Lugo	Architecture Based on Array Processors for Data-Dependent Superimposed Training Channel Estimation.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Jose Hugo Barron-Zambrano, César Torres-Huitzil, Jose Juan Garcia-Hernandez	FPGA-based CPG Robot Locomotion Modulation Using a Fuzzy Scheme and Visual Information.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Olivier Serres, Vikram K. Narayana, Tarek A. El-Ghazawi	An Architecture for Reconfigurable Multi-core Explorations.	ReConFig	2011	DBLP DOI BibTeX RDF
1	J. C. Peña-Ramos, Ramón Parra-Michel	Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Diana Göhringer, Lukas Meder, Michael Hübner 0001, Jürgen Becker 0001	Adaptive Multi-client Network-on-Chip Memory.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Antony W. Savich, Medhat Moussa	Resource Efficient Arithmetic Effects on RBM Neural Network Solution Quality Using MNIST.	ReConFig	2011	DBLP DOI BibTeX RDF
1	João Bispo, João M. P. Cardoso	Techniques for Dynamically Mapping Computations to Coprocessors.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Ahmad Salman, Marcin Rogawski, Jens-Peter Kaps	Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Rubén Salvador, Andrés Otero, Javier Mora 0001, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo	Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Azadeh Nazemi, Cesar Ortega-Sanchez, Iain Murray 0002	Digital Talking Book Player for the Visually Impaired Using FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro	EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Malte Baesler, Sven-Ole Voigt, Thomas Teufel	FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Chuan Hong, Imanol Martinez	Empty Resource Compaction Algorithms for Real-Time Hardware Tasks Placement on Partially Reconfigurable FPGAs Subject to Fault Ocurrence.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Hamed Sajjadi Kia, Cristinel Ababei	Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Cesar Ortega-Sanchez	MiniMIPS: An 8-Bit MIPS in an FPGA for Educational Purposes.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Pedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García	Analysis of Parallel Sorting Algorithms in K-best Sphere-Decoder Architectures for MIMO Systems.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Mieczyslaw Jessa, Lukasz Matuszewski	Enhancing the Randomness of a Combined True Random Number Generator Based on the Ring Oscillator Sampling Method.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Thomas Feller 0002, Sunil Malipatlolla, Michael Kasper, Sorin A. Huss	dcTPM: A Generic Architecture for Dynamic Context Management.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Thilo Pionteck, Christoph Osterloh, Carsten Albrecht	Linking Formal Description and Simulation of Runtime Reconfigurable Systems.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Michal Varchola, Tim Güneysu, Oliver Mischke	MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processor.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Adriano K. Sanches, João M. P. Cardoso, Alexandre C. B. Delbem	Identifying Merge-Beneficial Software Kernels for Hardware Implementation.	ReConFig	2011	DBLP DOI BibTeX RDF
1	German Leon, Germán Fabregat, José M. Claver	Automatic Type Inference for Resynthesis on Hardware Description Languages.	ReConFig	2011	DBLP DOI BibTeX RDF
1	L. R. Vela-Garcia, J. Vazquez Castillo, Ramón Parra-Michel, Alejandro Castillo Atoche	High-Speed Stochastic Processes Generator Based on Sum-of-Sinusoids for Channel Emulation.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Zhilei Chai, Jianbo Shi	Improving KLT in Embedded Systems by Processing Oversampling Video Sequence in Real-Time.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Rémi Busseuil, Lyonel Barthe, Gabriel Marchesan Almeida, Luciano Ost, Florent Bruguier, Gilles Sassatelli, Pascal Benoit, Michel Robert, Lionel Torres	Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Yun Qu, Yi-Hua E. Yang, Viktor K. Prasanna	Multi-stream Regular Expression Matching on FPGA.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Luis Manuel Ledesma-Carrillo, Eduardo Cabal-Yepez, René de Jesús Romero-Troncoso, Arturo Garcia-Perez, Roque Alfredo Osornio-Rios, Tobia D. Carozzi	Reconfigurable FPGA-Based Unit for Singular Value Decomposition of Large m x n Matrices.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Dongdong Chen, Mihai Sima	Fixed-Point CORDIC-Based QR Decomposition by Givens Rotations on FPGA.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Rafael A. Arce-Nazario, José R. Ortiz-Ubarri	Enumeration of Costas Arrays Using GPUs and FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Karl Pereira, Peter Athanas, Heshan Lin, Wu Feng 0001	Spectral Method Characterization on FPGA and GPU Accelerators.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger	Efficient Dual-Rail Implementations in FPGA Using Block RAMs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Guillermo Conde, Gregory W. Donohoe	Reconfigurable Block Floating Point Processing Elements in Virtex Platforms.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton	Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Alberto Nannarelli	FPGA Based Acceleration of Decimal Operations.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Michael Hübner 0001, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker 0001	Dynamic Processor Reconfiguration.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Moinuddin Sayed, Phillip H. Jones	Characterizing Non-ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-Based Thermometers.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Marcus R. Perrett, Izzat Darwazeh	A Simple Ethernet Stack Implementation in VHDL to Enable FPGA Logic Reconfigurability.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Jacob Couch, Peter Athanas	An Analysis of Implanted Antennas in Xilinx FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Christian de Schryver, Ivan Shcherbakov, Frank Kienle, Norbert Wehn, Henning Marxen, Anton Kostiuk, Ralf Korn	An Energy Efficient FPGA Accelerator for Monte Carlo Option Pricing with the Heston Model.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Ye Lu 0003, John V. McCanny, Sakir Sezer	The Impact of Global Routing on the Performance of NoCs in FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh	Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Hui Zhu, Sébastien Le Beux, Nataliya Yakymets, Ian O'Connor	Using Self-Reconfiguration to Increase Manufacturing Yield of CNTFET-based Architectures.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Benno Lomb, Tim Güneysu	Decrypting HDCP-protected Video Streams Using Reconfigurable Hardware.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Cuautëmoc Chävez Corona, Edgar Ferrer Moreno, Francisco Rodríguez-Henríquez	Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing Bilinear Pairings.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Mark G. Arnold	Configuring Field-Programmable Robot Arrays.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Malèk Channoufi, Pierre Lecoy, Rabah Attia, Bruno Delacressonniere, S. Garcia	Toward All Optical Interconnections in Chip Multiprocessor (2).	ReConFig	2011	DBLP DOI BibTeX RDF
1	Rizwan A. Ashraf, Ouns Mouri, Rami Jadaa, Ronald F. DeMara	Design-for-Diversity for Improved Fault-Tolerance of TMR Systems on FPGAs.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Markus Happe, Andreas Agne, Christian Plessl	Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Pei Liu 0003, Fatemeh O. Ebrahim, Ahmed Hemani, Kolin Paul	A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade	Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Lennin C. Yllescas-Calderon, Adrian J. Espino-Orozco, Ramón Parra-Michel, Luis Fernando González Pérez	Design and Implementation of a Simplified Turbo Decoder for 3GPP2.	ReConFig	2011	DBLP DOI BibTeX RDF
1	David M. Webster, Marcin Lukowiak	Versatile FPGA Architecture for Skein Hashing Algorithm.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Piotr Stepien, John Cobb	Configuration Sharing Optimized Placment and Routing.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Ouiza Dahmoune, Robert de B. Johnston	Applying Model-Checking to Post-Silicon-Verification: Bridging the Specification-Realisation Gap.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Francisco J. Quiles 0002, Manuel Ortiz, María Brox, Carlos Diego Moreno-Moreno, Javier Hormigo, Julio Villalba	UCORE: Reconfigurable Platform for Educational Purposes.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Andrew G. Schmidt, William V. Kritikos, Ron Sass, Erik K. Anderson, Matthew French	Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core Systems on a Programmable Chip.	ReConFig	2010	DBLP DOI BibTeX RDF
1	Julien Francq, Céline Thuillet	Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results.	ReConFig	2010	DBLP DOI BibTeX RDF

Publications at "ReConFig"( http://dblp.L3S.de/Venues/ReConFig )