Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Samuel Presa Toledo, Alexandra L. Zimpeck, Ricardo Reis 0001, Cristina Meinhardt |
Impact of schmitt trigger inverters on process variability robustness of 1-Bit full adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, Batumi, Georgia, December 5-8, 2017, pp. 290-293, 2017, IEEE, 978-1-5386-1911-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Mario Osta, Ali Ibrahim, Hussein Chible, Maurizio Valle |
Approximate Multipliers Based on Inexact Adders for Energy Efficient Data Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NGCAS ![In: New Generation of CAS, NGCAS 2017, Genova, Italy, September 6-9, 2017, pp. 125-128, 2017, IEEE, 978-1-5090-6447-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Marta Franceschi, Vincent Camus, Ali Ibrahim, Christian C. Enz, Maurizio Valle |
Approximate FPGA Implementation of CORDIC for Tactile Data Processing Using Speculative Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NGCAS ![In: New Generation of CAS, NGCAS 2017, Genova, Italy, September 6-9, 2017, pp. 41-44, 2017, IEEE, 978-1-5090-6447-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Subhendu Roy, Yuzhe Ma, Jin Miao, Bei Yu 0001 |
A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017, pp. 1-6, 2017, IEEE, 978-1-5090-6023-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Shahrzad Keshavarz, Daniel E. Holcomb |
Privacy leakages in approximate adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Darjn Esposito, Davide De Caro, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo |
On the use of approximate adders in carry-save multiplier-accumulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Mengting Li, Wenhao Sun, Zhimin Lu, Song Chen 0001, Feng Wu |
Memristor-based material implication logic design for full adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 271-274, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | H. Junqi, T. Nandha Kumar, Haider Abbas, Fabrizio Lombardi |
Simulation-based evaluation of frequency upscaled operation of exact/approximate ripple carry adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Cambridge, United Kingdom, October 23-25, 2017, pp. 1-6, 2017, IEEE Computer Society, 978-1-5386-0362-8. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Muhammad Kamran Ayub, Osman Hasan, Muhammad Shafique 0001 |
Statistical Error Analysis for Low Power Approximate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017, pp. 75:1-75:6, 2017, ACM, 978-1-4503-4927-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Muhammad Abdullah Hanif, Rehan Hafiz, Osman Hasan, Muhammad Shafique 0001 |
QuAd: Design and Analysis of Quality-Area Optimal Low-Latency Approximate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017, pp. 42:1-42:6, 2017, ACM, 978-1-4503-4927-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
16 | Mohammad Hossein Moaiyeri, Shima Sedighiani, Fazel Sharifi, Keivan Navi |
Design and analysis of carbon nanotube FET based quaternary full adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Inf. Technol. Electron. Eng. ![In: Frontiers Inf. Technol. Electron. Eng. 17(10), pp. 1056-1066, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Andrew Adamatzky |
On Half-Adders Based on Fusion of Signal Carriers: Excitation, Fluidics, and Electricity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Complex Syst. ![In: Complex Syst. 25(3), 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram |
A comparative study on performance and reliability of 32-bit binary adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 53, pp. 54-67, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Yavar Safaei Mehrabani, Mohammad Eshghi |
Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(11), pp. 3268-3281, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Jisha M. Nair, C. Pradeep |
Intelligent selective modular redundancy for online fault detection of adders in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 6(4), pp. 213-221, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Weiqiang Liu 0001, Linbin Chen, Chenghua Wang, Máire O'Neill, Fabrizio Lombardi |
Design and Analysis of Inexact Floating-Point Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 65(1), pp. 308-314, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Yogita Bansal, Charu Madhu |
A novel high-speed approach for 16 × 16 Vedic multiplication with compressor adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 49, pp. 39-49, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Morteza Dorrigiv, Ghassem Jaberipur |
Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 50, pp. 39-53, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Mojtaba Valinataj, Mahboobeh Mirshekar, Hamid Jazayeri |
Novel low-cost and fault-tolerant reversible logic adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 53, pp. 56-72, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Atiyeh Panahi, Fazel Sharifi, Mohammad Hossein Moaiyeri, Keivan Navi |
CNFET-based approximate ternary adders for energy-efficient image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 47, pp. 454-465, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Yongqiang Zhang 0006, Hongjun Lv, Huakun Du, Cheng Huang, Shuai Liu, Guangjun Xie |
Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 44(7), pp. 1351-1366, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Zvi M. Kedem, Kirthi Krishna Muntimadugu |
Mathematical Modeling of General Inaccurate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1606.01753, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
16 | P. Balasubramanian 0001, Nikos E. Mastorakis |
ASIC-based Implementation of Synchronous Section-Carry Based Carry Lookahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1603.07961, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
16 | P. Balasubramanian 0001, Nikos E. Mastorakis |
Design of Synchronous Section-Carry Based Carry Lookahead Adders with Improved Figure of Merit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1606.05621, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
|
16 | Firdous Ahmad, Ghulam Mohiuddin Bhat, Hossein Khademolhosseini, Saeid Azimi, Shaahin Angizi, Keivan Navi |
Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. ![In: J. Comput. Sci. 16, pp. 8-15, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Darjn Esposito, Davide De Caro, Antonio Giuseppe Maria Strollo |
Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8), pp. 1200-1209, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Zhixi Yang, Jun Yang, Kefei Xing, Guang Yang |
An analytical framework for error modeling of approximate adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 13(20), pp. 20160814, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Stephanie O. Ames, Vinicius Zanandrea, Ingrid F. V. Oliveira, Samuel P. Toledo, Cristina Meinhardt |
Investigating PVT variability effects on full adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016, pp. 155-161, 2016, IEEE, 978-1-5090-0733-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Cunxi Yu, Maciej J. Ciesielski |
Analyzing Imprecise Adders Using BDDs - A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016, pp. 152-157, 2016, IEEE Computer Society, 978-1-4673-9039-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Ali Asghar Vatanjou, Even Låte, Trond Ytterdal, Snorre Aunet |
Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCAS ![In: IEEE Nordic Circuits and Systems Conference, NORCAS 2016, Copenhagen, Denmark, November 1-2, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-1095-0. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Lauren Guckert, Earl E. Swartzlander Jr. |
Optimized memristor-based ripple carry adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 50th Asilomar Conference on Signals, Systems and Computers, ACSSC 2016, Pacific Grove, CA, USA, November 6-9, 2016, pp. 1575-1579, 2016, IEEE, 978-1-5386-3954-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Zahiruddin Alamgir, Karsten Beckmann, Nathaniel C. Cady, Alvaro Velasquez, Sumit Kumar Jha 0001 |
Flow-based computing on nanoscale crossbars: Design and implementation of full adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 1870-1873, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Rui Zhou, Weikang Qian |
A General Sign Bit Error Correction Scheme for Approximate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016, pp. 221-226, 2016, ACM, 978-1-4503-4274-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Sunil Dutt, Harsh Patel, Sukumar Nandi, Gaurav Trivedi |
Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-Resilient Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016, pp. 134-139, 2016, IEEE Computer Society, 978-1-4673-8700-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Ugur Cini, Olcay Kurt |
MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2016, Istanbul, Turkey, April 12-14, 2016, pp. 1-4, 2016, IEEE, 978-1-5090-0336-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
16 | Azadeh Alsadat Emrani Zarandi, Amir Sabbagh Molahosseini, Mehdi Hosseinzadeh 0001, Saeid Sorouri, Samuel Antão, Leonel Sousa |
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(2), pp. 374-378, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Yinan Sun, Yongpan Liu, Zhibo Wang 0004, Huazhong Yang |
Multistage Function Speculation Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(4), pp. 954-965, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Cong Liu 0015, Jie Han 0001, Fabrizio Lombardi |
An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 64(5), pp. 1268-1281, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Peter Kornerup |
Reviewing High-Radix Signed-Digit Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 64(5), pp. 1502-1505, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Roberto Sierra, Carlos Carreras, Gabriel Caffarena, Carlos A. López Bario |
A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(1), pp. 52-62, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Atef Ibrahim, Fayez Gebali |
Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 46(9), pp. 783-794, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Kamalika Datta, Tanay Chattopadhyay, Indranil Sengupta 0001 |
All optical design of binary adders using semiconductor optical amplifier assisted Mach-Zehnder interferometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 46(9), pp. 839-847, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Manish Kumar Jaiswal, B. Sharat Chandra Varma 0001, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung |
Configurable Architectures for Multi-Mode Floating Point Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8), pp. 2079-2090, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Weiqiang Liu 0001, Earl E. Swartzlander Jr. |
Design of 3-D quantum-dot cellular automata adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 12(6), pp. 20150195, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Abdulmajeed Alghamdi, Fayez Gebali |
Performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACRIM ![In: IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM 2015, Victoria, BC, Canada, August 24-26, 2015, pp. 80-83, 2015, IEEE, 978-1-4673-7788-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Ioannis Voyiatzis |
Symmetric transparent on-line BIST of word-organized memories with binary adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 20th IEEE European Test Symposium, ETS 2015, Cluj-Napoca, Romania, 25-29 May, 2015, pp. 1-2, 2015, IEEE, 978-1-4799-7603-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Mustafa Aktan, Dursun Baran, Vojin G. Oklobdzija |
Minimizing Energy by Achieving Optimal Sparseness in Parallel Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARITH ![In: 22nd IEEE Symposium on Computer Arithmetic, ARITH 2015, Lyon, France, June 22-24, 2015, pp. 10-17, 2015, IEEE, 978-1-4799-8664-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Leonardo Bandeira Soares, Sergio Bampi, Andre Luis Rodeghiero Rosa, Eduardo A. C. da Costa |
Near-threshold computing for very wide frequency scaling: Approximate adders to rescue performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 13th International New Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, June 7-10, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8893-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Zhixi Yang, Jie Han 0001, Fabrizio Lombardi |
Transmission gate-based approximate adders for inexact computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015, pp. 145-150, 2015, IEEE Computer Society, 978-1-4673-7849-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Honglan Jiang, Jie Han 0001, Fabrizio Lombardi |
A Comparative Review and Evaluation of Approximate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015, pp. 343-348, 2015, ACM, 978-1-4503-3474-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Babu M. Pranay, Srivatsava Jandhyala |
Accuracy Configurable Modified Booth Multiplier Using Approximate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2015, Indore, India, December 21-23, 2015, pp. 281-285, 2015, IEEE, 978-1-4673-9692-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Noureddine Chabini, Said Belkouch |
Area and delay aware approaches for realizing multi-operand addition on FPGAs using two-operand adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: 12th IEEE/ACS International Conference of Computer Systems and Applications, AICCSA 2015, Marrakech, Morocco, November 17-20, 2015, pp. 1-4, 2015, IEEE Computer Society, 978-1-5090-0478-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Karri Manikantta Reddy, Kumar Y. B. Nithin, Dheeraj Sharma, M. H. Vasantha |
Low power, high speed error tolerant multiplier using approximate adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015, pp. 1-6, 2015, IEEE Computer Society, 978-1-4799-1743-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
16 | Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo |
Area-Delay Efficient Binary Adders in QCA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(5), pp. 1174-1179, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Raffaele De Rose, Marco Lanuzza, Fabio Frustaci, Sohan Purohit |
Designing Dynamic Carry Skip Adders: Analysis and Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 33(4), pp. 1019-1034, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Qian Wang, Xiaoyu Song, Ming Gu 0001, Jia-Guang Sun 0001 |
Functional Verification of High Performance Adders in COQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Appl. Math. ![In: J. Appl. Math. 2014, pp. 197252:1-197252:9, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan |
Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10), pp. 1517-1530, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Ireneusz Brzozowski, Andrzej Kos |
Designing of low-power data oriented adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 45(9), pp. 1177-1186, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Stephan Held, Sophie Theresa Spirkl |
Fast Prefix Adders for Non-Uniform Input Arrival Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1411.2917, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
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16 | Cecilia García Martin, Erdal Oruklu |
Performance evaluation of FinFET pass-transistor full adders with BSIM-CMG model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 57th International Midwest Symposium on Circuits and Systems, MWSCAS 2014, College Station, TX, USA, August 3-6, 2014, pp. 917-920, 2014, IEEE, 978-1-4799-4134-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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16 | Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero |
Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014, pp. 118-123, 2014, IEEE Computer Society, 978-1-4799-3763-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Halil Kukner, Pieter Weckx, Sebastien Morrison, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken |
NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 17th Euromicro Conference on Digital System Design, DSD 2014, Verona, Italy, August 27-29, 2014, pp. 98-107, 2014, IEEE Computer Society, 978-1-4799-5793-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Divya Mahajan 0001, Matheen Musaddiq, Earl E. Swartzlander Jr. |
Memristor based adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2014, Pacific Grove, CA, USA, November 2-5, 2014, pp. 1256-1260, 2014, IEEE, 978-1-4799-8297-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Seyed Hamed Fatemi Langroudi, Ghassem Jaberipur |
Double {0, 1, 2} representation modulo-(2n - 3) adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSSIP ![In: International Conference on Systems, Signals and Image Processing, IWSSIP 2014, Dubrovnik, Croatia, May 12-15, 2014, pp. 119-122, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP BibTeX RDF |
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16 | Ting An, Hao Cai, Lirida Alves de Barros Naviner |
Simulation study of aging in CMOS binary adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIPRO ![In: 37th International Convention on Information and Communication Technology, Electronics and Microelectronics, MIPRO 2014, Opatija, Croatia, May 26-30, 2014, pp. 51-55, 2014, IEEE, 978-953-233-081-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz |
On Hard Adders and Carry Chains in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, Boston, MA, USA, May 11-13, 2014, pp. 52-59, 2014, IEEE Computer Society, 978-1-4799-5110-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Li Li 0021, Hai Zhou 0001 |
On error modeling and analysis of approximate adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014, pp. 511-518, 2014, IEEE, 978-1-4799-6277-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Gai Liu, Ye Tao, Mingxing Tan, Zhiru Zhang |
CASA: correlation-aware speculative adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014, pp. 189-194, 2014, ACM, 978-1-4503-2975-0. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Xinghua Yang, Fei Qiao, Chang Liu, Qi Wei 0001, Huazhong Yang |
Design of multi-stage latency adders using detection and sequence-dependence between successive calculations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 998-1001, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Minas Dasygenis |
Generation and validation of multioperand carry save adders from the web. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DTIS ![In: Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2014, Santorini, Greece, May 6-8, 2014, pp. 1-6, 2014, IEEE, 978-1-4799-4972-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
16 | Mahmoud Alshewimy |
Yüksek performanslı karma toplayıcıların tasarımı (High performance hybrid adders design) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2014 |
RDF |
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16 | Mauro Olivieri, Antonio Mastrandrea |
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2013, pp. 785281:1-785281:12, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | David H. K. Hoe, L. P. Deepthi Bollepalli, Chris D. Martinez |
FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2013, pp. 382682:1-382682:10, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Keshab K. Parhi |
Comments on "Low-energy CSMT carry generators and binary adders". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(4), pp. 791, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Jinghang Liang, Jie Han 0001, Fabrizio Lombardi |
New Metrics for the Reliability of Approximate and Probabilistic Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 62(9), pp. 1760-1771, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Javier Hormigo, Julio Villalba, Emilio L. Zapata |
Multioperand Redundant Adders on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 62(10), pp. 2013-2025, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | P. Balasubramanian 0001, David A. Edwards, William B. Toms |
Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 22(4), 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Vaibhav Gupta, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy 0001 |
Low-Power Digital Signal Processing Using Approximate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1), pp. 124-137, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Mehdi Saeedi, Alireza Shafaei, Massoud Pedram |
Constant-Factor Optimization of Quantum Adders on 2D Quantum Architectures ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1304.0432, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
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16 | Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas |
New High-Speed Multioutput Carry Look-Ahead Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 60-II(10), pp. 667-671, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Mehdi Saeedi, Alireza Shafaei, Massoud Pedram |
Constant-Factor Optimization of Quantum Adders on 2D Quantum Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RC ![In: Reversible Computation - 5th International Conference, RC 2013, Victoria, BC, Canada, July 4-5, 2013. Proceedings, pp. 58-69, 2013, Springer, 978-3-642-38985-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | P. Balasubramanian, D. Dhivyaa, J. P. Jayakirthika, P. Kaviyarasi, K. Prasad |
Low power self-timed carry lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 457-460, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Ismo Hänninen, Craig S. Lent, Gregory L. Snider |
Models of irreversibility for binary adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 1071-1074, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Rakshith Saligram |
Design of Low Logical Cost Conservative Reversible Adders Using Novel PCTG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: 2013 International Symposium on Electronic System Design, Singapore, December 10-12, 2013, pp. 46-51, 2013, IEEE Computer Society, 978-0-7695-5143-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
16 | Amit Grover, Neeti Grover |
Comparative Analysis: Area-Efficient Carry Select Adders 180 Nm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: Proceedings of the Asia Modelling Symposium 2013, Seventh Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2013, 23 July, 2013, Hong Kong, China / 25 July, 2013, Kuala Lumpur, Malaysia, pp. 99-102, 2013, IEEE, 978-0-7695-5101-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Martin Kumm, Martin Hardieck, Jens Willkomm, Peter Zipf, Uwe Meyer-Baese |
Multiple constant multiplication with ternary adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: 23rd International Conference on Field programmable Logic and Applications, FPL 2013, Porto, Portugal, September 2-4, 2013, pp. 1-8, 2013, IEEE, 978-1-4799-0004-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Alexios Thanos, Haridimos T. Vergos |
Fast parallel-prefix Ling-carry adders in QCA nanotechnology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 20th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, UAE, December 8-11, 2013, pp. 565-568, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Wesley Chu, Ali I. Unwala, Pohan Wu, Earl E. Swartzlander Jr. |
Implementation of a high speed multiplier using carry lookahead adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 2013 Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, November 3-6, 2013, pp. 400-404, 2013, IEEE, 978-1-4799-2390-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Kjell O. Jeppson, Per Larsson-Edefors |
Exploring prefix-tree adders using excel spreadsheets Setting up an explorative learning environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2013 IEEE International Conference on Microelectronic Systems Education, MSE 2013, Austin, TX, USA, June 2-3, 2013, pp. 48-51, 2013, IEEE Computer Society, 978-1-4799-0139-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Mojtaba Maleknejad, Keivan Navi, Omid Hashemipour |
Dramatically Low-Transistor-Count High-Speed Ternary Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 43rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2013, Toyama, Japan, May 22-24, 2013, pp. 170-175, 2013, IEEE Computer Society, 978-1-4673-6067-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik |
Exploring the energy efficiency of Multispeculative Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013, pp. 309-315, 2013, IEEE Computer Society, 978-1-4799-2987-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Ali Sayyed, Luciano Lavagno, Shah Khalid, Najeeb Ur Rahman |
Implementation and performance analysis of variable latency adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013, pp. 267-272, 2013, IEEE, 978-1-4799-1166-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | George Razvan Voicu, Mihai Lefter, Marius Enachescu, Sorin Dan Cotofana |
3D stacked wide-operand adders: A case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013, Washington, DC, USA, June 5-7, 2013, pp. 133-141, 2013, IEEE Computer Society, 978-1-4799-0494-5. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | Ireneusz Brzozowski, Damian Palys, Andrzej Kos |
An analysis of full adder cells for low-power data oriented adders design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013, Gdynia, Poland, June 20-22, 2013, pp. 346-351, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
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16 | Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan |
Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 50th Annual Design Automation Conference 2013, DAC '13, Austin, TX, USA, May 29 - June 07, 2013, pp. 48:1-48:8, 2013, ACM, 978-1-4503-2071-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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16 | P. Balasubramanian 0001, David A. Edwards, William B. Toms |
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2012, pp. 575389:1-575389:13, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Haridimos T. Vergos |
Area-time efficient end-around inverted carry adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 45(4), pp. 388-394, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Shahzad Asif, Mark Vesterbacka |
Performance analysis of radix-4 adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 45(2), pp. 111-120, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
16 | Haridimos T. Vergos, Dimitris Bakalis |
Area-time efficient multi-modulus adders and their applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 36(5), pp. 409-419, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
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16 | Feng Liu 0029, QingPing Tan, Otmane Aït Mohamed |
Formal proof of integer adders using all-prefix-sums operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 55(9), pp. 1949-1960, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|