Search results for "coprocessor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Yasser Shoukry, M. Watheq El-Kharashi, Sherif Hammad	MPC-On-Chip: An Embedded GPC Coprocessor for Automotive Active Suspension Systems.	IEEE Embed. Syst. Lett.	2010	DBLP DOI BibTeX RDF
16	H. Parandeh-Afshar, Sied Mehdi Fakhraie, Omid Fatemi	Parallel merged multiplier-accumulator coprocessor optimized for digital filters.	Comput. Electr. Eng.	2010	DBLP DOI BibTeX RDF
16	Carsten Albrecht, Jürgen Foag, Roman Koch, Erik Maehle, Thilo Pionteck	DynaCORE - Dynamically Reconfigurable Coprocessor for Network Processors.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
16	Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos	High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures.	ISVLSI	2010	DBLP DOI BibTeX RDF
16	George Kornaros, Antonios Motakis	On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms.	DSD	2010	DBLP DOI BibTeX RDF
16	Holger Flatt, Holger Blume, Peter Pirsch	Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD Resolution.	ReConFig	2010	DBLP DOI BibTeX RDF
16	Zhiping Cai, Zhijun Wang 0001, Kai Zheng 0003	A Distributed TCAM Coprocessor Architecture for Integrated Policy Filtering and Content Filtering.	ICC	2010	DBLP DOI BibTeX RDF
16	Huitao Gu, Shuwei Sun, Shuming Chen	A coprocessor for real-time motion estimation in HD video coding.	VCIP	2010	DBLP DOI BibTeX RDF
16	Peishun Wang, Huaxiong Wang, Josef Pieprzyk	Secure Coprocessor-based Private Information Retrieval without Periodical Preprocessing.	AISC	2010	DBLP BibTeX RDF
16	Liang Ma, Caijun Zhen, Bin Zhao, Jingwei Ma, Gang Wang 0001, Xiaoguang Liu 0001	Towards Fast De-duplication Using Low Energy Coprocessor.	NAS	2010	DBLP DOI BibTeX RDF	De-duplication, Commodity coprocessors, Computing complexity, Low energy
16	Zhi-gang Yang, Jun-lei Qian	Hardware Implementation of RBF Neural Network on FPGA Coprocessor.	ICICA (1)	2010	DBLP DOI BibTeX RDF
16	John R. Douceur, Jeremy Elson, Jon Howell, Jacob R. Lorch	The Utility Coprocessor: Massively Parallel Computation from the Coffee Shop.	USENIX Annual Technical Conference	2010	DBLP BibTeX RDF
16	Soonwoo Choi, Jason Jong Kyu Park, Moonmo Koo, Daewoong Kim, Soo-Ik Chae	A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor.	SoCC	2010	DBLP DOI BibTeX RDF
16	Avinash Lakshminarayana, Sumit Ahuja, Sandeep K. Shukla	Coprocessor design space exploration using high level synthesis.	ISQED	2010	DBLP DOI BibTeX RDF
16	Nicolas Guillermin	A High Speed Coprocessor for Elliptic Curve Scalar Multiplications over \mathbbFp\mathbb{F}_p.	CHES	2010	DBLP DOI BibTeX RDF
16	Silvia Franchini, Antonio Gentile, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile	An embedded, FPGA-based computer graphics coprocessor with native geometric algebra support.	Integr.	2009	DBLP DOI BibTeX RDF
16	Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, Masaki Nakagawa	A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
16	Sumit Ahuja, Swathi T. Gurumani, Chad Spackman, Sandeep K. Shukla	Hardware Coprocessor Synthesis from an ANSI C Specification.	IEEE Des. Test Comput.	2009	DBLP DOI BibTeX RDF
16	Hari Kannan, Michael Dalton, Christos Kozyrakis	Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor.	DSN	2009	DBLP DOI BibTeX RDF
16	Holger Flatt, Ingo Schmädecke, Michael Kärgel, Holger Blume, Peter Pirsch	Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures.	ICSAMOS	2009	DBLP DOI BibTeX RDF
16	Qian Ding, William Robinson	An FPGA Implementation of an Elliptic Curve Cryptosystem Coprocessor over Prime Fields.	ERSA	2009	DBLP BibTeX RDF
16	Lu Gao, Li Guo, Canxing Lu	Acceleration of MELP Algorithm Using DSP Coprocessor with Extended Registers.	DSD	2009	DBLP DOI BibTeX RDF
16	Peng Li, Hua Tang, Weiqian Liang	Low power embedded speech recognition system based on a MCU and a coprocessor.	ICASSP	2009	DBLP DOI BibTeX RDF
16	Grigorios Chrysos 0001, Euripides Sotiriades, Ioannis Papaefstathiou, Apostolos Dollas	A FPGA based coprocessor for gene finding using Interpolated Markov Model (IMM).	FPL	2009	DBLP DOI BibTeX RDF
16	Guillermo Botella Juan, Antonio García Ríos, Uwe Meyer-Bäse, Manuel Rodríguez 0002, María C. Molina, Luís Parrilla Roure	Enhanced gradient-based motion vector coprocessor.	FPL	2009	DBLP DOI BibTeX RDF
16	Muhammad Shahzad, Saira Zahid	Image Coprocessor: A Real-Time Approach Towards Object Tracking.	ICDIP	2009	DBLP DOI BibTeX RDF
16	Srihari Cadambi, Igor Durdanovic, Venkata Jakkula, Murugan Sankaradass, Eric Cosatto, Srimat T. Chakradhar, Hans Peter Graf	A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines.	FCCM	2009	DBLP DOI BibTeX RDF	Machine Learning, FPGAs, Support Vector Machines, Parallel Architectures, Hardware Acceleration
16	Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi, Srimat T. Chakradhar, Igor Durdanovic, Eric Cosatto, Hans Peter Graf	A Massively Parallel Coprocessor for Convolutional Neural Networks.	ASAP	2009	DBLP DOI BibTeX RDF
16	Romuald Mosqueron, Julien Dubois, Marco Mattavelli, David Mauvilet	Smart Camera Based on Embedded HW/SW Coprocessor.	EURASIP J. Embed. Syst.	2008	DBLP DOI BibTeX RDF
16	Volker Hampel, Peter Sobe, Erik Maehle	Experiences with a FPGA-based Reed/Solomon-encoding coprocessor.	Microprocess. Microsystems	2008	DBLP DOI BibTeX RDF
16	Marcelo Panaro de Moraes Zamith, Esteban Walter Gonzalez Clua, Aura Conci, Anselmo Antunes Montenegro, Regina Leal-Toledo, Paulo A. Pagliosa, Luis Valente, Bruno Feijó	A game loop architecture for the GPU used as a math coprocessor in real-time applications.	Comput. Entertain.	2008	DBLP DOI BibTeX RDF	Game loop, real-time physics, GPGPU
16	Lifu Wang, Partha Dasgupta	Coprocessor-based hierarchical trust management for software integrity and digital identity protection.	J. Comput. Secur.	2008	DBLP DOI BibTeX RDF
16	Yi Wang 0016, Douglas L. Maskell, Jussipekka Leiwo	A unified architecture for a public key cryptographic coprocessor.	J. Syst. Archit.	2008	DBLP DOI BibTeX RDF
16	Jing Hu 0006, Steven F. Quigley, Andrew Chan 0002	An element-by-element preconditioned Conjugate Gradient solver of 3D tetrahedral finite elements on an FPGA coprocessor.	FPL	2008	DBLP DOI BibTeX RDF
16	Alessandro Barenghi, Guido Bertoni, Luca Breveglieri, Gerardo Pelosi	A FPGA Coprocessor for the Cryptographic Tate Pairing over Fp.	ITNG	2008	DBLP DOI BibTeX RDF	FPGA Tate Fp
16	Lance Saldanha, Roman L. Lysecky	Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	floating point to fixed conversion, floating point, fixed point, hardware/software partitioning
16	Wei Zhang, Yibo Xue, Dongsheng Wang 0002, Tian Song	A multiple simple regular expression matching architecture and coprocessor for deep packet inspection.	ACSAC	2008	DBLP DOI BibTeX RDF
16	Yijun Liu, Pinghua Chen, Guobo Xie, Zhusong Liu, Zhenkun Li	The Design of a Low-Power Asynchronous DES Coprocessor for Sensor Network Encryption.	ISCSCT (2)	2008	DBLP DOI BibTeX RDF
16	André Rigland Brodtkorb	The Graphics Processor as a Mathematical Coprocessor in MATLAB.	CISIS	2008	DBLP DOI BibTeX RDF
16	Kuo-Kun Tseng, Ying-Dar Lin, Tsern-Huei Lee, Yuan-Cheng Lai	Deterministic high-speed root-hashing automaton matching coprocessor for embedded network processor.	SIGARCH Comput. Archit. News	2007	DBLP DOI BibTeX RDF
16	Alireza Hodjat, Lejla Batina, David Hwang 0001, Ingrid Verbauwhede	HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor.	Integr.	2007	DBLP DOI BibTeX RDF
16	Sotirios G. Ziavras, Alexandros V. Gerbessiotis, Rohan Bafna	Coprocessor design to support MPI primitives in configurable multiprocessors.	Integr.	2007	DBLP DOI BibTeX RDF
16	Robert Simon Sherratt, Kai Zhang, Owen J. Wilkes	A Block Coprocessor for User Data Rate Improvements to GPRS Coding Scheme 4.	J. Circuits Syst. Comput.	2007	DBLP DOI BibTeX RDF
16	Jesús Lázaro 0001, Jagoba Arias, Armando Astarloa, Unai Bidarte, Aitzol Zuloaga	Hardware architecture for a general regression neural network coprocessor.	Neurocomputing	2007	DBLP DOI BibTeX RDF
16	Benno Stabernack, Kai-Immo Wels, Heiko Hübert	A System on a Chip Architecture of an H.264/AVC Coprocessor for DVB-H and DMB Applications.	IEEE Trans. Consumer Electron.	2007	DBLP DOI BibTeX RDF
16	Walter Stechele, L. Alvado Cárcel, Stephan Herrmann 0002, J. Lidón Simón	A Coprocessor for Accelerating Visual Information Processing	CoRR	2007	DBLP BibTeX RDF
16	Adnan Abdul-Aziz Gutub	Area Flexible GF(2k) Elliptic Curve Cryptography Coprocessor.	Int. Arab J. Inf. Technol.	2007	DBLP BibTeX RDF
16	Jean-Luc Beuchat, Nicolas Brisebarre, Masaaki Shirase, Tsuyoshi Takagi, Eiji Okamoto	A Coprocessor for the Final Exponentiation of the etaT Pairing in Characteristic Three.	IACR Cryptol. ePrint Arch.	2007	DBLP BibTeX RDF
16	Henrik Svensson, Thomas Lenart, Viktor Öwall	Implementing the G.723.1 Speech Codec Using a Coarse-Grained Reconfigurable Coprocessor.	ERSA	2007	DBLP BibTeX RDF
16	Ramalatha Marimuthu, S. Kumaravel, Durai Sridharan, Veeraraghavan Sampath Kumar	A Novel Area and Time Efficient Squarer Using Vedic Mathematics for Coprocessor Applications.	MLMTA	2007	DBLP BibTeX RDF
16	You-Bo Wang, Xiang-jun Dong, Zhi-Guang Tian	FPGA Based Design of Elliptic Curve Cryptography Coprocessor.	ICNC (5)	2007	DBLP DOI BibTeX RDF
16	George Emmanuel Bozinis	Neuro-Genetic Coprocessor for Principal Component Analysis.		2007	RDF
16	Christophe Layer	A coprocessor for fast searching in large databases: associative computing engine. (PDF / PS)		2007	RDF
16	David D. Hwang, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede	AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
16	Rahim Khoja, Mehul Marolia, Tinku Acharya, Chaitali Chakrabarti	A coprocessor architecture for fast protein structure prediction.	Pattern Recognit.	2006	DBLP DOI BibTeX RDF
16	Camilo Quintáns, María José Moure, María Dolores Valdés, Enrique Mandado	A virtual instrumentation laboratory based on a reconfigurable coprocessor.	IEEE Trans. Instrum. Meas.	2006	DBLP DOI BibTeX RDF
16	Salvatore Carta, Danilo Pani, Luigi Raffo	Reconfigurable Coprocessor for Multimedia Application Domain.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	multimedia, reconfigurable computing, digital signal processing, domain-specific architectures
16	Bing-Fei Wu, Chung-Fu Lin	Memory-efficient architecture for JPEG 2000 coprocessor with large tile image.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
16	Francisco Fons, Mariano Fons, Enrique Cantó, Mariano López	Dynamically Reconfigurable CORDIC Coprocessor for Trigonometric.	ARCS Workshops	2006	DBLP BibTeX RDF
16	Muhammad Atif Tahir, Ahmed Bouridane	An Fpga Based Coprocessor for Cancer Classification Using Nearest Neighbour Classifier.	ICASSP (3)	2006	DBLP DOI BibTeX RDF
16	Hadi Parandeh-Afshar, Mohsen Ahmadvand, Saeed Safari	A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor.	ICECS	2006	DBLP DOI BibTeX RDF
16	Aziz Ahmedsaid	An FPGA coprocessor for large matrix decompositions.		2006	RDF
16	Ernesto Martins, Luís Almeida 0001, José Alberto Fonseca	An FPGA-based coprocessor for real-time fieldbus traffic scheduling - architecture and implementation.	J. Syst. Archit.	2005	DBLP DOI BibTeX RDF
16	Guillermo Marcus, Juan Arturo Nolazco-Flores	An FPGA-based coprocessor for the SPHINX speech recognition system: early experiences.	ReConFig	2005	DBLP DOI BibTeX RDF
16	Bing-Fei Wu, Chung-Fu Lin	A low memory QCB-based DWT for JPEG2000 coprocessor supporting large tile size.	ICASSP (5)	2005	DBLP DOI BibTeX RDF
16	Chih-Chiang Wu, Sung-Hua Wen, Nen-Fu Huang, Chia-Nan Kao	A pattern matching coprocessor for deep and large signature set in network security system.	GLOBECOM	2005	DBLP DOI BibTeX RDF
16	Ju-Ho Sohn, Jeong-Ho Woo, Ramchan Woo, Hoi-Jun Yoo	A fixed-point multimedia coprocessor with 50Mvertices/s programmable SIMD vertex shader for mobile applications.	ESSCIRC	2005	DBLP DOI BibTeX RDF
16	Kai Zheng 0003, Zhen Liu 0018, Bin Liu 0001	High Performance Embedded Route Lookup Coprocessor for Network Processors.	ICCNMC	2005	DBLP DOI BibTeX RDF
16	Alireza Hodjat, David Hwang 0001, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede	A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-µm CMOS technology.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	crypto-processor, security, FPGA, VLSI, cryptography, advanced encryption standard (AES), ASIC, hardware architectures
16	Fabio Sozzani, Guido Bertoni, Stefano Turcato, Luca Breveglieri	A Parallelized Design for an Elliptic Curve Cryptosystem Coprocessor.	ITCC (1)	2005	DBLP DOI BibTeX RDF
16	Lasse Harju, Jari Nurmi	A Synchronization Coprocessor Architecture for WCDMA/OFDM Mobile Terminal Implementations.	SoC	2005	DBLP DOI BibTeX RDF
16	Young H. Cho, William H. Mangione-Smith	A pattern matching coprocessor for network security.	DAC	2005	DBLP DOI BibTeX RDF	network security, pattern matching, intrusion, snort, pattern search
16	Travis Simpkins	Design, Modeling, and Simulation of a Compact Optoelectronic Neural Coprocessor.		2005	RDF
16	Todd W. Arnold, Leendert van Doorn	The IBM PCIXCC: A new cryptographic coprocessor for the IBM eServer.	IBM J. Res. Dev.	2004	DBLP DOI BibTeX RDF
16	Tom Van Court, Martin C. Herbordt, Richard J. Barton	Case study of a functional genomics application for an FPGA-based coprocessor.	Microprocess. Microsystems	2004	DBLP DOI BibTeX RDF
16	Bing-Fei Wu, Chung-Fu Lin	An efficient architecture for JPEG2000 coprocessor.	IEEE Trans. Consumer Electron.	2004	DBLP DOI BibTeX RDF
16	Guido Bertoni, Luca Breveglieri, Thomas J. Wollinger, Christof Paar	Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems.	IACR Cryptol. ePrint Arch.	2004	DBLP BibTeX RDF
16	Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey	Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor.	DATE	2004	DBLP DOI BibTeX RDF
16	Andreas C. Döring	Parallelism in a CRC Coprocessor.	ARCS Workshops	2004	DBLP BibTeX RDF
16	Muhammad Atif Tahir, Ahmed Bouridane, Fatih Kurugollu	An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer.	FPL	2004	DBLP DOI BibTeX RDF
16	Nick L. Petroni Jr., Timothy Fraser, Jesus Molina, William A. Arbaugh	Copilot - a Coprocessor-based Kernel Runtime Integrity Monitor.	USENIX Security Symposium	2004	DBLP BibTeX RDF
16	Christophe Layer, Hans-Jörg Pfleiderer	High Performance Associative Coprocessor Architecture for Advanced Database Searching.	Databases and Applications	2004	DBLP BibTeX RDF
16	Philip P. Dang	Design of high-performance coprocessor for color error diffusion.	Color Imaging: Processing, Hardcopy, and Applications	2004	DBLP DOI BibTeX RDF
16	John Williams 0004, Neil W. Bergmann	Programmable parallel coprocessor architectures for reconfigurable system-on-chip.	FPT	2004	DBLP DOI BibTeX RDF
16	Sébastien Bilavarn, Eric Debes	Reconfigurable coprocessor for media streaming.	ICME	2004	DBLP BibTeX RDF
16	Bing-Fei Wu, Chung-Fu Lin	Analysis and architecture design for high performance JPEG2000 coprocessor.	ISCAS (2)	2004	DBLP BibTeX RDF
16	Scott F. Smith 0002	A Scalable Coprocessor for Bioinformatic Sequence Alignments.	ESA/VLSI	2004	DBLP BibTeX RDF
16	Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Sung-Bong Yang, Moon Key Lee	An effective out-of-order execution control scheme for an embedded floating point coprocessor.	Microprocess. Microsystems	2003	DBLP DOI BibTeX RDF
16	Maurizio Martina, Andrea Molino, Andrea Terreno, Fabrizio Vacca	Implementation of a SPIHT coprocessor: memory issues and hardware implications.	ICIP (2)	2003	DBLP DOI BibTeX RDF
16	YunKyung Lee, YoungSu Park	High Speed, Small Area AES Block Cipher Coprocessor Design for USIM Card.	VLSI	2003	DBLP BibTeX RDF
16	Isa Servan Uzun, Abbes Amira, Faycal Bensaali	A reconfigurable coprocessor for high-resolution image filtering in real time.	ICECS	2003	DBLP DOI BibTeX RDF
16	Faycal Bensaali, Abbes Amira, Ahmed Bouridane	An FPGA based coprocessor for large matrix product implementation.	FPT	2003	DBLP DOI BibTeX RDF
16	Faycal Bensaali, Abbes Amira, Ahmed Bouridane	An FPGA based coprocessor for 3D affine transformations.	FPT	2003	DBLP DOI BibTeX RDF
16	Christophe Cunat, Jean Gobert, Yves Mathieu	A coprocessor for real-time MPEG4 facial animation on mobiles.	ESTIMedia	2003	DBLP BibTeX RDF
16	Maurizio Martina, Andrea Molino, Andrea Terreno, Fabrizio Vacca	FPGA implementation of a reconfigurable SPIHT coprocessor.	ISSPA (2)	2003	DBLP DOI BibTeX RDF
16	Maurizio Martina, Andrea Molino, Federico Quaglio, Fabrizio Vacca	A power-scalable motion estimation coprocessor for energy constrained applications.	ISSPA (2)	2003	DBLP DOI BibTeX RDF
16	Isa Servan Uzun, Abbes Amira, Aziz Ahmedsaid, Faycal Bensaali	Towards a general framework for an FPGA-based FFT coprocessor.	ISSPA (1)	2003	DBLP DOI BibTeX RDF
16	Rohit Garg, Chris Y. Chung, Donglok Kim, Yongmin Kim 0001	Boundary macroblock padding in MPEG-4 video decoding using a graphics coprocessor.	IEEE Trans. Circuits Syst. Video Technol.	2002	DBLP DOI BibTeX RDF
16	Ernesto Martins, Paulo A. C. S. Neves, José Alberto Fonseca	Architecture of a fieldbus message scheduler coprocessor based on the planning paradigm.	Microprocess. Microsystems	2002	DBLP DOI BibTeX RDF
16	J. Hatashita, J. Harris, H. Smith, P. L. Nico	An Evaluation Architecture for a Network Coprocessor.	IASTED PDCS	2002	DBLP BibTeX RDF