Search results for "cycle-accurate"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
6	Chris Gniady, Babak Falsafi	Speculative Sequential Consistency with Little Custom Storage.	IEEE PACT	2002	DBLP DOI BibTeX RDF
6	Lin Li 0002, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam	Leakage Energy Management in Cache Hierarchies.	IEEE PACT	2002	DBLP DOI BibTeX RDF
6	Georgi Kuzmanov, Stamatis Vassiliadis, Jos T. J. van Eijndhoven	A 2D Addressing Mode for Multimedia Applications.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
6	Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam	EAC: A Compiler Framework for High-Level Energy Estimation and Optimization.	DATE	2002	DBLP DOI BibTeX RDF
6	Syed Saif Abrar	High Performance Multiprocessor Architecture Design Methodology for Application-Specific Embedded Systems.	HiPC	2002	DBLP DOI BibTeX RDF
6	Zachary K. Baker, Viktor K. Prasanna	Performance Modeling and Interpretive Simulation of PIM Architectures and Applications (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
6	Jeanine E. Cook, Richard L. Oliver, Eric E. Johnson	Toward reducing processor simulation time via dynamic reduction of microarchitecture complexity.	SIGMETRICS	2002	DBLP DOI BibTeX RDF
6	Mohamed M. Zahran, Manoj Franklin	A Feasibility Study of Hierarchical Multithreading.	IPDPS	2002	DBLP DOI BibTeX RDF
6	Sujoy Basu, Sumit Roy 0002, Raj Kumar, Tom Fisher, Bruce E. Blaho	Peppermint and Sled: Tools for Evaluating SMP Systems Based on IA-64 (IPF) Processors.	IPDPS	2002	DBLP DOI BibTeX RDF	simulation, architecture, IA-64
6	M. Balakrishnan, Anshul Kumar, C. P. Joshi	A New Performance Evaluation Approach for System Level Design Space Exploration.	ISSS	2002	DBLP DOI BibTeX RDF	design space exploration, system level design, statistical simulation
6	Chris Y. Chung, Ravi Managuli, Yongmin Kim 0001	Design and Evaluation of a Multimedia Computing Architecture Based on a 3D Graphics Pipeline.	ASAP	2002	DBLP DOI BibTeX RDF
6	Anoop Iyer, Diana Marculescu	Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors.	ISCA	2002	DBLP DOI BibTeX RDF
6	Michael I. Gordon, William Thies, Michal Karczmarek, Jasper Lin, Ali S. Meli, Andrew A. Lamb, Chris Leger, Jeremy Wong, Henry Hoffmann, David Maze, Saman P. Amarasinghe	A stream compiler for communication-exposed architectures.	ASPLOS	2002	DBLP DOI BibTeX RDF
6	Yongsoo Joo, Yongseok Choi, Hojun Shim, Hyung Gyu Lee, Kwanho Kim, Naehyuck Chang	Energy exploration and reduction of SDRAM memory systems.	DAC	2002	DBLP DOI BibTeX RDF	low power, memory system, SDRAM
6	Trevor N. Mudge	Power: A First-Class Architectural Design Constraint.	Computer	2001	DBLP DOI BibTeX RDF
6	Christopher T. Weaver, Todd M. Austin	A Fault Tolerant Approach to Microprocessor Design.	DSN	2001	DBLP DOI BibTeX RDF
6	Wei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai	Exploiting VLIW schedule slacks for dynamic and leakage energy reduction.	MICRO	2001	DBLP DOI BibTeX RDF
6	Aneesh Aggarwal, Manoj Franklin	Putting Data Value Predictors to Work in Fine-Grain Parallel Processors.	HiPC	2001	DBLP DOI BibTeX RDF
6	Krishna Kumar Rangan, Philip A. Wilsey, Nilesh Pisolkar, Nael B. Abu-Ghazaleh	PPIM-SIM: An Efficient Simulator for a Parallel Processor in Memory.	Annual Simulation Symposium	2001	DBLP DOI BibTeX RDF
6	André Chátelain, Yves Mathys, Giovanni Placido, Alberto La Rosa, Luciano Lavagno	High-level architectural co-simulation using Esterel and C.	CODES	2001	DBLP DOI BibTeX RDF
6	Krishna Kumar Rangan, Nael B. Abu-Ghazaleh, Philip A. Wilsey	A Distributed Multiple-SIMD Intelligent Memory.	ICPP	2001	DBLP DOI BibTeX RDF	Processing (ICPP '01)-in-memory architectures, PPIM, M-SIMD, ppim-sim, Data-intensive applications
6	Amisha Parikh, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Energy-Aware Instruction Scheduling.	HiPC	2000	DBLP DOI BibTeX RDF
6	Ashutosh S. Dhodapkar, Chee How Lim, George Cai, W. Robert Daasch	TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator.	PACS	2000	DBLP DOI BibTeX RDF
6	Xinan Tang, Manning Aalsma, Raymond Jou	A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors.	FPL	2000	DBLP DOI BibTeX RDF
6	Tajana Simunic, Giovanni De Micheli, Luca Benini, Mat Hans	Source Code Optimization and Profiling of Energy Consumption in Embedded Systems.	ISSS	2000	DBLP DOI BibTeX RDF
6	Jürgen Teich, Philipp W. Kutter, Ralph Weper	Description and Simulation of Microprocessor Instruction Sets Using ASMs.	Abstract State Machines	2000	DBLP DOI BibTeX RDF
6	Martin Burtscher, Benjamin G. Zorn	Hybridizing and Coalescing Load Value Predictors.	ICCD	2000	DBLP DOI BibTeX RDF
6	Tor E. Jeremiassen	Sleipnir - An Instruction-Level Simulator Generator.	ICCD	2000	DBLP DOI BibTeX RDF
6	Ramesh V. Peri, Srinivas Doddapaneni	Compilers and Tools for Embedded Systems - Introduction.	HICSS	2000	DBLP DOI BibTeX RDF
6	Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye	Energy-driven integrated hardware-software optimizations using SimplePower.	ISCA	2000	DBLP DOI BibTeX RDF	energy optimization and estimation, energy simulator, hardware-software interaction, system energy, compiler optimizations, low-power architectures
6	Derek L. Howard, Mikko H. Lipasti	The Effect of Program Optimization on Trace Cache Efficiency.	IEEE PACT	1999	DBLP DOI BibTeX RDF	compiler optimization, Microarchitecture, superscalar processors, trace cache
6	Martin Burtscher, Benjamin G. Zorn	Exploring Last n Value Prediction.	IEEE PACT	1999	DBLP DOI BibTeX RDF	predictor design, value prediction, processor performance, value locality, behavior prediction
6	Bassam Tabbara, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli, Enrica Filippi, Luciano Lavagno	Fast Hardware-Software Co-simulation Using VHDL Models.	DATE	1999	DBLP DOI BibTeX RDF
6	Eric Schnarr, James R. Larus	Fast Out-Of-Order Processor Simulation Using Memoization.	ASPLOS	1998	DBLP DOI BibTeX RDF	out-of-order processor simulation, memoization, direct-execution
6	James Smith 0001, Giovanni De Micheli	Automated Composition of Hardware Components.	DAC	1998	DBLP DOI BibTeX RDF	reconstruction, emulation, visibility, functional simulation
6	Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf	An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures.	ASAP	1997	DBLP DOI BibTeX RDF
6	Claudio Passerone, Luciano Lavagno, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli	Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis.	DAC	1997	DBLP DOI BibTeX RDF