Search results for "field-programmable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Vinay Sriram, David Kearney	High Speed High Fidelity Infrared Scene Simulation Using Reconfigurable Computing.	FPL	2006	DBLP DOI BibTeX RDF
20	Nastaran Baradaran, Pedro C. Diniz	Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures.	FPL	2006	DBLP DOI BibTeX RDF
20	G. Adam Covington, Charles L. G. Comstock, Andrew A. Levine, John W. Lockwood, Young H. Cho	High Speed Document Clustering in Reconfigurable Hardware.	FPL	2006	DBLP DOI BibTeX RDF
20	Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic	Adaptive FPGAs: High-Level Architecture and a Synthesis Method.	FPL	2006	DBLP DOI BibTeX RDF
20	Jason D. Bakos, Charles L. Cathey, Allen Michalski	Predictive Load Balancing for Interconnected FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
20	Ángel Quirós-Olozábal, Ma de los Ángeles Cifredo Chacón, Diego Gomez Vela	FPGA-Based Boundary-Scan Bist.	FPL	2006	DBLP DOI BibTeX RDF
20	Volodymyr V. Kindratenko, David Pointer	A case study in porting a production scientific supercomputing application to a reconfigurable computer.	FCCM	2006	DBLP DOI BibTeX RDF
20	Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan	Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths.	FCCM	2006	DBLP DOI BibTeX RDF
20	Dionissios Efstathiou, Konstantinos Kazakos, Apostolos Dollas	Parrotfish: Task Distribution in a Low Cost Autonomous ad hoc Sensor Network through Dynamic Runtime Reconfiguration.	FCCM	2006	DBLP DOI BibTeX RDF
20	Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann	FPGAs, GPUs and the PS2 - A Single Programming Methodology.	FCCM	2006	DBLP DOI BibTeX RDF
20	Ronald Scrofano, Maya B. Gokhale, Frans Trouw, Viktor K. Prasanna	Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers.	FCCM	2006	DBLP DOI BibTeX RDF
20	Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson	A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer.	FCCM	2006	DBLP DOI BibTeX RDF
20	Heather Quinn, Debayan Bhaduri, Christof Teuscher, Paul S. Graham, Maya B. Gokhale	The STAR-C Truth: Analyzing Reconfigurable Supercomputing Reliability.	FCCM	2006	DBLP DOI BibTeX RDF
20	Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo	Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
20	Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones	A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture.	FCCM	2006	DBLP DOI BibTeX RDF
20	Reid B. Porter, Jan R. Frigo, Maya B. Gokhale, Christophe Wolinski, François Charot, Charles Wagner	A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing.	FCCM	2006	DBLP DOI BibTeX RDF
20	Amit Chowdhary, John P. Hayes	Area-optimal technology mapping for field-programmable gate arrays based on lookup tables.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
20	Kara K. W. Poon, Steven J. E. Wilton, Andy Yan	A detailed power model for field-programmable gate arrays.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Power estimation model, architecture, sensitivity analysis, power consumption
20	David Varghese, J. Neil Ross	A continuous-time hierarchical field programmable analogue array for rapid prototyping and hierarchical approach to analogue systems design.	SBCCI	2005	DBLP DOI BibTeX RDF	HFPAA, differential difference amplifier, interconnectivity analysis, non-permuting grouped combinations listing algorithm, rents rule, second generation current-conveyor, hierarchical architecture, FPAA
20	Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama	Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic.	ISMVL	2005	DBLP DOI BibTeX RDF
20	Peter Tawdross, Andreas König 0001	Investigation of Particle Swarm Optimization for Dynamic Reconfiguration of Field-Programmable Analog Circuits.	HIS	2005	DBLP DOI BibTeX RDF
20	David N. Abramson, Jordan D. Gray, Shyam Subramanian, Paul E. Hasler	A Field-Programmable Analog Array Using Translinear Elements.	IWSOC	2005	DBLP DOI BibTeX RDF
20	Joachim Becker, Fabian Henrici, Yiannos Manoli	System-Level Analog Simulation of a Mixed-Signal Continuous-Time Field Programmable Analog Array.	IWSOC	2005	DBLP DOI BibTeX RDF
20	Jacqueline E. Rice, Kenneth B. Kent, Troy Ronda, Zhao Yong	Configurable hardware solutions for computing autocorrelation coefficients: a case study (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
20	Mohamed Taher, Esam El-Araby, Tarek A. El-Ghazawi, Kris Gaj	Image processing library for reconfigurable computers (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
20	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	Exploration of heterogeneous reconfigurable architectures (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
20	Edward Brown, James Irvine 0001, Bill Wilkie	Rapid prototyping of a test harness for forward error correcting codes (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
20	Nicola Bruti Liberati, Eckhard Platen, Filippo Martini, Massimo Piccardi	An FPGA generator for multipoint distributed random variables (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
20	Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang	Instruction set extension with shadow registers for configurable processors.	FPGA	2005	DBLP DOI BibTeX RDF	shadow register, compilation, ASIP, configurable processor
20	Michael Attig, John W. Lockwood	A framework for rule processing in reconfigurable network systems (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
20	Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster 0001	An FPGA-based VLIW processor with custom hardware execution.	FPGA	2005	DBLP DOI BibTeX RDF	NIOS, parallelism, compiler, synthesis, kernels, VLIW
20	Jasmine Lam, John McAllister, Jennifer Dudley	Core-Based Methodology: An Automated Approach for Implementing a Complete System from Algorithms to a Heterogeneous Network including FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF
20	J. Greg Nash	Systolic Architecture for Computing the Discrete Fourier Transform on FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF
20	Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan	A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation.	FCCM	2005	DBLP DOI BibTeX RDF	standard hardware binary, FPGA, dynamic optimization, system-on-a-chip, platforms, codesign, hardware/software partitioning, configurable logic, Place and route, warp processors, just-in-time (JIT) compilation
20	Michael Attig, John W. Lockwood	A Framework for Rule Processing in Reconfigurable Network Systems.	FCCM	2005	DBLP DOI BibTeX RDF
20	Pedro C. Diniz	Evaluation of Code Generation Strategies for Scalar Replaced Codes in Fine-Grain Configurable Architectures.	FCCM	2005	DBLP DOI BibTeX RDF
20	Young-Il Kim, Bong-Il Park, Jae-Gon Lee, Chong-Min Kyung	SmartGlue: an interface controller with auto reconfiguration for field programmable computing machine.	ASP-DAC	2004	DBLP DOI BibTeX RDF
20	Joachim Becker, Yiannos Manoli	A continuous-time field programmable analog array (FPAA) consisting of digitally reconfigurable GM-cells.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
20	Ji Luo 0003, Joseph B. Bernstein, J. Ari Tuchman, Hu Huang 0001, Kuan-Jung Chung, Anthony L. Wilson	A High Performance Radiation-Hard Field Programmable Analog Array .	ISQED	2004	DBLP DOI BibTeX RDF
20	Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell	An Approach to the Built-In Self-Test of Field Programmable Analog Arrays.	VTS	2004	DBLP DOI BibTeX RDF
20	Ganesh K. Venayagamoorthy, Venu G. Gudise	Swarm Intelligence for Digital Circuits Implementation on Field Programmable Gate Arrays Platforms.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
20	Arturo Hernández Aguirre, Ricardo Salem Zebulum, Carlos A. Coello Coello	Evolutionary Multiobjective Design targeting a Field Programmable Transistor Array.	Evolvable Hardware	2004	DBLP DOI BibTeX RDF
20	Geoffrey Wall, Faizal Iqbal, Jason C. Isaacs, Xiuwen Liu, Simon Y. Foo	Real Time Texture Classification using Field Programmable Gate Arrays.	AIPR	2004	DBLP DOI BibTeX RDF
20	Helmut Steckenbiller, Rudi Knorr	Buffer schemes for runtime reconfiguration of function variants in communication systems.	FPGA	2004	DBLP DOI BibTeX RDF
20	Paul Kohlbrenner, Kris Gaj	An embedded true random number generator for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF	TRNG, FPGA, random numbers, RNG, cryptographic
20	Sashisu Bajracharya, Chang Shu 0003, Kris Gaj, Tarek A. El-Ghazawi	Implementation of elliptic curve cryptosystems over GF(2n) in optimal normal basis on a reconfigurable computer.	FPGA	2004	DBLP DOI BibTeX RDF
20	Terrence S. T. Mak, Kai-Pui Lam	FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation.	FPL	2004	DBLP DOI BibTeX RDF
20	Milos Drutarovský, Viktor Fischer	Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector.	FPL	2004	DBLP DOI BibTeX RDF
20	Edson L. Horta, John W. Lockwood	Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
20	Rawat Siripokarpirom	Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
20	Faycal Bensaali, Abbes Amira	Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic.	FPL	2004	DBLP DOI BibTeX RDF
20	Joseph Zambreno, David Nguyen, Alok N. Choudhary	Exploring Area/Delay Tradeoffs in an AES FPGA Implementation.	FPL	2004	DBLP DOI BibTeX RDF
20	Didier Keymeulen, Ricardo Salem Zebulum, Adrian Stoica, Vu Duong, Michael I. Ferguson	Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device.	FPL	2004	DBLP DOI BibTeX RDF
20	Christophe Layer, Hans-Jörg Pfleiderer	A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data.	FPL	2004	DBLP DOI BibTeX RDF
20	Sashisu Bajracharya, Chang Shu 0003, Kris Gaj, Tarek A. El-Ghazawi	Implementation of Elliptic Curve Cryptosystems over GF(2n) in Optimal Normal Basis on a Reconfigurable Computer.	FPL	2004	DBLP DOI BibTeX RDF
20	Minoru Watanabe, Fuminori Kobayashi	A High-Density Optically Reconfigurable Gate Array Using Dynamic Method.	FPL	2004	DBLP DOI BibTeX RDF
20	Jim Tørresen	An Evolvable Hardware Tutorial.	FPL	2004	DBLP DOI BibTeX RDF
20	Martin Schoeberl	Java Technology in an FPGA.	FPL	2004	DBLP DOI BibTeX RDF
20	Muhammad Atif Tahir, Ahmed Bouridane, Fatih Kurugollu	An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer.	FPL	2004	DBLP DOI BibTeX RDF
20	César Torres-Huitzil, René Cumplido-Parra, Santos López-Estrada	Design and Implementation of a CFAR Processor for Target Detection.	FPL	2004	DBLP DOI BibTeX RDF
20	Viktor Fischer, Milos Drutarovský, Martin Simka, Nathalie Bochard	High Performance True Random Number Generator in Altera Stratix FPLDs.	FPL	2004	DBLP DOI BibTeX RDF
20	David V. Schuehler, John W. Lockwood	A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks.	FPL	2004	DBLP DOI BibTeX RDF
20	Keith D. Underwood, K. Scott Hemmert	Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance.	FCCM	2004	DBLP DOI BibTeX RDF	IEEE floating point, re-configurable computing, FPGA, arithmetic
20	Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow	Reconfigurable Molecular Dynamics Simulator.	FCCM	2004	DBLP DOI BibTeX RDF
20	Philip James-Roxby, Paul R. Schumacher, Charlie Ross	A Single Program Multiple Data Parallel Processing Platform for FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
20	He Chuan, Mi Lu, Chuanwen Sun	Accelerating Seismic Migration Using FPGA-Based Coprocessor Platform.	FCCM	2004	DBLP DOI BibTeX RDF
20	Dirk Eilers, Helmut Steckenbiller, Andreas Herkersdorf	Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication Systems.	FCCM	2004	DBLP DOI BibTeX RDF
20	Michael Attig, Sarang Dharmapurikar, John W. Lockwood	Implementation Results of Bloom Filters for String Matching.	FCCM	2004	DBLP DOI BibTeX RDF
20	Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif	Wiring requirement and three-dimensional integration technology for field programmable gate arrays.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
20	Abderrahim Doumar, Hideo Ito	Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
20	Jean-Luc Beuchat	Some Modular Adders and Multipliers for Field Programmable Gate Arrays.	IPDPS	2003	DBLP DOI BibTeX RDF	modulo m addition, modulo m multiplication, FPGA, Computer arithmetic
20	Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.	ISMVL	2003	DBLP DOI BibTeX RDF
20	H. S. Ng, Sui-Tung Mak, Kai-Pui Lam	Field programmable gate arrays and analog implementation of BRIN for optimization problems.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
20	Ricardo Salem Zebulum, Didier Keymeulen, Vu Duong, Xin Guo 0002, Michael I. Ferguson, Adrian Stoica	Experimental Results in Evolutionary Fault-Recovery for Field Programmable.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
20	Jeannette Plante, Harry C. Shaw, Lisa P. Mickens, Charles T. Johnson-Bey	Overview of Field Programmable Analog Arrays as Enabling Technology for Evolvable Hardware for High Reliability Systems.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
20	Zhibin Dai, Dilip K. Banerji	Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy.	VLSI Design	2003	DBLP DOI BibTeX RDF
20	Joydeep Ray, James C. Hoe	High-level modeling and FPGA prototyping of microprocessors.	FPGA	2003	DBLP DOI BibTeX RDF	operation-centric, FPGA, evaluation, prototyping, microprocessor, microarchitecture
20	François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat	A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL.	FPGA	2003	DBLP DOI BibTeX RDF	AES RIJNDAEL, high encryption rates, FPGA, cryptography, reconfigurable hardware
20	Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald 0001, Russell P. Kraft, Bryan S. Goda	A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.	FPGA	2003	DBLP DOI BibTeX RDF
20	M. A. Hannan Bin Azhar, Keith R. Dimond	FPGA-based design of an evolutionary controller for collision-free robot navigation.	FPGA	2003	DBLP DOI BibTeX RDF
20	Allen Michalski, Kris Gaj, Tarek A. El-Ghazawi	An Implementation Comparison of an IDEA Encryption Cryptosystem on Two General-Purpose Reconfigurable Computers.	FPL	2003	DBLP DOI BibTeX RDF
20	François-Xavier Standaert, Loïc van Oldeneel tot Oldenzeel, David Samyde, Jean-Jacques Quisquater	Power Analysis of FPGAs: How Practical is the Attack?	FPL	2003	DBLP DOI BibTeX RDF
20	John W. Lockwood, Christopher E. Neely, Christopher K. Zuver, James Moscola, Sarang Dharmapurikar, David Lim	An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall.	FPL	2003	DBLP DOI BibTeX RDF
20	Leonel Sousa, Pedro Tomás, Francisco J. Pelayo, Antonio Martínez-Álvarez, Christian A. Morillas, Samuel F. Romero	An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time.	FPL	2003	DBLP DOI BibTeX RDF
20	Javier Ramírez 0001, Uwe Meyer-Bäse, Antonio García 0001, Antonio Lloris-Ruíz	Design and Implementation of RNS-Based Adaptive Filters.	FPL	2003	DBLP DOI BibTeX RDF
20	Roland H. C. Yap, Stella Z. Q. Wang, Martin Henz	Hardware Implementations of Real-Time Reconfigurable WSAT Variants.	FPL	2003	DBLP DOI BibTeX RDF
20	Miguel Angel Aguirre Echánove, Jonathan Noel Tombs, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo	UNSHADES-1: An Advanced Tool for In-System Run-Time Hardware Debugging.	FPL	2003	DBLP DOI BibTeX RDF
20	Nuno Roma, Tiago Dias 0001, Leonel Sousa	Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
20	Stuart Colsell, Reuben Edwards	Adaptive Real-Time Systems and the FPAA.	FPL	2003	DBLP DOI BibTeX RDF
20	David V. Schuehler, Harvey Ku, John W. Lockwood	A TCP/IP Based Multi-device Programming Circuit.	FPL	2003	DBLP DOI BibTeX RDF
20	Haibo Wang 0005, Sarma B. K. Vrudhula	Behavioral synthesis of field programmable analog array circuits.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Programmable circuits, analog synthesis
20	Alan Daly, William P. Marnane	Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, encryption, RSA, public key, exponentiation, modular multiplication, montgomery
20	Andy Yan, Rebecca Cheng, Steven J. E. Wilton	On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques.	FPGA	2002	DBLP DOI BibTeX RDF
20	Barry Shackleford, Motoo Tanaka, Richard J. Carter, Greg Snider	FPGA implementation of neighborhood-of-four cellular automata random number generators.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, cellular automata, random number generator
20	Miguel Arias-Estrada, Eduardo Rodríguez-Palacios	An FPGA Co-processor for Real-Time Visual Tracking.	FPL	2002	DBLP DOI BibTeX RDF
20	Sebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus Künanz	A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor.	FPL	2002	DBLP DOI BibTeX RDF
20	Dylan Carline, Paul Coulton	A Novel Watermarking Technique for LUT Based FPGA Designs.	FPL	2002	DBLP DOI BibTeX RDF
20	Alex Carreira, Trevor W. Fox, Laurence E. Turner	A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM.	FPL	2002	DBLP DOI BibTeX RDF
20	Daniel G. Saab, Fatih Kocan, Jacob A. Abraham	Massively Parallel/Reconfigurable Emulation Model for the D-algorithm.	FPL	2002	DBLP DOI BibTeX RDF
20	Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man	Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications.	FPL	2002	DBLP DOI BibTeX RDF