Search results for "floorplanning"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim	Thermal optimization in multi-granularity multi-core floorplanning.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	Chia-Pin R. Liu	A Novel Floorplanning for Hierarchical VLSI Design.	CATA	2009	DBLP BibTeX RDF
17	Rajeev K. Nain, Malgorzata Chrzanowska-Jeske	Placement-aware 3D Floorplanning.	ISCAS	2009	DBLP DOI BibTeX RDF
17	Fubing Mao, Yuchun Ma, Ning Xu 0006, Xianlong Hong, Yu Wang 0002	Multi-objective Floorplanning Based on Fuzzy Logic.	FSKD (4)	2009	DBLP DOI BibTeX RDF
17	Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong	Simultaneous buffer and interlayer via planning for 3D floorplanning.	ISQED	2009	DBLP DOI BibTeX RDF
17	Louis K. Scheffer	Industrial Floorplanning and Prototyping.	Handbook of Algorithms for Physical Design Automation	2008	DBLP DOI BibTeX RDF
17	Susmita Sur-Kolay	Floorplanning.	Handbook of Algorithms for Physical Design Automation	2008	DBLP DOI BibTeX RDF
17	Dinesh P. Mehta, Yan Feng	Recent Advancesin Floorplanning.	Handbook of Algorithms for Physical Design Automation	2008	DBLP DOI BibTeX RDF
17	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu	An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning.	J. Inf. Sci. Eng.	2008	DBLP BibTeX RDF
17	Jing Liu 0006, Weicai Zhong, Licheng Jiao, Xue Li 0001	Moving Block Sequence and Organizational Evolutionary Algorithm for General Floorplanning With Arbitrarily Shaped Rectilinear Blocks.	IEEE Trans. Evol. Comput.	2008	DBLP DOI BibTeX RDF
17	Jill H. Y. Law, Evangeline F. Y. Young	Multi-bend bus driven floorplanning.	Integr.	2008	DBLP DOI BibTeX RDF
17	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
17	Nikolaos G. Bourbakis	A generic, formal language-based methodology for hierarchical floorplanning-placement.	Comput. Lang. Syst. Struct.	2008	DBLP DOI BibTeX RDF
17	Junhua Wu, Chunmei Ma, Baogui Huang	Congestion Aware High Level Synthesis Combined with Floorplanning.	PACIIA (2)	2008	DBLP DOI BibTeX RDF
17	Renshen Wang, Evangeline F. Y. Young, Yi Zhu 0002, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng	3-D floorplanning using labeled tree and dual sequences.	ISPD	2008	DBLP DOI BibTeX RDF	3-D packing, sequence, labeled tree
17	Guolong Chen, Wenzhong Guo, Hongju Cheng, Xiang Feng, Xiaotong Fang	VLSI floorplanning based on Particle Swarm Optimization.	ISKE	2008	DBLP DOI BibTeX RDF
17	Sea-Ho Kim, Byung-Gyu Ahn, Ki-Seok Chung, Sung-Hwan Oh	Timing driven force-directed floorplanning with incremental static timing analyzer.	APCCAS	2008	DBLP DOI BibTeX RDF
17	Tao Wan, Malgorzata Chrzanowska-Jeske	A novel net-degree distribution model and its application to floorplanning benchmark generation.	Integr.	2007	DBLP DOI BibTeX RDF
17	Love Singhal, Elaheh Bozorgzadeh	Multi-layer floorplanning for reconfigurable designs.	IET Comput. Digit. Tech.	2007	DBLP DOI BibTeX RDF
17	Yongkui Han, Israel Koren	Simulated Annealing Based Temperature Aware Floorplanning.	J. Low Power Electron.	2007	DBLP DOI BibTeX RDF
17	De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang 0003, Ching-Hwa Cheng	Fixed-outline floorplanning using robust evolutionary search.	Eng. Appl. Artif. Intell.	2007	DBLP DOI BibTeX RDF
17	Pingqiang Zhou, Yuchun Ma, Qiang Zhou 0001, Xianlong Hong	Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning.	CAD/Graphics	2007	DBLP DOI BibTeX RDF
17	Heyong Wang, Kang Hu, Jing Liu 0006, Licheng Jiao	Multiagent evolutionary algorithm for floorplanning using moving block sequence.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
17	Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley	Efficient Modeling and Floorplanning of Embedded-FPGA Fabric.	FPL	2007	DBLP DOI BibTeX RDF
17	Rong Luo, Peng Sun	A Novel Ant Colony Optimization Based Temperature-Aware Floorplanning Algorithm.	ICNC (4)	2007	DBLP DOI BibTeX RDF
17	Won-Jin Kim, Ki-Seok Chung	An incremental floorplanning algorithm for temperature reduction.	SoCC	2007	DBLP DOI BibTeX RDF
17	Hailin Jiang, Malgorzata Marek-Sadowska	Power-Gating Aware Floorplanning.	ISQED	2007	DBLP DOI BibTeX RDF
17	Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama	A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning.	PDPTA	2007	DBLP BibTeX RDF
17	Jyh Perng Fang, Yang-Shan Tong, Sao-Jie Chen	An Enhanced BSA for Floorplanning.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2006	DBLP DOI BibTeX RDF
17	Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003	Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm.	J. Circuits Syst. Comput.	2006	DBLP DOI BibTeX RDF
17	Yangdong Deng, Peng Li 0001	Temperature-Aware Floorplanning of 3-D ICs Considering Thermally Dependent Leakage Power.	J. Low Power Electron.	2006	DBLP DOI BibTeX RDF
17	Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng	Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.	IEEE Trans. Circuits Syst. I Regul. Pap.	2006	DBLP DOI BibTeX RDF
17	Masaya Yoshikawa, Hidekazu Terai	Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation.	J. Adv. Comput. Intell. Intell. Informatics	2006	DBLP DOI BibTeX RDF
17	Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong	Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree.	JCIS	2006	DBLP DOI BibTeX RDF
17	Sami J. Habib	Modeling the Coverage Problem in Wireless Sensor Networks as Floorplanning and Placement Problems.	Wireless and Optical Communications	2006	DBLP BibTeX RDF
17	Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar	Comparing simulation techniques for microarchitecture-aware floorplanning.	ISPASS	2006	DBLP DOI BibTeX RDF
17	Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu	On handling the fixed-outline constraints of floorplanning using less flexibility first principles.	ISCAS	2006	DBLP DOI BibTeX RDF
17	Magdy S. Abadir	Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs.	IOLTS	2006	DBLP DOI BibTeX RDF
17	Wei-Lun Hung, Greg M. Link, Yuan Xie 0001, Narayanan Vijaykrishnan, Mary Jane Irwin	Interconnect and Thermal-aware Floorplanning for 3D Microprocessors.	ISQED	2006	DBLP DOI BibTeX RDF
17	Karthik Sankaranarayanan, Sivakumar Velusamy, Mircea R. Stan, Kevin Skadron	A Case for Thermal-Aware Floorplanning at the Microarchitectural Level.	J. Instr. Level Parallelism	2005	DBLP BibTeX RDF
17	Rong Liu, Sheqin Dong, Xianlong Hong	An efficient algorithm to fixed-outline floorplanning based on instance augmentation.	CAD/Graphics	2005	DBLP DOI BibTeX RDF
17	Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong	Microarchitecture evaluation with floorplanning and interconnect pipelining.	ASP-DAC	2005	DBLP DOI BibTeX RDF
17	Masaya Yoshikawa, Hidekazu Terai	Hybrid genetic algorithm engine for high-speed floorplanning.	ECCTD	2005	DBLP DOI BibTeX RDF
17	Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin	IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs.	ICCAD	2005	DBLP DOI BibTeX RDF
17	Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen	Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
17	Yunfeng Wang, Jinian Bian, Xianlong Hong	Interconnect delay optimization via high level re-synthesis after floorplanning.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
17	Jacob R. Minz, Eric Wong 0002, Sung Kyu Lim	Reliability-aware floorplanning for 3D circuits.	SoCC	2005	DBLP DOI BibTeX RDF
17	Song Chen 0001, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng	Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.	ISQED	2005	DBLP DOI BibTeX RDF
17	Gregory J. Briggs, Edwin J. Tan, Nicholas A. Nelson, David H. Albonesi	QUILT: a GUI-based integrated circuit floorplanning environment for computer architecture research and education.	WCAE@ISCA	2005	DBLP DOI BibTeX RDF
17	Guowu Yang, Xiaoyu Song, Hannah Honghua Yang, Fei Xie	A Theoretical Upper Bound for IP-Based Floorplanning.	COCOON	2005	DBLP DOI BibTeX RDF
17	Jing Liu 0006, Weicai Zhong, Licheng Jiao	Moving Block Sequence and Organizational Evolutionary Algorithm for General Floorplanning.	CIS (1)	2005	DBLP DOI BibTeX RDF
17	Song Chen 0001, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu	A buffer planning algorithm for chip-level floorplanning.	Sci. China Ser. F Inf. Sci.	2004	DBLP DOI BibTeX RDF
17	Richard Auletta	Expert System Perimeter Block Placement Floorplanning.	DATE	2004	DBLP DOI BibTeX RDF
17	Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen	Temporal floorplanning using 3D-subTCG.	ASP-DAC	2004	DBLP DOI BibTeX RDF
17	Yi-Hui Cheng, Yao-Wen Chang	Integrating buffer planning with floorplanning for simultaneous multi-objective optimization.	ASP-DAC	2004	DBLP DOI BibTeX RDF
17	Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang	Substrate noise-aware floorplanning for mixed-signal SOCs.	ISCAS (2)	2004	DBLP BibTeX RDF
17	Tao Wan, Malgorzata Chrzanowska-Jeske	Generating random benchmark circuits for floorplanning.	ISCAS (5)	2004	DBLP BibTeX RDF
17	Pun Hang Shiu, Ramprasad Ravichandran, Siddharth Easwar, Sung Kyu Lim	Multi-layer floorplanning for reliable system-on-package.	ISCAS (5)	2004	DBLP BibTeX RDF
17	Ching-Chung Hu, De-Sheng Chen, Yiwen Wang 0003	Fast multilevel floorplanning for large scale modules.	ISCAS (5)	2004	DBLP BibTeX RDF
17	Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske	Substrate noise optimization in early floorplanning for mixed signal SOCs.	SoCC	2004	DBLP DOI BibTeX RDF
17	Saurabh N. Adya	Unification of VLSI placement and floorplanning.		2004	RDF
17	Keith W. C. Wong, Evangeline F. Y. Young	Fast buffer planning and congestion optimization in interconnect-driven floorplanning.	ASP-DAC	2003	DBLP DOI BibTeX RDF
17	Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou 0001	Interconnect-driven floorplanning by searching alternative packings.	ASP-DAC	2003	DBLP DOI BibTeX RDF
17	Katherine Shu-Min Li, Yih-Huai Cherng, Yao-Wen Chang	Noise-aware buffer planning for interconnect-driven floorplanning.	ASP-DAC	2003	DBLP DOI BibTeX RDF
17	Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong 0001	Floorplanning with power supply noise avoidance.	ASP-DAC	2003	DBLP DOI BibTeX RDF
17	Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao	Simultaneous floorplanning and buffer block planning.	ASP-DAC	2003	DBLP DOI BibTeX RDF
17	Shinya Yamasaki, Shingo Nakaya, Shin'ichi Wakabayashi, Tetsushi Koide	A Performance-Driven Floorplanning Method with Interconnect Performance Estimation.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2002	DBLP BibTeX RDF
17	Miguel F. Anjos, Anthony Vannelli	An Attractor-Repeller approach to floorplanning.	Math. Methods Oper. Res.	2002	DBLP DOI BibTeX RDF
17	Hua Tang, Alex Doboli	Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing.	IWLS	2002	DBLP BibTeX RDF
17	Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu	Floorplanning with abutment constraints based on corner block list.	Integr.	2001	DBLP DOI BibTeX RDF
17	Saurabh N. Adya, Igor L. Markov	Fixed-outline Floorplanning through Better Local Search.	ICCD	2001	DBLP DOI BibTeX RDF
17	Hung-Ming Chen, D. F. Wong 0001, Wai-Kei Mak, Hannah Honghua Yang	Faster and more accurate wiring evaluation in interconnect-centric floorplanning.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
17	Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu	Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.	DAC	2001	DBLP DOI BibTeX RDF
17	Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh	3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems.	Des. Autom. Embed. Syst.	2000	DBLP DOI BibTeX RDF
17	Nikolaos G. Bourbakis, Mohammad Mortazavi	A floorplanning-Synthesis Methodology for Multiple Chip Module Design.	Trans. SDPS	2000	DBLP BibTeX RDF
17	Abdallah Tabbara, Bassam Tabbara, Robert K. Brayton, A. Richard Newton	Integration of retiming with architectural floorplanning.	Integr.	2000	DBLP DOI BibTeX RDF
17	Bah-Hwee Gwee, Meng-Hiot Lim	A GA with heuristic-based decoder for IC floorplanning.	Integr.	2000	DBLP DOI BibTeX RDF
17	Milan Vasilko, Graham Benyon-Tinker	Automatic Temporal Floorplanning with Guaranteed Solution Feasibility.	FPL	2000	DBLP DOI BibTeX RDF
17	María José Gil Larrea, José Miguel Urquijo Aramburu, José Luis Gutiérrez Temiño	Minimum area in wheels [VLSI floorplanning].	ICECS	2000	DBLP DOI BibTeX RDF
17	Patrick Groeneveld, Jacob Greidinger, J. George Janac, Wilm E. Donath	The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only).	ISPD	2000	DBLP DOI BibTeX RDF
17	Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh	Routability-driven repeater block planning for interconnect-centric floorplanning.	ISPD	2000	DBLP DOI BibTeX RDF
17	Shingo Nakaya, Tetsushi Koide, Shin'ichi Wakabayashi	An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair.	ISCAS	2000	DBLP DOI BibTeX RDF
17	Tetsushi Koide, Shin'ichi Wakabayashi	A timing-driven floorplanning algorithm with the Elmore delay model for building block layout.	Integr.	1999	DBLP DOI BibTeX RDF
17	Milan Vasilko	DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems.	FPL	1999	DBLP DOI BibTeX RDF
17	Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin	A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning.	DAC	1999	DBLP DOI BibTeX RDF
17	Manfred Schoelzke	Timing driven floorplanning beim hierarchischen VLSI-Entwurf.		1999	RDF
17	Shantanu Tarafdar, Miriam Leeser, Zixin Yin	Integrating floorplanning in data-transfer based high-level synthesis.	ICCAD	1998	DBLP DOI BibTeX RDF
17	Israel Koren, Zahava Koren	Yield and Routing Objectives in Floorplanning.	DFT	1998	DBLP DOI BibTeX RDF
17	Zahava Koren, Israel Koren	On the effect of floorplanning on the yield of large area integrated circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
17	Helena Krupnova, Christian Rabedaoro, Gabriele Saucier	Synthesis and Floorplanning for Large Hierarchical FPGAs.	FPGA	1997	DBLP DOI BibTeX RDF
17	Jianzhong Shi, Dinesh Bhatia	Performance Driven Floorplanning for FPGA Based Designs.	FPGA	1997	DBLP DOI BibTeX RDF
17	Maggie Zhiwei Kang, Wayne Wei-Ming Dai	General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure.	ASP-DAC	1997	DBLP DOI BibTeX RDF
17	Dinesh P. Mehta, Naveed A. Sherwani	A Minimum-Area Floorplanning Algorithm for MBC Designs.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF
17	Gary K. H. Yeap, Majid Sarrafzadeh	Sliceable Floorplanning by Graph Dualization.	SIAM J. Discret. Math.	1995	DBLP DOI BibTeX RDF
17	Habib Youssef, Sadiq M. Sait, Khalid J. Al-Farra	Timing influenced force directed floorplanning.	EURO-DAC	1995	DBLP DOI BibTeX RDF
17	Morteza Saheb Zamani, Graham R. Hellestrand	A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs.	ISCAS	1995	DBLP DOI BibTeX RDF
17	Kai-Yuan Chao, D. F. Wong 0001	Floorplanning for Low Power Designs.	ISCAS	1995	DBLP DOI BibTeX RDF
17	Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman	Floorplanning with Datapath Optimization.	ISCAS	1995	DBLP DOI BibTeX RDF
17	Carsten F. Ball, Peter V. Kraus, Dieter A. Mlynski	Fuzzy Partitioning applied to VLSI-Floorplanning and Placement.	ISCAS	1994	DBLP DOI BibTeX RDF
17	Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida	A Floorplanning Method with Topological Constraint Manipulation.	ISCAS	1994	DBLP DOI BibTeX RDF