Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim |
Thermal optimization in multi-granularity multi-core floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 43-48, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Chia-Pin R. Liu |
A Novel Floorplanning for Hierarchical VLSI Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CATA ![In: Proceedings of the ISCA 24th International Conference on Computers and Their Applications, CATA 2009, April 8-10, 2009, Holiday Inn Downtown-Superdome, New Orleans, Louisiana, USA, pp. 81-86, 2009, ISCA, 978-1-880843-70-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
17 | Rajeev K. Nain, Malgorzata Chrzanowska-Jeske |
Placement-aware 3D Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 1727-1730, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Fubing Mao, Yuchun Ma, Ning Xu 0006, Xianlong Hong, Yu Wang 0002 |
Multi-objective Floorplanning Based on Fuzzy Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSKD (4) ![In: Sixth International Conference on Fuzzy Systems and Knowledge Discovery, FSKD 2009, Tianjin, China, 14-16 August 2009, 6 Volumes, pp. 331-335, 2009, IEEE Computer Society, 978-0-7695-3735-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong |
Simultaneous buffer and interlayer via planning for 3D floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 740-745, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Louis K. Scheffer |
Industrial Floorplanning and Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook of Algorithms for Physical Design Automation ![In: Handbook of Algorithms for Physical Design Automation., 2008, Auerbach Publications, 978-0-8493-7242-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Susmita Sur-Kolay |
Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook of Algorithms for Physical Design Automation ![In: Handbook of Algorithms for Physical Design Automation., 2008, Auerbach Publications, 978-0-8493-7242-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Dinesh P. Mehta, Yan Feng |
Recent Advancesin Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Handbook of Algorithms for Physical Design Automation ![In: Handbook of Algorithms for Physical Design Automation., 2008, Auerbach Publications, 978-0-8493-7242-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu |
An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 24(1), pp. 115-127, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP BibTeX RDF |
|
17 | Jing Liu 0006, Weicai Zhong, Licheng Jiao, Xue Li 0001 |
Moving Block Sequence and Organizational Evolutionary Algorithm for General Floorplanning With Arbitrarily Shaped Rectilinear Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 12(5), pp. 630-646, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Jill H. Y. Law, Evangeline F. Y. Young |
Multi-bend bus driven floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 41(2), pp. 306-316, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(6), pp. 733-744, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Nikolaos G. Bourbakis |
A generic, formal language-based methodology for hierarchical floorplanning-placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Lang. Syst. Struct. ![In: Comput. Lang. Syst. Struct. 34(1), pp. 25-42, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Junhua Wu, Chunmei Ma, Baogui Huang |
Congestion Aware High Level Synthesis Combined with Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACIIA (2) ![In: PACIIA 2008, Volume 2, 2008 IEEE Pacific-Asia Workshop on Computational Intelligence and Industrial Application, 19-20 December 2008, Wuhan, China, pp. 935-938, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Renshen Wang, Evangeline F. Y. Young, Yi Zhu 0002, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng |
3-D floorplanning using labeled tree and dual sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008, pp. 54-59, 2008, ACM, 978-1-60558-048-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
3-D packing, sequence, labeled tree |
17 | Guolong Chen, Wenzhong Guo, Hongju Cheng, Xiang Feng, Xiaotong Fang |
VLSI floorplanning based on Particle Swarm Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISKE ![In: 3rd International Conference on Intelligent System and Knowledge Engineering, ISKE 2008, Xiamen, China, November 17-19, 2008, pp. 1020-1025, 2008, IEEE, 978-1-4244-2196-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Sea-Ho Kim, Byung-Gyu Ahn, Ki-Seok Chung, Sung-Hwan Oh |
Timing driven force-directed floorplanning with incremental static timing analyzer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008, pp. 1000-1003, 2008, IEEE, 978-1-4244-2342-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Tao Wan, Malgorzata Chrzanowska-Jeske |
A novel net-degree distribution model and its application to floorplanning benchmark generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 40(4), pp. 420-433, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Love Singhal, Elaheh Bozorgzadeh |
Multi-layer floorplanning for reconfigurable designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 1(4), pp. 276-294, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Yongkui Han, Israel Koren |
Simulated Annealing Based Temperature Aware Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 3(2), pp. 141-155, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang 0003, Ching-Hwa Cheng |
Fixed-outline floorplanning using robust evolutionary search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Eng. Appl. Artif. Intell. ![In: Eng. Appl. Artif. Intell. 20(6), pp. 821-830, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Pingqiang Zhou, Yuchun Ma, Qiang Zhou 0001, Xianlong Hong |
Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAD/Graphics ![In: 10th International Conference on Computer-Aided Design and Computer Graphics, CAD/Graphics 2007, Beijing, China, 15-18 October, 2007, pp. 338-343, 2007, IEEE, 978-1-4244-1579-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Heyong Wang, Kang Hu, Jing Liu 0006, Licheng Jiao |
Multiagent evolutionary algorithm for floorplanning using moving block sequence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore, pp. 4372-4377, 2007, IEEE, 978-1-4244-1339-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley |
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 665-669, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Rong Luo, Peng Sun |
A Novel Ant Colony Optimization Based Temperature-Aware Floorplanning Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC (4) ![In: Third International Conference on Natural Computation, ICNC 2007, Haikou, Hainan, China, 24-27 August 2007, Volume 4, pp. 751-755, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Won-Jin Kim, Ki-Seok Chung |
An incremental floorplanning algorithm for temperature reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2007 IEEE International SOC Conference, Tampere, Finland, November 19-21, 2007, pp. 67-70, 2007, IEEE, 978-1-4244-1592-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Hailin Jiang, Malgorzata Marek-Sadowska |
Power-Gating Aware Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 853-860, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Takayoshi Shimazu, Shin'ichi Wakabayashi, Shinobu Nagayama |
A Parallel Multistage Metaheuristic Algorithm for VLSI Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2007, Las Vegas, Nevada, USA, June 25-28, 2007, Volume 2, pp. 801-807, 2007, CSREA Press, 1-60132-021-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
17 | Jyh Perng Fang, Yang-Shan Tong, Sao-Jie Chen |
An Enhanced BSA for Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2), pp. 528-534, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003 |
Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 15(1), pp. 107-128, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Yangdong Deng, Peng Li 0001 |
Temperature-Aware Floorplanning of 3-D ICs Considering Thermally Dependent Leakage Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 2(2), pp. 177-188, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Zhuoyuan Li, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng |
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12), pp. 2637-2646, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Masaya Yoshikawa, Hidekazu Terai |
Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Adv. Comput. Intell. Intell. Informatics ![In: J. Adv. Comput. Intell. Intell. Informatics 10(1), pp. 112-120, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong |
Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JCIS ![In: Proceedings of the 2006 Joint Conference on Information Sciences, JCIS 2006, Kaohsiung, Taiwan, ROC, October 8-11, 2006, 2006, Atlantis Press, 90-78677-01-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Sami J. Habib |
Modeling the Coverage Problem in Wireless Sensor Networks as Floorplanning and Placement Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wireless and Optical Communications ![In: Sixth IASTED International Multi-Conference on Wireless and Optical Communications: Conference on Communication Systems and Applications, Conference on Optical Communication Systems and Networks, Conference on Wireless Networks and Emerging Technologies, Conference on Wireless SENSOR Networks, Banff, Alberta, Canada, July 3-5, 2006, 2006, IASTED/ACTA Press, 0-88986-565-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
17 | Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar |
Comparing simulation techniques for microarchitecture-aware floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2006 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2006, March 19-21, 2006, Austin, Texas, USA, Proceedings, pp. 80-88, 2006, IEEE Computer Society, 1-4244-0186-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu |
On handling the fixed-outline constraints of floorplanning using less flexibility first principles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Magdy S. Abadir |
Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 81, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Wei-Lun Hung, Greg M. Link, Yuan Xie 0001, Narayanan Vijaykrishnan, Mary Jane Irwin |
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 98-104, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Karthik Sankaranarayanan, Sivakumar Velusamy, Mircea R. Stan, Kevin Skadron |
A Case for Thermal-Aware Floorplanning at the Microarchitectural Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Instr. Level Parallelism ![In: J. Instr. Level Parallelism 7, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
17 | Rong Liu, Sheqin Dong, Xianlong Hong |
An efficient algorithm to fixed-outline floorplanning based on instance augmentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAD/Graphics ![In: 9th International Conference on Computer-Aided Design and Computer Graphics, CAD/Graphics 2005, Hong Kong, China, 7-10 December, 2005, pp. 6, 2005, IEEE Computer Society, 0-7695-2473-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong |
Microarchitecture evaluation with floorplanning and interconnect pipelining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 8-15, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Masaya Yoshikawa, Hidekazu Terai |
Hybrid genetic algorithm engine for high-speed floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: Proceedings of the 2005 European Conference on Circuit Theory and Design, ECCTD 2005, Cork, Ireland, August 29th - September 1st 2005, pp. 189-192, 2005, IEEE, 0-7803-9066-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin |
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2005 International Conference on Computer-Aided Design, ICCAD 2005, San Jose, CA, USA, November 6-10, 2005, pp. 159-164, 2005, IEEE Computer Society, 0-7803-9254-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen |
Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2219-2222, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Yunfeng Wang, Jinian Bian, Xianlong Hong |
Interconnect delay optimization via high level re-synthesis after floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5641-5644, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Jacob R. Minz, Eric Wong 0002, Sung Kyu Lim |
Reliability-aware floorplanning for 3D circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Proceedings 2005 IEEE International SOC Conference, September 25-28, 2005, Washington Dulles Airport, Herndon, VA, USA, pp. 81-82, 2005, IEEE, 0-7803-9264-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Song Chen 0001, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng |
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 628-633, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Gregory J. Briggs, Edwin J. Tan, Nicholas A. Nelson, David H. Albonesi |
QUILT: a GUI-based integrated circuit floorplanning environment for computer architecture research and education. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE@ISCA ![In: Proceedings of the 2005 workshop on Computer architecture education - held in conjunction with the 32nd International Symposium on Computer Architecture, WCAE@ISCA 2005, Madison, Wisconsin, USA, June 5, 2005, pp. 5, 2005, ACM, 978-1-4503-4734-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Guowu Yang, Xiaoyu Song, Hannah Honghua Yang, Fei Xie |
A Theoretical Upper Bound for IP-Based Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COCOON ![In: Computing and Combinatorics, 11th Annual International Conference, COCOON 2005, Kunming, China, August 16-29, 2005, Proceedings, pp. 411-419, 2005, Springer, 3-540-28061-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Jing Liu 0006, Weicai Zhong, Licheng Jiao |
Moving Block Sequence and Organizational Evolutionary Algorithm for General Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIS (1) ![In: Computational Intelligence and Security, International Conference, CIS 2005, Xi'an, China, December 15-19, 2005, Proceedings, Part I, pp. 238-246, 2005, Springer, 3-540-30818-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Song Chen 0001, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
A buffer planning algorithm for chip-level floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 47(6), pp. 763-776, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Richard Auletta |
Expert System Perimeter Block Placement Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 140-143, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen |
Temporal floorplanning using 3D-subTCG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 725-730, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Yi-Hui Cheng, Yao-Wen Chang |
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 624-627, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang |
Substrate noise-aware floorplanning for mixed-signal SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 445-448, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
17 | Tao Wan, Malgorzata Chrzanowska-Jeske |
Generating random benchmark circuits for floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 345-348, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
17 | Pun Hang Shiu, Ramprasad Ravichandran, Siddharth Easwar, Sung Kyu Lim |
Multi-layer floorplanning for reliable system-on-package. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 69-72, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
17 | Ching-Chung Hu, De-Sheng Chen, Yiwen Wang 0003 |
Fast multilevel floorplanning for large scale modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 205-208, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
17 | Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske |
Substrate noise optimization in early floorplanning for mixed signal SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA, pp. 301-304, 2004, IEEE, 0-7803-8445-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Saurabh N. Adya |
Unification of VLSI placement and floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2004 |
RDF |
|
17 | Keith W. C. Wong, Evangeline F. Y. Young |
Fast buffer planning and congestion optimization in interconnect-driven floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 411-416, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou 0001 |
Interconnect-driven floorplanning by searching alternative packings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 417-422, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Katherine Shu-Min Li, Yih-Huai Cherng, Yao-Wen Chang |
Noise-aware buffer planning for interconnect-driven floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 423-426, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong 0001 |
Floorplanning with power supply noise avoidance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 427-430, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao |
Simultaneous floorplanning and buffer block planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 431-434, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Shinya Yamasaki, Shingo Nakaya, Shin'ichi Wakabayashi, Tetsushi Koide |
A Performance-Driven Floorplanning Method with Interconnect Performance Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. ![In: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12), pp. 2775-2784, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
17 | Miguel F. Anjos, Anthony Vannelli |
An Attractor-Repeller approach to floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Methods Oper. Res. ![In: Math. Methods Oper. Res. 56(1), pp. 3-27, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Hua Tang, Alex Doboli |
Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWLS ![In: 11th IEEE/ACM International Workshop on Logic & Synthesis, IWLS 2002, June 4-7, 2002, New Orleans, Louisiana, USA., pp. 41-44, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
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17 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Floorplanning with abutment constraints based on corner block list. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 31(1), pp. 65-77, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Saurabh N. Adya, Igor L. Markov |
Fixed-outline Floorplanning through Better Local Search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings, pp. 328-334, 2001, IEEE Computer Society, 0-7695-1200-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Hung-Ming Chen, D. F. Wong 0001, Wai-Kei Mak, Hannah Honghua Yang |
Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001, pp. 62-67, 2001, ACM, 1-58113-351-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001, pp. 770-775, 2001, ACM, 1-58113-297-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh |
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 5(3-4), pp. 329-338, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Nikolaos G. Bourbakis, Mohammad Mortazavi |
A floorplanning-Synthesis Methodology for Multiple Chip Module Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. SDPS ![In: Trans. SDPS 4(1), pp. 67-81, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP BibTeX RDF |
|
17 | Abdallah Tabbara, Bassam Tabbara, Robert K. Brayton, A. Richard Newton |
Integration of retiming with architectural floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 29(1), pp. 25-43, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Bah-Hwee Gwee, Meng-Hiot Lim |
A GA with heuristic-based decoder for IC floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 28(2), pp. 157-172, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Milan Vasilko, Graham Benyon-Tinker |
Automatic Temporal Floorplanning with Guaranteed Solution Feasibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 656-664, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | María José Gil Larrea, José Miguel Urquijo Aramburu, José Luis Gutiérrez Temiño |
Minimum area in wheels [VLSI floorplanning]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2000 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, December 17-20, 2000, pp. 646-649, 2000, IEEE, 0-7803-6542-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Patrick Groeneveld, Jacob Greidinger, J. George Janac, Wilm E. Donath |
The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 214, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Probir Sarkar, Vivek Sundararaman, Cheng-Kok Koh |
Routability-driven repeater block planning for interconnect-centric floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 186-191, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Shingo Nakaya, Tetsushi Koide, Shin'ichi Wakabayashi |
An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 65-68, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Tetsushi Koide, Shin'ichi Wakabayashi |
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 27(1), pp. 57-76, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Milan Vasilko |
DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 9th International Workshop, FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings, pp. 124-133, 1999, Springer, 3-540-66457-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin |
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999., pp. 262-267, 1999, ACM Press. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Manfred Schoelzke |
Timing driven floorplanning beim hierarchischen VLSI-Entwurf. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1999 |
RDF |
|
17 | Shantanu Tarafdar, Miriam Leeser, Zixin Yin |
Integrating floorplanning in data-transfer based high-level synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1998, San Jose, CA, USA, November 8-12, 1998, pp. 412-417, 1998, ACM / IEEE Computer Society, 1-58113-008-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Israel Koren, Zahava Koren |
Yield and Routing Objectives in Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 28-36, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Zahava Koren, Israel Koren |
On the effect of floorplanning on the yield of large area integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(1), pp. 3-14, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Helena Krupnova, Christian Rabedaoro, Gabriele Saucier |
Synthesis and Floorplanning for Large Hierarchical FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, FPGA 1997, Monterey, CA, USA, February 9-11, 1997, pp. 105-111, 1997, ACM, 0-89791-801-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Jianzhong Shi, Dinesh Bhatia |
Performance Driven Floorplanning for FPGA Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, FPGA 1997, Monterey, CA, USA, February 9-11, 1997, pp. 112-118, 1997, ACM, 0-89791-801-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Maggie Zhiwei Kang, Wayne Wei-Ming Dai |
General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997, pp. 265-270, 1997, IEEE, 0-7803-3663-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Dinesh P. Mehta, Naveed A. Sherwani |
A Minimum-Area Floorplanning Algorithm for MBC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 56-59, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Gary K. H. Yeap, Majid Sarrafzadeh |
Sliceable Floorplanning by Graph Dualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Discret. Math. ![In: SIAM J. Discret. Math. 8(2), pp. 258-280, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Habib Youssef, Sadiq M. Sait, Khalid J. Al-Farra |
Timing influenced force directed floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995, pp. 156-161, 1995, IEEE Computer Society, 0-8186-7156-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Morteza Saheb Zamani, Graham R. Hellestrand |
A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 49-52, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Kai-Yuan Chao, D. F. Wong 0001 |
Floorplanning for Low Power Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 45-48, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman |
Floorplanning with Datapath Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 41-44, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Carsten F. Ball, Peter V. Kraus, Dieter A. Mlynski |
Fuzzy Partitioning applied to VLSI-Floorplanning and Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 177-180, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Tetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin'ichi Wakabayashi, Noriyoshi Yoshida |
A Floorplanning Method with Topological Constraint Manipulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, pp. 165-168, 1994, IEEE, 0-7803-1916-8. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|