Search results for "programmable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Fei Li 0003, Yizhou Lin, Lei He 0001, Deming Chen, Jason Cong	Power modeling and characteristics of field programmable gate arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
18	J. V. Millor, J. S. Fernandez	A network management approach enabling active and programmable Internets.	IEEE Netw.	2005	DBLP DOI BibTeX RDF
18	Sagi Schein, Eran Karpen, Gershon Elber	Real-time geometric deformation displacement maps using programmable hardware.	Vis. Comput.	2005	DBLP DOI BibTeX RDF	Deformation displacement mapping, Geometric texture, Graphics hardware
18	Tien Pham Van	Real-Time Video over Programmable Networked Devices.	NPC	2005	DBLP DOI BibTeX RDF
18	Paul Willmann, Hyong-youb Kim, Scott Rixner, Vijay S. Pai	An Efficient Programmable 10 Gigabit Ethernet Network Interface Card.	HPCA	2005	DBLP DOI BibTeX RDF
18	Hongbing Fan, Yu-Liang Wu	Crossbar based design schemes for switch boxes and programmable interconnection networks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	switch matrix, FPGA, routing, interconnection network, layout, crossbar, switch box
18	Luís Gomes 0001, Anikó Costa	Teaching Formal Methods Within System-on-a-Programmable-Chip Design.	MSE	2005	DBLP DOI BibTeX RDF
18	Brendan McAllister, Alan Marshall 0001, Roger F. Woods	Programmable Network Functionality for Improved QoS of Interactive Video Traffic.	Net-Con	2005	DBLP DOI BibTeX RDF	Layered MPEG-4, End-to-end delay control, Video conferencing
18	Bushar Yousef, Doan B. Hoang, Glynn Rogers	Partitioning and Differentiated Resource Allocation in Programmable Networks.	ISCC	2005	DBLP DOI BibTeX RDF
18	Mitsuaki Nakasumi	A Programmable Pipelined Queue for Approximate String Matching.	KES (4)	2005	DBLP DOI BibTeX RDF
18	Eric Lebel, Ali Assi 0001, Mohamad Sawan	Field programmable Gm-C array for wide frequency range bandpass filter applications.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Sheng-Yu Peng, Bradley A. Minch, Paul E. Hasler	A programmable floating-gate bump circuit with variable width.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
18	Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim	A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
18	Bradley R. Quinton, Steven J. E. Wilton	Concentrator access networks for programmable logic cores on SoCs.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
18	Phil Corbishley, Esther Rodríguez-Villegas	Programmable switched-current floating-gate cells.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
18	Louie Pylarinos, Khoman Phang	Low-voltage programmable gm-C filter for hearing aids using dynamic gate biasing.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Amir Hosein Kamalizad, Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka	A Programmable DSP Architecture for Wireless Communication Systems.	ASAP	2005	DBLP DOI BibTeX RDF
18	Amit Laknaur, Haibo Wang 0005	Built-In-Self-Testing Techniques for Programmable Capacitor Arrays.	ISQED	2005	DBLP DOI BibTeX RDF
18	Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell	Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays.	VTS	2005	DBLP DOI BibTeX RDF	FPAA testing, Mixed-signal test, interconnect testing, oscillation-based test
18	Christoph M. Kirsch, Marco A. A. Sanvido, Thomas A. Henzinger	A programmable microkernel for real-time systems.	VEE	2005	DBLP DOI BibTeX RDF	real time, virtual machine, operating system
18	Stéphane Simard, Rachid Beguenane, Éric Larouche, Luc Morin	A 2005 review of FPGA arithmetic (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
18	Xin Jia, Ranga Vemuri	The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture.	FCCM	2005	DBLP DOI BibTeX RDF
18	Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	Analog Switch, DC defective behaviour, DC test, open defect, bridging defect
18	Weisheng Chong, Masanori Hariyama, Michitaka Kameyama	Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits.	ISVLSI	2004	DBLP DOI BibTeX RDF
18	Michel Leong, Pedro Vasconcelos, Jorge R. Fernandes, Leonel Sousa	A programmable cellular neural network circuit.	SBCCI	2004	DBLP DOI BibTeX RDF	VLSI, cellular neural networks, microelectronics
18	Danny van Noort	A Programmable Molecular Computer in Microreactors.	DNA	2004	DBLP DOI BibTeX RDF
18	Heiko Kalte, Mario Porrmann, Ulrich Rückert 0001	System-on-Programmable-Chip Approach Enabling Online Fine-Grained 1D-Placement.	IPDPS	2004	DBLP DOI BibTeX RDF
18	Tyson S. Hall, Christopher M. Twigg, Paul E. Hasler, David V. Anderson	Developing Large-Scale Field-Programmable Analog Arrays.	IPDPS	2004	DBLP DOI BibTeX RDF
18	Elyon DeKoven, Arnold P. O. S. Vermeeren, Xi Zeng	Designing collaborative interfaces for programmable appliances: a SenSay case study.	SMC (1)	2004	DBLP DOI BibTeX RDF
18	Lawrence Cheng, Alex Galis, Arso Savanovic, Borka Jerman-Blazic, Janez Bester	Self-Management GRID Services - A Programmable Network Approach.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
18	José Franco Machado do Amaral, Jorge Luís Machado do Amaral, Cristina Costa Santini, Marco Aurélio Cavalcanti Pacheco, Ricardo Tanscheit, Moisés H. Szwarcman	Intrinsic Evolution of Analog Circuits on a Programmable Analog Multiplexer Array.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
18	Jarkko Jussila, Kari Halonen	Programmable-gain amplifiers based on AC couplings for continuous reception.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
18	Gang Xu, Jiren Yuan	A programmable analog-to-digital converter.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
18	Kamakshi Sivaramakrishnan, Ivan R. Linscott, G. Leonard Tyler	Design of multiplierless programmable linear phase narrowband-bandpass FIR filters.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
18	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	At-Speed Functional Verification of Programmable Devices.	DFT	2004	DBLP DOI BibTeX RDF
18	Alireza Hodjat, Patrick Schaumont, Ingrid Verbauwhede	Architectural Design Features of a Programmable High Throughput AES Coprocessor.	ITCC (2)	2004	DBLP DOI BibTeX RDF
18	Haibo Wang 0005, Suchitra Kulkarni, Spyros Tragoudas	On-line Testing Field Programmable Analog Array Circuits.	ITC	2004	DBLP DOI BibTeX RDF
18	Bertrand Mathieu, Yannick Carlinet, Yvon Gourhant	A Programmable Network Enabling Content Adaptation.	MATA	2004	DBLP DOI BibTeX RDF
18	Deepa Srinivasan, Wu-chang Feng	Performance Analysis of Multi-dimensional Packet Classification on Programmable Network Processors.	LCN	2004	DBLP DOI BibTeX RDF
18	Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez 0001, Antonio García 0001	Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices.	FPL	2004	DBLP DOI BibTeX RDF
18	Wim Roelandts	FPGAs and the Era of Field Programmability.	FPL	2004	DBLP DOI BibTeX RDF
18	Erik Schüler, Luigi Carro	A Low Power FPAA for Wide Band Applications.	FPL	2004	DBLP DOI BibTeX RDF
18	Young H. Cho, William H. Mangione-Smith	Deep Packet Filter with Dedicated Logic and Read Only Memories.	FCCM	2004	DBLP DOI BibTeX RDF
18	Abdel Ejnioui, N. Ranganathan	Routing on field-programmable switch matrices.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
18	Ujval J. Kapasi, Scott Rixner, William J. Dally, Brucek Khailany, Jung Ho Ahn, Peter R. Mattson, John D. Owens	Programmable Stream Processors.	Computer	2003	DBLP DOI BibTeX RDF
18	Christian Bachmeir, Peter Tabery	Scalable Diverse Protected Multicast as a Programmable Service Leveraging IP-Multicast.	NCA	2003	DBLP DOI BibTeX RDF
18	Jirí Síma	On the Complexity of Training a Single Perceptron with Programmable Synaptic Delays.	ALT	2003	DBLP DOI BibTeX RDF
18	Siva Nageswara Rao Borra, Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti 0001	A Parallel Genetic Approach to the Placement Problem for Field Programmable Gate Arrays.	IPDPS	2003	DBLP DOI BibTeX RDF
18	Tommaso Cucinotta, Marco Di Natale, David Corcoran	A Protocol for Programmable Smart Cards.	DEXA Workshops	2003	DBLP DOI BibTeX RDF
18	Le-Jeng Shiue, Vineet Goel, Jörg Peters 0001	Mesh mutation in programmable graphics hardware.	Graphics Hardware	2003	DBLP DOI BibTeX RDF
18	Ahmad Darabiha, Jonathan Rose, W. James MacLean	Video-Rate Stereo Depth Measurement on Programmable Hardware.	CVPR (1)	2003	DBLP DOI BibTeX RDF
18	Sanghoon Choi, William R. Eisenstadt, Robert M. Fox	Design of programmable embedded IF source for design self-test.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
18	Nuno F. Paulino, M. Serrazina, João Goes, Adolfo Steiger-Garção	Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
18	Tieying Zhu	CPU Schedule in Programmable Routers: Virtual Service Queuing with Feedback Algorithm.	GCC (2)	2003	DBLP DOI BibTeX RDF
18	Jo Ueyama, Geoff Coulson, Gordon S. Blair, Stefan Schmid 0002, Antônio Tadeu A. Gomes, Ackbar Joolia, Kevin Lee	A Globally-Applied Component Model for Programmable Networking.	IWAN	2003	DBLP DOI BibTeX RDF
18	Ian Wakeman, David Ellis, Tim Owen, Julian Rathke, Des Watson	Risky Business: Motivations for Markets in Programmable Networks.	IWAN	2003	DBLP DOI BibTeX RDF
18	James Moscola, John W. Lockwood, Ronald Prescott Loui, Michael Pachos	Implementation of a Content-Scanning Module for an Internet Firewall.	FCCM	2003	DBLP DOI BibTeX RDF
18	Bart Kienhuis, Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers	A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF	Y-chart approach, Architecture Template, Stack of Y-charts, Abstraction Pyramid, Embedded Systems, Design Space Exploration
18	Patrick Lysaght	Field Programmable Systems.	HiPC	2002	DBLP DOI BibTeX RDF
18	Chia-Lin Yang, Alvin R. Lebeck	A Programmable Memory Hierarchy for Prefetching Linked Data Structures.	ISHPC	2002	DBLP DOI BibTeX RDF
18	Shao-Yi Chien, Yu-Wen Huang, Liang-Gee Chen	A hardware accelerator for video segmentation using programmable morphology PE array.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
18	Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.	IOLTW	2002	DBLP DOI BibTeX RDF
18	Li Shang, Alireza Kaviani, Kusuma Bathala	Dynamic power consumption in Virtex[tm]-II FPGA family.	FPGA	2002	DBLP DOI BibTeX RDF
18	Gordon J. Brebner	Multithreading for Logic-Centric Systems.	FPL	2002	DBLP DOI BibTeX RDF
18	Javier Ramírez 0001, Antonio García 0001	U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation.	FPL	2002	DBLP DOI BibTeX RDF
18	Sylvain Poussier, Hassan Rabah, Serge Weber	SOPC-based Embedded Smart Strain Gage Sensor.	FPL	2002	DBLP DOI BibTeX RDF
18	Joshua D. Walstrom, Jeffrey J. Cook, Derek B. Gottlieb, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter	The Design of the Amalgam Reconfigurable Cluster.	FCCM	2002	DBLP DOI BibTeX RDF
18	Adrian Stoica, Ricardo Salem Zebulum, Didier Keymeulen, Raoul Tawel, Taher Daud, Anil Thakoor	Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
18	Santanu Dutta	Architecture and design of NX-2700: a programmable single-chip HDTV all-format-decode-and-display processor.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
18	Craig B. Zilles, Gurindar S. Sohi	A Programmable Co-Processor for Profiling.	HPCA	2001	DBLP DOI BibTeX RDF
18	Jörg Langeheine, Joachim Becker, Simon Fölling, Karlheinz Meier, Johannes Schemmel	Initial Studies of a New VLSI Field Programmable Transistor Array.	ICES	2001	DBLP DOI BibTeX RDF
18	Chun Lu, Bingxue Shi, Lu Chen	A programmable on-chip BP learning neural network with enhanced neuron characteristics.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
18	Xiaoqiang Shou, Michael M. Green	A programmable VHF CMOS read-channel continuous-time filter with on-chip tuning.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
18	Sree Ganesan, Ranga Vemuri	Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems.	ARVLSI	2001	DBLP DOI BibTeX RDF
18	Erik Lindholm, Mark J. Kligard, Henry P. Moreton	A user-programmable vertex engine.	SIGGRAPH	2001	DBLP DOI BibTeX RDF	graphics hardware, graphics systems
18	Toru Hasegawa, Shigehiro Ano, Koji Nakao, Fumito Kubota	Programmable Remote Traffic Monitoring Method Using Active Network Approach.	IWAN	2001	DBLP DOI BibTeX RDF
18	Carlos Macián	The Octopus Network Model: Opening Up the Internet to Active and Programmable Network Implementations.	IWAN	2001	DBLP DOI BibTeX RDF
18	Ann Garrison Darrin, Richard Conde, Bobbie Chern, Phil Luers, Steve Jurczyk, Carl Mills	Adaptive Instrument Module: Space Instrument Controller "brain" Through Programmable Logic Devices.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
18	Gordon J. Brebner, Oliver Diessel	Chip-Based Reconfigurable Task Management.	FPL	2001	DBLP DOI BibTeX RDF
18	L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia	A Scheduler ASIC for a Programmable Packet Switch.	IEEE Micro	2000	DBLP DOI BibTeX RDF
18	Tong Liu 0007, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	Testing and testable designs for one-time programmable FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
18	Richard Evans, Jonathan D. Moffett	Derivation of Safety Targets for the Random Failure of Programmable Vehicle Based Systems.	SAFECOMP	2000	DBLP DOI BibTeX RDF
18	Craig Slorach, Ken Sharman	The Design and Implementation of Custom Architectures for Evolvable Hardware Using Off-the-Shelf Programmable Devices.	ICES	2000	DBLP DOI BibTeX RDF
18	Hamish Fallside, Michael John Sebastian Smith	Internet Connected FPL.	FPL	2000	DBLP DOI BibTeX RDF
18	Bernardo Kastrup, Jeroen Trum, Orlando Moreira, Jan Hoogerbrugge, Jef L. van Meerbergen	Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis.	FPL	2000	DBLP DOI BibTeX RDF
18	Alfred Blaickner, O. Nagy, Herbert Grünbacher	Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic.	FPL	2000	DBLP DOI BibTeX RDF	digital receiver, FPGA, synchronization, Wireless, hardware/software co-design, software radio
18	Srini Krishnamoorthy, Sriram Swaminathan, Russell Tessier	Area-Optimized Technology Mapping for Hybrid FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
18	Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley	Reconfigurable Array Media Processor (RAMP).	FCCM	2000	DBLP DOI BibTeX RDF
18	Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja	The design of an SRAM-based field-programmable gate array. I. Architecture.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
18	Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja	The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
18	Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang	A Programmable BIST Core for Embedded DRAM.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF
18	Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici	Realization of a programmable rank-order filter architecture using capacitive threshold logic gates.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
18	B. E. Duewer, John M. Wilson 0002, D. A. Winick, Paul D. Franzon	MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications.	ARVLSI	1999	DBLP DOI BibTeX RDF	Variable Capacitors, Programable Interconnect, RF Switching, Digital Switching, Bistable Devices, MEMS, Crossbar, Capacitive Coupling
18	Wenyi Feng, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi	Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources.	DFT	1999	DBLP DOI BibTeX RDF	Online Repair, Reassignment, Fault Tolerance, FPGA, Reconfiguration
18	Laurent Moll, Mark Shand, Alan Heirich	Sepia: Scalable 3D Compositing Using PCI Pamette.	FCCM	1999	DBLP DOI BibTeX RDF
18	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001	Low-power realization of FIR filters on programmable DSPs.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
18	Daniel Mange, Eduardo Sanchez, André Stauffer, Gianluca Tempesti, Pierre Marchal, Christian Piguet	Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
18	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001	Extensions to Programmable DSP architectures for Reduced Power Dissipation.	VLSI Design	1998	DBLP DOI BibTeX RDF	Low Power Design, DSP Architecture
18	Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith	Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
18	Samary Baranov	CAD System for ASM and FSM Synthesis.	FPL	1998	DBLP DOI BibTeX RDF