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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 363 occurrences of 173 keywords
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Results
Found 524 publication records. Showing 524 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
11 | Yen-Tai Lai, Ping-Tsung Wang |
Hierarchical interconnection structures for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(2), pp. 186-196, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
11 | Andrew Lim 0001, Venkat Thanvantri, Sartaj Sahni |
Planar topological routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6), pp. 651-656, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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11 | Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan 0001 |
Algorithms for an FPGA switch module routing problem with application to global routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1), pp. 32-46, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
11 | Maggie Zhiwei Kang, Wayne Wei-Ming Dai, Tom Dillinger, David P. LaPotin |
Delay bounded buffered tree construction for timing driven floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 707-712, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Total Wire Length, DBB-tree, SPT, Floorplanning, Buffer Insertion, Delay Bounds, Elmore Delay, MST |
11 | Chingwei Yeh, Chi-Shong Wang |
On the integration of partitioning and global routing for rectilinear placement problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1), pp. 83-91, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
11 | Chunghee Kim, Hyunchul Shin |
A performance-driven logic emulation system: FPGA network design and performance-driven partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5), pp. 560-568, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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11 | Robert C. Carden IV, Jianmin Li, Chung-Kuan Cheng |
A global router with a theoretical bound on the optimal solution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2), pp. 208-216, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
11 | Dongsheng Wang 0012, Ernest S. Kuh |
Performance-Driven Interconnect Global Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 132-136, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
11 | Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns |
Placement and routing tools for the Triptych FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(4), pp. 473-482, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
11 | Vijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai |
Design of FPGAs with Area I/O for Field Programmable MCM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 17-23, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
11 | Tianxiong Xue, Ernest S. Kuh |
Post routing performance optimization via multi-link insertion and non-uniform wiresizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 575-580, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
post routing performance optimization, link insertion and wiresizing, delay skew, routing area, delay |
11 | Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel |
Block-oriented programmable design with switching network interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(1), pp. 45-53, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
11 | Jagannathan Narasimham, Kazuo Nakajima, Chong S. Rim, Anton T. Dahbura |
Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8), pp. 976-986, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
11 | Massoud Pedram, Bahman S. Nobandegani, Bryan Preas |
Design and analysis of segmented routing channels for row-based FPGA's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12), pp. 1470-1479, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
11 | Suphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin |
An adaptive timing-driven placement for high performance VLSIs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10), pp. 1488-1498, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
11 | Kurt Mehlhorn, Stefan Näher |
A faster compaction algorithm with automatic jog insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2), pp. 158-166, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
11 | Patrick Groeneveld |
A multiple layer contour-based gridless channel router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12), pp. 1278-1288, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
11 | John D. Provence, S. Naganathan |
A parallel distributed processing approach to VLSI global routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPDP ![In: Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, SPDP 1990, Dallas, Texas, USA, December 9-13, 1990., pp. 283-286, 1990, IEEE Computer Society, 0-8186-2087-0. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
11 | Suphachai Sutanthavibul, Eugene Shragowitz |
An Adaptive Timing-Driven Layout for High Speed VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 90-95, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
11 | Joseph F. JáJá, S. Alice Wu |
On routing two-terminal nets in the presence of obstacles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(5), pp. 563-570, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
11 | G. D. Adams, Carlo H. Séquin |
Template Style Considerations for Sea-of-Gates Layout Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 31-36, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
11 | Ali A. Minai, Ronald D. Williams, F. W. Blake |
A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC Layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 770-776, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
11 | Vijay S. Bobba, J. W. Smith |
A parameter-driven router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 810-818, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
11 | Rostam Joobbani, Daniel P. Siewiorek |
WEAVER: a knowledge-based routing expert. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 266-272, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
OPS5 |
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