Search results for "superscalar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Norman Kojima, Yukiko Parameswar, Christian Klingner, Yukio Ohtaguro, Masataka Matsui, Shigeaki Iwasa, Tatsuo Teruyama, Takayoshi Shimazawa, Hideki Takeda, Kouji Hashizume, Haruyuki Tago, Masaaki Yamada	Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor.	ASP-DAC	2000	DBLP DOI BibTeX RDF
17	Murali Annavaram, Gary S. Tyson, Edward S. Davidson	Instruction overhead and data locality effects in superscalar processors.	ISPASS	2000	DBLP DOI BibTeX RDF
17	Tatiana Gadelha Serra dos Santos, Sergio Bampi	Analyzing Instruction Prefetch Schemes in Superscalar Architectures.	PDPTA	2000	DBLP BibTeX RDF
17	Mark Wolff, Linda M. Wills	SATSim: a superscalar architecture trace simulator using interactive animation.	WCAE	2000	DBLP DOI BibTeX RDF
17	Hadi Shahriar Shahhoseini, Madjid Naderi, S. Nemati	Achieving the best performance on superscalar processors.	SIGARCH Comput. Archit. News	1999	DBLP DOI BibTeX RDF
17	John Clouser, Mark Matson, R. Badeau, R. Dupcak, Sridhar Samudrala, Randy L. Allmon, N. Fairbanks	A 600-MHz superscalar floating-point processor.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
17	Ruey-Liang Ma, Chung-Ping Chung	Reducing Memory Traffic and Accelerting Prolog Execution in a Superscalar Prolog System.	J. Inf. Sci. Eng.	1999	DBLP BibTeX RDF
17	Jongbok Lee, Soo-Mook Moon, Wonyong Sung	An enhanced two-level adaptive multiple branch prediction for superscalar processors.	J. Syst. Archit.	1999	DBLP DOI BibTeX RDF
17	Pradip Bose, Sunil Kim, Francis P. O'Connell, William A. Ciarfella	Bounds modelling and compiler optimizations for superscalar performance tuning.	J. Syst. Archit.	1999	DBLP DOI BibTeX RDF
17	Jurij Silc, Borut Robic, Theo Ungerer	Processor architecture - from dataflow to superscalar and beyond.		1999	RDF
17	Lucian N. Vintan, Cristian Armat, Gordon B. Steven	The impact of cache organisation on the instruction issue rate of a superscalar processor.	PDP	1999	DBLP DOI BibTeX RDF
17	Eric Rotenberg, Quinn Jacobson, James E. Smith 0001	A Study of Control Independence in Superscalar Processors.	HPCA	1999	DBLP DOI BibTeX RDF
17	Miroslav N. Velev, Randal E. Bryant	Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic.	CHARME	1999	DBLP DOI BibTeX RDF
17	Oleg Bessonov, Dominique Fougère, Ky Dang Quoc, Bernard Roux	Methods for Achieving Peak Computational Rates for Linear Algebra Operations on Superscalar RISC Processors.	PaCT	1999	DBLP DOI BibTeX RDF
17	Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero	Adding a vector unit to a superscalar processor.	International Conference on Supercomputing	1999	DBLP DOI BibTeX RDF
17	Omar Hammami	Neural Network Classifiers Execution on Superscalar Microprocessors.	ISHPC	1999	DBLP DOI BibTeX RDF
17	Kanad Ghose, Milind B. Kamble	Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation.	ISLPED	1999	DBLP DOI BibTeX RDF	power estimation, low power caches
17	Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen	Superscalar Processor Validation at the Microarchitecture Level.	VLSI Design	1999	DBLP DOI BibTeX RDF
17	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh	A Comparison of Scalable Superscalar Processors.	SPAA	1999	DBLP DOI BibTeX RDF
17	Sanjay J. Patel	Trace cache design for wide-issue superscalar processors.		1999	RDF
17	Graham P. Jones	The limits of a decoupled out-of-order superscalar architecture.		1999	RDF
17	Hajime Kubosawa, Hiromasa Takahashi, Satoshi Ando, Yoshimi Asada, Akira Asato, Atsuhiro Suga, Michihide Kimura, Naoshi Higaki, Hideo Miyake, Tomio Sato, Hideaki Anbutsu, Toshitaka Tsuda, Tetsuo Yoshimura, Isao Amano, Mutsuaki Kai, Shin Mitarai	A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
17	Kazumasa Suzuki, Tomohisa Arai, Kouhei Nadehara, Ichiro Kuroda	V830R/AV: embedded multimedia superscalar RISC processor.	IEEE Micro	1998	DBLP DOI BibTeX RDF
17	Steven Wallace, Nader Bagherzadeh	A scalable register file architecture for superscalar processors.	Microprocess. Microsystems	1998	DBLP DOI BibTeX RDF
17	José González 0002, Antonio González 0001	Data value speculation in superscalar processors.	Microprocess. Microsystems	1998	DBLP DOI BibTeX RDF
17	Philip H. Sweany, Steve Carr 0001, Brett L. Huber	Compiler Optimization for Superscalar Systems: Global Instruction Scheduling without Copies.	Digit. Tech. J.	1998	DBLP BibTeX RDF
17	Venkata Krishnan, Josep Torrellas	An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors.	IEEE PACT	1998	DBLP DOI BibTeX RDF
17	Soner Önder, Rajiv Gupta 0001	Superscalar Execution with Direct Data Forwarding.	IEEE PACT	1998	DBLP DOI BibTeX RDF
17	Fred G. Gustavson, André Henriksson, Isak Jonsson, Bo Kågström, Per Ling	Superscalar GEMM-based Level 3 BLAS - The On-going Evolution of a Portable and High-Performance Library.	PARA	1998	DBLP DOI BibTeX RDF
17	Joon-Seok Kim 0002, Sun Kook Yoo, Sung-Wook Park, Nam Hoon Jung, Woo-Suk Ko, Keun-Sup Lee, Dae Hee Youn	4-way superscalar DSP processor for audio codec applications.	ICASSP	1998	DBLP DOI BibTeX RDF
17	J. Alcântara, V. C. Alves, E. Filho	Designing the Dispatch Stage of a Superscalar Microprocessor.	SBCCI	1998	DBLP DOI BibTeX RDF
17	M. Srinivas, Alexandru Nicolau	Analyzing the Individual/Combined Effects of Speculative and Guarded Execution on a Superscalar Architecture.	IPPS/SPDP	1998	DBLP DOI BibTeX RDF
17	S.-K. Cheng, R.-Ming Shiu, Jean Jyh-Jiun Shann	Decoding Unit with High Issue Rate for X86 Superscalar Microprocessors.	ICPADS	1998	DBLP DOI BibTeX RDF
17	Mark Matson, Dan Bailey, Shane L. Bell, Larry L. Biro, Steve Butler, John Clouser, Jim Farrell, Mike Gowan, Donald A. Priore, Kathryn Wilcox	Circuit implementation of a 600 MHz superscalar RISC microprocessor.	ICCD	1998	DBLP DOI BibTeX RDF
17	Ing-Jer Huang, Tzu-Chin Peng	Analysis of ×86 instruction set usage for DOS/Windows applications and its implication on superscalar design.	ICCD	1998	DBLP DOI BibTeX RDF
17	Francisca Quintana, Roger Espasa, Mateo Valero	An ISA Comparison Between Superscalar and Vector Processors.	VECPAR	1998	DBLP DOI BibTeX RDF
17	Chris Basoglu, Woobin Lee, Yongmin Kim 0001	An Efficient FFT Algorithm for Superscalar and VLIW Processor Architectures.	Real Time Imaging	1997	DBLP DOI BibTeX RDF
17	Cliff A. Maier, James A. Markevitch, Cheryl Senter Brashears, Tim Sippel, Earl T. Cohen, Jim Blomgren, James G. Ballard, Jay Pattin, Viki Moldenhauer, Jeffrey A. Thomas, George Taylor	A 533-MHz BiCMOS superscalar RISC microprocessor.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
17	Dezsö Sima	Superscalar instruction issue.	IEEE Micro	1997	DBLP DOI BibTeX RDF
17	José M. Pérez Villadeamigo, Santiago Rodríguez de la Fuente, Rafael Méndez Cavanillas, M. Isabel García Clemente	The em88110: emulating a superscalar processor.	ACM SIGCSE Bull.	1997	DBLP DOI BibTeX RDF
17	Allen Leung, Krishna V. Palem, Cristian Ungureanu	Run-Time versus Compile-Time Instruction Scheduling in Superscalar (RISC) Processors: Performance and Trade-Off.	J. Parallel Distributed Comput.	1997	DBLP DOI BibTeX RDF
17	Gordon B. Steven, Bruce Christianson, Roger Collins, Richard D. Potter, Fleur L. Steven	A superscalar architecture to exploit instruction level parallelism.	Microprocess. Microsystems	1997	DBLP DOI BibTeX RDF
17	Isidoro Urriza, J. I. García, Denis Navarro	Instruction issue system for superscalar processors.	PDP	1997	DBLP BibTeX RDF
17	A. Richard Kennedy, Mike Alexander, Eric Fiene, Jose A. Lyon, Belli Kuttanna, Rajesh Patel, Mydung N. Pham, Michael Putrino, Cody Croxton, Suzanne Litch, Brad Burgess	A G3 PowerPC™ superscalar low-power microprocessor.	COMPCON	1997	DBLP DOI BibTeX RDF
17	Prasenjit Biswas, Andy Freeman, Kouji Yamada, Norio Nakagawa, Kunio Uchiyama	Functional verification of the superscalar SH-4 microprocessor.	COMPCON	1997	DBLP DOI BibTeX RDF
17	James E. Bennett, Michael J. Flynn	Prediction Caches for Superscalar Processors.	MICRO	1997	DBLP DOI BibTeX RDF	Prediction cache, Dynamic scheduling, Memory latency, Victim cache, Stream buffer
17	Yuan C. Chou, Daniel P. Siewiorek, John Paul Shen	A Realistic Study on Multithreaded Superscalar Processor Design.	Euro-Par	1997	DBLP DOI BibTeX RDF
17	Jongbok Lee, Wonyong Sung, Soo-Mook Moon	An Enhanced Two-Level Adaptive Multiple Branch Prediction for Superscalar Processors.	Euro-Par	1997	DBLP DOI BibTeX RDF
17	Rong-Yuh Hwang	An Efficient Technique of Instruction Scheduling on a Superscalar-Based Mulprocessor.	IPPS	1997	DBLP DOI BibTeX RDF	FLASH multiprocessor, block data transfer, multiple communication protocols, embedded protocol processor, protocol, shared memory, prefetching, cache storage, FLASH, cache coherence protocol, multiprocessor architecture, MAGIC
17	Toni Juan, Juan J. Navarro, Olivier Temam	Data Caches for Superscalar Processors.	International Conference on Supercomputing	1997	DBLP DOI BibTeX RDF
17	Andrew Davey, David Lloyd	An Evaluation of Asynchronous and Synchronous Design for Superscalar Architectures.	ICCD	1997	DBLP DOI BibTeX RDF
17	Shusuke Okamoto, Masahiro Sowa	Intruction Fetch Mechanism for PN-Superscalar.	PDPTA	1997	DBLP BibTeX RDF
17	Chung-Ho Chen, Akida Wu	An enhanced DLX-based superscalar system simulator.	WCAE@HPCA	1997	DBLP DOI BibTeX RDF
17	Kyle L. Nelson, Alok Jain, Randal E. Bryant	Formal Verification of a Superscalar Execution Unit.	DAC	1997	DBLP DOI BibTeX RDF
17	Nader Vasseghi, Kenneth Yeager, Egino Saito, Mahdi Seddighnezhad	200-MHz superscalar RISC microprocessor.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
17	Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto	2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
17	Kenneth C. Yeager	The Mips R10000 superscalar microprocessor.	IEEE Micro	1996	DBLP DOI BibTeX RDF
17	David H. Albonesi, Israel Koren	A Mean Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques.	Int. J. Parallel Program.	1996	DBLP DOI BibTeX RDF
17	Martti Forsell	Minimal pipeline architecture - an alternative to superscalar architecture.	Microprocess. Microsystems	1996	DBLP DOI BibTeX RDF
17	Chandrasekhar Narayanaswami 0001	Superscalar RISC machines, straight-line programs, and graphics.	Vis. Comput.	1996	DBLP DOI BibTeX RDF	Straight-line coding, Branch reduction, Processor architecture, Graphics programs
17	M. Loikkanen, Nader Bagherzadeh	A fine-grain multithreading superscalar architecture.	IEEE PACT	1996	DBLP DOI BibTeX RDF
17	P. Tinumalai, Boris Beylin, Krishna Subramanian 0003	The design of a modulo scheduler for a superscalar RISC processor.	IEEE PACT	1996	DBLP DOI BibTeX RDF
17	Manoj Franklin	Incorporating fault tolerance in superscalar processors.	HiPC	1996	DBLP DOI BibTeX RDF
17	Allen Leung, Krishna V. Palem, Cristian Ungureanu	Run-time versus compile-time instruction scheduling in superscalar (RISC) processors: performance and tradeoffs.	HiPC	1996	DBLP DOI BibTeX RDF
17	Harvey J. Wasserman	Benchmark Tests on the Digital Equipment Corporation Alpha AXP 21164-based AlphaServer 8400, Including a Comparison of Optimized Vector and Superscalar Processing.	International Conference on Supercomputing	1996	DBLP DOI BibTeX RDF
17	Bryan Black, Andrew S. Huang, Mikko H. Lipasti, John Paul Shen	Can Trace-Driven Simulators Accurately Predict Superscalar Performance?	ICCD	1996	DBLP DOI BibTeX RDF
17	Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes	Reducing State Loss For Effective Trace Sampling of Superscalar Processors.	ICCD	1996	DBLP DOI BibTeX RDF
17	Anthony C. J. Fox, Neal A. Harman	An Algebraic Model of Correctness for Superscalar Microprocessors.	FMCAD	1996	DBLP DOI BibTeX RDF
17	James J. Carrig Jr., Gerard G. L. Meyer	A Three-Parameter Fast Givens QR Algorithm for Superscalar Processors.	ICPP, Vol. 2	1996	DBLP DOI BibTeX RDF
17	Shusuke Okamoto, Masahiro Sowa	Hybrid Processor Based on VLIW and PN-Superscalar.	PDPTA	1996	DBLP BibTeX RDF
17	Kenneth M. Wilson, Kunle Olukotun, Mendel Rosenblum	Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors.	ISCA	1996	DBLP DOI BibTeX RDF
17	Jerry R. Burch	Techniques for Verifying Superscalar Microprocessors.	DAC	1996	DBLP DOI BibTeX RDF
17	Joe Circello, Greg Edgington, Dan McCarthy, James Gay, David Schimke, Steven Sullivan, Richard Duerden, Chris Hinds, Danny Marquette, Lal Sood, Al Crouch, Daniel Chow	The superscalar architecture of the MC68060.	IEEE Micro	1995	DBLP DOI BibTeX RDF
17	John H. Edmondson, Paul I. Rubinfeld, Ronald P. Preston, Vidya Rajagopalan	Superscalar instruction execution in the 21164 Alpha microprocessor.	IEEE Micro	1995	DBLP DOI BibTeX RDF
17	Christian Iseli, Eduardo Sanchez	Spyder: A SURE (SUperscalar and REconfigurable) processor.	J. Supercomput.	1995	DBLP DOI BibTeX RDF
17	Pohua P. Chang, Daniel M. Lavery, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu	The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF
17	Steven Wallace, Nader Bagherzadeh	Performance issues of a superscalar microprocessor.	Microprocess. Microsystems	1995	DBLP DOI BibTeX RDF
17	Michael Kantrowitz, Lisa M. Noack	Functional Verification of a Multiple-issue, Pipelined, Superscalar Alpha Processor - the Alpha 21164 CPU Chip	Digit. Tech. J.	1995	DBLP BibTeX RDF
17	Neng-Pin Lu, Chung-Ping Chung	Memory System Design in Superscalar Processing.	Int. J. High Speed Comput.	1995	DBLP DOI BibTeX RDF
17	James E. Smith, Gurindar S. Sohi	The microarchitecture of superscalar processors.	Proc. IEEE	1995	DBLP DOI BibTeX RDF
17	Ruey-Liang Ma, Chung-Ping Chung	Periodic Adaptive Branch Prediction and its Application in Superscalar Processing in Prolog.	Comput. J.	1995	DBLP DOI BibTeX RDF
17	Chikako Nakanishi, Hideki Ando, Hirohisa Machida, Masao Nakaya	Code scheduling on a superscalar processor: SARCH.	Syst. Comput. Jpn.	1995	DBLP DOI BibTeX RDF
17	Wayne Yamamoto, Mario Nemirovsky	Increasing superscalar performance through multistreaming.	PACT	1995	DBLP BibTeX RDF
17	David H. Albonesi, Israel Koren	An analytical model of high performance superscalar-based multiprocessors.	PACT	1995	DBLP BibTeX RDF
17	David Levitan, Thomas Thomas, Paul Tu	The PowerPC 620 Microprocessor: A High Performance Superscalar RISC Microprocessor.	COMPCON	1995	DBLP DOI BibTeX RDF
17	Dale Greenley, J. Bauman, D. Chang, Dennis Chen, R. Eltejaein, Philip A. Ferolito, P. Fu, Robert B. Garner, D. Greenhill, H. Grewal, Kalon Holdbrook, B. Kim, Leslie Kohn, Hang Kwan, M. Levitt, Guillermo Maturana, D. Mrazek, Chitresh Narasimhaiah, Kevin Normoyle, N. Parveen, P. Patel, A. Prabhu, Marc Tremblay, Michelle Wong, L. Yang, Krishna Yarlagadda, Robert K. Yu, Robert Yung, Gregory B. Zyner	UltraSPARC: The Next Generation Superscalar 64-bit SPARC.	COMPCON	1995	DBLP DOI BibTeX RDF
17	Trung A. Diep, John Paul Shen	Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures.	FTCS	1995	DBLP DOI BibTeX RDF
17	Nirmal R. Saxena, Chien Chen, Ravi Swami, Hideki Osone, Shalesh Thusoo, David Lyon, David Chang, Anand Dharmaraj, Niteen Patkar, Yizhi Lu, Ben Chia	Error Detection and Handling in a Superscalar, Speculative Out-of-Order Execution Processor System.	FTCS	1995	DBLP DOI BibTeX RDF
17	Luis A. Lozano, Guang R. Gao	Exploiting short-lived variables in superscalar processors.	MICRO	1995	DBLP DOI BibTeX RDF
17	Simonjit Dutta, Manoj Franklin	Control flow prediction with tree-like subgraphs for superscalar processors.	MICRO	1995	DBLP DOI BibTeX RDF
17	Subbarao Palacharla, James E. Smith 0001	Decoupling integer execution in superscalar processors.	MICRO	1995	DBLP DOI BibTeX RDF
17	Shlomo Weiss	Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors.	HPCA	1995	DBLP DOI BibTeX RDF
17	Rastislav Bodík, Rajiv Gupta 0001	Array Data Flow Analysis for Load-Store Optimizations in Superscalar Architectures.	LCPC	1995	DBLP DOI BibTeX RDF
17	Manoj Franklin	A study of time redundant fault tolerance techniques for superscalar processors.	DFT	1995	DBLP DOI BibTeX RDF
17	Miroslav Tuma, Miroslav Rozlozník	On the Efficiency of Superscalar and Vector Computer for some Problems in Scientif Computing.	SOFSEM	1995	DBLP DOI BibTeX RDF
17	Roger Collins	Exploiting instruction-level parallelism in superscalar architecture.		1995	RDF
17	Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura	A 120-MHz BiCMOS superscalar RISC processor.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
17	Gianfranco Gerosa, Sonya Gary, Carl Dietz, Dac Pham, Kathy Hoover, Jose Alvarez, Hector Sanchez, Pete Ippolito, Tai Ngo, Suzanne Litch, Jim Eno, Jim Golab, Neil Vanderschaaf, Jim Kahle	A 2.2 W, 80 MHz superscalar RISC microprocessor.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
17	Robert F. Krick, Lawrence T. Clark, Daniel J. Deleganes, Keng L. Wong, Roshan Fernando, Goutam Debnath, Jashojiban Banik	A 150 MHz 0.6 μm BiCMOS superscalar microprocessor.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
17	John Lenell, Nader Bagherzadeh	A performance comparison of several superscalar processor models with a VLIW processor.	Microprocess. Microsystems	1994	DBLP DOI BibTeX RDF