Search results for "switch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez 0002, José Flich, Francisco J. Quiles 0001, José Duato	A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination.	IEEE Trans. Parallel Distributed Syst.	2009	DBLP DOI BibTeX RDF
19	Norman C. Beaulieu	Switching Rates of Selection Diversity and Switch-And-Stay Diversity.	ICC	2008	DBLP DOI BibTeX RDF
19	Beibei Wang 0001, Chia-Chin Chong, Fujio Watanabe, K. J. Ray Liu	Dynamic Frequency-Intelligent Reserve-and-Switch Technique (D-FIRST) to Combat Inter-Operator Interference.	ICC	2008	DBLP DOI BibTeX RDF
19	Jiaxin Li, Ning Deng 0002, Caixia Liu, Mengxiao Liu, Zuo Wang, Qi Zuo	FG-NC: A Schedule Algorithm of Designing Concurrent Multi-direction Data Switch Structure.	ICYCS	2008	DBLP DOI BibTeX RDF
19	Xiangbin Cheng, Jun Bi, Xing Li	Swing - A Novel Mechanism Inspired by Shim6 Address-Switch Conception to Limit the Effectiveness of DoS Attacks.	ICN	2008	DBLP DOI BibTeX RDF	IPv6, Shim6, DoS attack
19	Xiaolin Wang, Yan Cai 0002, Sheng Xiao, Weibo Gong	A Three-Stage Load-Balancing Switch.	INFOCOM	2008	DBLP DOI BibTeX RDF
19	Anchao Cheng, Xin Yao 0005, Lianguo Duan	Design and Implementation of Integrated Services Switch Simulation Model Based on ATM-MPLS.	CSSE (2)	2008	DBLP DOI BibTeX RDF
19	Pekka Jääskeläinen, Pertti Kellomäki, Jarmo Takala, Heikki Kultala, Mikael Lepistö	Reducing Context Switch Overhead with Compiler-Assisted Threading.	EUC (2)	2008	DBLP DOI BibTeX RDF
19	Charbel J. Akl, Magdy A. Bayoumi	Feedback-Switch Logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static CMOS Circuit Family.	ISQED	2008	DBLP DOI BibTeX RDF	circuit family, low-power, high-speed
19	Ilias Iliadis, Nikolaos Chrysos, Cyriel Minkenberg	Performance evaluation of the Data Vortex photonic switch.	IEEE J. Sel. Areas Commun.	2007	DBLP DOI BibTeX RDF
19	Matthieu Gallet, Yves Robert, Frédéric Vivien	Scheduling Communication Requests Traversing a Switch: Complexity and Algorithms.	PDP	2007	DBLP DOI BibTeX RDF
19	Shuibing He, Dan Feng	An Object-based Storage Controller Based on Switch Fabric.	IEEE NAS	2007	DBLP DOI BibTeX RDF
19	Onur Alparslan, Shin'ichi Arakawa, Masayuki Murata 0001	Switch Architectures For Small-buffered Optical Packet Switched Networks.	ISCC	2007	DBLP DOI BibTeX RDF
19	Amin Farajianzadeh, Siavash Khorsandi	Toward a Differentiated-Service Enabled Parallel Packet Switch.	ISCC	2007	DBLP DOI BibTeX RDF
19	Hani H. Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.	Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine.	ICCD	2007	DBLP DOI BibTeX RDF
19	Ahmad Patooghy, Mahdi Fazeli, Seyed Ghassem Miremadi	A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips.	PRDC	2007	DBLP DOI BibTeX RDF	SEU-Tolerance, Power Consumption, NoC
19	Theofanis Orphanoudakis, Andreas Drakos, Chris Matrakidis, Christina Tanya Politi, Alexandros A. Stavdas	An Efficient Optical Switch Architecture with Controlled Latency for GRID Networks.	ICNS	2007	DBLP DOI BibTeX RDF	scheduling, GRID, OBS, optical switching, OPS
19	Guillem Femenias	Performance Analysis of Generalized Sort, Switch, and Examine Combining.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
19	Alessio Filippi, Sri Andari Husen, Stan Baggen	Automatic switch between static and mobile operation modes in DVB-T/H receivers.	VTC Spring	2006	DBLP DOI BibTeX RDF
19	Ana Busic, Mouad Ben Mamoun, Jean-Michel Fourneau	Modeling Fiber Delay Loops in an All Optical Switch.	QEST	2006	DBLP DOI BibTeX RDF
19	Antônio Marcos Alberti, Sebastião R. de Aguiar Filho, Anilton S. Garcia	Modeling, Simulation and Performance Evaluation for a CIOQ Switch Architecture.	Annual Simulation Symposium	2006	DBLP DOI BibTeX RDF
19	Kostas Siozios, Dimitrios Soudris	Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures.	FPL	2006	DBLP DOI BibTeX RDF
19	Chuan-Ching Sue, Wei-Ren Chen, Chin-Yu Huang	Design and Analysis of a Fully Non-blocking Quantum Switch.	ICICIC (2)	2006	DBLP DOI BibTeX RDF
19	Renjie Pi, Xiaosu Zhan, Yue Ma	Design a Transparent MGCP Media Switch.	CSCWD	2006	DBLP DOI BibTeX RDF
19	Jae-Sung Kong, Sang-Heon Kim, Jang-Kyoo Shin, Minho Lee 0001	An Artificial Retina Chip Using Switch-Selective Resistive Network for Intelligent Sensor Systems.	ICIC (3)	2006	DBLP DOI BibTeX RDF
19	Vijay Shanker Tripathi, C. B. Tripathi, Sudarshan Tiwari	Performance Evaluation of a Fault-Tolerant Switch for Next Generation Computer Networks.	ICPADS (2)	2006	DBLP DOI BibTeX RDF
19	Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama	Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.	ISMVL	2006	DBLP DOI BibTeX RDF
19	Y. Toyosaki, Tetsushi Ueta, Takuji Kousaka	Switch synchronizing delayed feedback control for piecewise linear systems.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Daewook Kim, Manho Kim, Gerald E. Sobelman	DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti	A model for the distortion due to switch on-resistance in sample-and-hold circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Josh Carnes, Un-Ku Moon	The effect of switch resistance on pipelined ADC MDAC settling time.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Björn Griese, Mario Porrmann	A Reconfigurable Ethernet Switch for Self-Optimizing Communication Systems.	BICC	2006	DBLP DOI BibTeX RDF
19	Zhiyu Liu, Volkan Kursun	Leakage Biased Sleep Switch Domino Logic.	ISQED	2006	DBLP DOI BibTeX RDF	gate oxide tunneling, sleep mode, Domino logic, subthreshold leakage current, dual threshold voltage
19	Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano	Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet.	ICPP	2006	DBLP DOI BibTeX RDF
19	P. Sritakaew, A. Sangswang	Reliability Improvement of a Distribution System Using PV Grid Connected System with Tie Switch.	APCCAS	2006	DBLP DOI BibTeX RDF
19	Yen-Wen Chen	Study of LSP arrangement schemes in label switch networks.	Int. J. Netw. Manag.	2005	DBLP DOI BibTeX RDF
19	Yu Cao 0001, Xiaodong Yang, Xuejue Huang, Dennis Sylvester	Switch-factor based loop RLC modeling for efficient timing analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
19	Roberto Rojas-Cessa, Eiji Oki, H. Jonathan Chao	On the combined input-crosspoint buffered switch with round-robin arbitration.	IEEE Trans. Commun.	2005	DBLP DOI BibTeX RDF
19	Ximing Hu, Xingming Zhang 0002, Binqiang Wang, Zhengrong Zhao	Scheduling Multicast Traffic in a Combined Input Separate Output Queued Switch.	NPC	2005	DBLP DOI BibTeX RDF
19	Yue (Edward) Yao	Scalability of a Class of Switch Networks.	CNSR	2005	DBLP DOI BibTeX RDF
19	Dehui Zhang, Quan Liang Zhao, Jun Gang Han	Design and implementation of an SDH high-speed switch.	ASP-DAC	2005	DBLP DOI BibTeX RDF
19	Constantine Katsinis	Performance of Fault-Tolerant Distributed Shared Memory on Broadcast- and Switch-Based Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
19	Sofia A. Paredes, Trevor J. Hall	Flexible Bandwidth Provision in a Sectored Packet Switch with an Optical Core.	ISCC	2005	DBLP DOI BibTeX RDF
19	Joel J. P. C. Rodrigues, Mário M. Freire, Pascal Lorenz	Impact of Setup Message Processing and Optical Switch Configuration Times on the Performance of IP over Optical Burst Switching Networks.	ISCIS	2005	DBLP DOI BibTeX RDF
19	Igor Radusinovic, Zoran Veljovic	New Round-Robin Scheduling Algorithm for Combined Input-Crosspoint Buffered Switch.	ICN (1)	2005	DBLP DOI BibTeX RDF
19	Xiaohui Zeng, Shengyun Yang, Yanjing Lei, Lihua Han, Yi Lin, Jichang Kang	MPICH for FC-based Token-Routing Switch-Network.	SKG	2005	DBLP DOI BibTeX RDF
19	Peng Zhao, José Nelson Amaral	Feedback-Directed Switch-Case Statement Optimization.	ICPP Workshops	2005	DBLP DOI BibTeX RDF
19	Paul C. F. Tong, Ping-Ping Xu, Wensong Chen, John Hui, Patty Z. Q. Liu	A novel substrate-triggered ESD protection structure for a bus switch IC with on-chip substrate-pump.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
19	Somnath Sengupta	Analytical expression of HD3 due to non-linear MOS switch in MOSFET-C sample and hold circuits.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
19	Ding-Jyh Tsaur, Xian-Yang Lu, Chin-Chi Wu, Woei Lin	3D-VOQ Switch Design and Evaluation.	AINA	2005	DBLP DOI BibTeX RDF
19	Min-Chang Kang, Eun-Gu Jung, Dong-Soo Har	Design of an Asynchronous Switch Based on Butterfly Fat-Tree for Network-on-Chip Applications.	PCM (2)	2005	DBLP DOI BibTeX RDF
19	Ziqian Dong, Roberto Rojas-Cessa	Long Round-Trip Time Support with Shared-Memory Crosspoint Buffered Packet Switch.	Hot Interconnects	2005	DBLP DOI BibTeX RDF
19	Ximing Hu, Jing Qu, Binqiang Wang, Xiaobei Li	CISOQ: A Practical High-Performance Packet Switch Architecture for the Support of Multicast Traffic.	PDCAT	2005	DBLP DOI BibTeX RDF
19	Anand Sangtani, Ravinder Pal, Jia Zhang 0001	Short Circuit Switch An Intelligent Web Services Discovery and Invocation Engine.	IEEE SCC	2005	DBLP DOI BibTeX RDF
19	José Duato, José Flich, Teresa Nachiondo Frinós	A Cost-Effective Technique to Reduce HOL Blocking in Single-Stage and Multistage Switch Fabrics.	PDP	2004	DBLP DOI BibTeX RDF
19	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Fault Tolerance of Programmable Switch Blocks.	DATE	2004	DBLP DOI BibTeX RDF
19	Takeki Yazaki, T. Kanetake, S. Akahane, Yoshihiko Sakata, Kazuo Sugai, Hiroki Yano	High-Speed IPv6 Router/Switch Architecture.	SAINT Workshops	2004	DBLP DOI BibTeX RDF
19	Tae-Won Lee, Young-Chul Kim 0001, Mike Myung-Ok Lee	New MPLS Switch Architecture Supporting Diffserv for High_Speed Switching and QoS.	HSNMC	2004	DBLP DOI BibTeX RDF
19	Nitin Bansal, Amit Katyal	A Switch-Cap Regulator for SoC Applications.	VLSI Design	2004	DBLP DOI BibTeX RDF
19	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham	Towards The Complete Elimination of Gate/Switch Level Simulations.	VLSI Design	2004	DBLP DOI BibTeX RDF
19	Rohini Krishnan, José Pineda de Gyvez	Low Energy Switch Block For FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
19	Yuan Lu, Mike Jorda	Verifying a gigabit ethernet switch using SMV.	DAC	2004	DBLP DOI BibTeX RDF	Verification
19	Rahul Kundu, R. D. (Shawn) Blanton	ATPG for Noise-Induced Switch Failures in Domino Logic.	ICCAD	2003	DBLP DOI BibTeX RDF
19	Kee-Keun Lee, Bruce C. Kim	RF MEMS Switch for Wireless LAN Applications.	ICMENS	2003	DBLP DOI BibTeX RDF
19	Wenjie Li, Yiping Gong, Bin Liu 0001	Performance Evaluation of Crossbar Switch Fabrics in Core Routers.	AINA	2003	DBLP DOI BibTeX RDF	CIOQ, OPRR, VOQ, Single Queue, Speedup
19	Ayman G. Fayoumi, Anura P. Jayasumana	Performance Model of an Optical Switch using Fiber Delay Lines for Resolving Contentions.	LCN	2003	DBLP DOI BibTeX RDF
19	Sangwook Kim, E. Greeneich	Body effect compensated switch for low voltage switched-capacitor circuits.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
19	Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang	A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
19	Valeria Cardellini, Emiliano Casalicchio, Michele Colajanni, Marco Mambelli	Web switch support for differentiated services.	SIGMETRICS Perform. Evaluation Rev.	2001	DBLP DOI BibTeX RDF	quality of service, performance evaluation, distributed systems, load sharing
19	Kamon Jirasereeamornkul, Y. Roungraungpalangkul, Kosin Chamnongthai	A single stage single switch power factor correction converter.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
19	L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia	A Scheduler ASIC for a Programmable Packet Switch.	IEEE Micro	2000	DBLP DOI BibTeX RDF
19	Karsten Weihe	Edge-Disjoint Routing in Plane Switch Graphs in Linear Time.	FOCS	1999	DBLP DOI BibTeX RDF	Graph algorithms, planar graphs, disjoint paths
19	Mayez A. Al-Mouhamed, Mohammad Kaleemuddin	Evaluation of Pipelined Banyan Switch Architectures for ATM Networks.	ISCC	1999	DBLP DOI BibTeX RDF
19	J. W. Cohen	On the asymmetric clocked buffered switch.	Queueing Syst. Theory Appl.	1998	DBLP DOI BibTeX RDF	nearest-neighbour random walk, two-dimensional meromorphic functions, analytic continuation, two-server queueing model
19	Wenjian Qiao, Lionel M. Ni	Network Planning and Tuning in Switch-Based LANs.	ICPP	1998	DBLP DOI BibTeX RDF
19	Frank K. Hwang, Wen-Dar Lin	The Number of Rearrangements in a 3-stage Clos Network Using an Auxiliary Switch.	COCOON	1998	DBLP DOI BibTeX RDF
19	Tzi-cker Chiueh, Srinidhi Varadarajan	Design and Evaluation of a DRAM-based Shared Memory ATM Switch.	SIGMETRICS	1997	DBLP DOI BibTeX RDF
19	Yuan Chen, Vikas Jha, Rajive L. Bagrodia	A Multidimensional Study on the Feasibility of Parallel Switch-Level Circuit Simulation.	Workshop on Parallel and Distributed Simulation	1997	DBLP DOI BibTeX RDF
19	Wu-Yuin Hwang, Wen-Tsuen Chen, Yao-Wen Deng	A High-Performance ATM Switch with Completely and Fairly Shared Buffers.	ICPADS	1997	DBLP DOI BibTeX RDF
19	Yoon-Hwa Choi, Pong-Gyou Lee	Concurrent Error Detection and Fault Location in a Fast ATM Switch.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
19	Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer	SWiTEST: a switch level test generation system for CMOS combinational circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
19	Larry G. Jones, David T. Blaauw	A cache-based method for accelerating switch-level simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
19	Scott Shenker	Making Greed Work in Networks: A Game-Theoretic Analysis of Switch Service Disciplines.	SIGCOMM	1994	DBLP DOI BibTeX RDF
19	Larry G. Jones	An incremental zero/integer delay switch-level simulation environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
19	Jean-Luc Levaire	Semantics and Compilation of the Data-Parallel Switch Statement.	CONPAR	1992	DBLP DOI BibTeX RDF
19	Jer-Min Jou, Jau-Yien Lee, Yachyang Sun, Jhing-Fa Wang	An Efficient VLSI Switch-Box Router.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
19	H. Warmers, D. Sass, Ernst-Helmut Horneber	Switch-level timing models in the MOS simulator BRASIL.	EURO-DAC	1990	DBLP DOI BibTeX RDF
19	David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham	Derivation of signal flow for switch-level simulation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
19	Carles Ferrer 0001, Joan Oliver, Elena Valderrama	A new switch-level test pattern generation algorithm based on single path over a graph representation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
19	Jyh-Herng Chow, Williams Ludwell Harrison III	Switch-stacks: a scheme for microtasking nested parallel loops.	SC	1990	DBLP DOI BibTeX RDF
19	Edward H. Frank	Exploiting parallelism in a switch-level simulation machine.	DAC	1986	DBLP DOI BibTeX RDF
19	Seung Ho Hwang, Young Hwan Kim, A. Richard Newton	An accuration delay modeling technique for switch-level timing verification.	DAC	1986	DBLP DOI BibTeX RDF
19	Trevor N. Mudge, B. A. Makrucki	Probabilistic analysis of a crossbar switch.	ISCA	1982	DBLP BibTeX RDF
19	Gottfried W. R. Luderer, H. Che, J. P. Haggerty, Peter A. Kirslis, W. T. Marshall	A Distributed UNIX System Based on a Virtual Circuit Switch.	SOSP	1981	DBLP DOI BibTeX RDF	UNIX
19	Bernhard Quatember	Modular crossbar switch for large-scale multiprocessor systems: structure and implementation.	AFIPS National Computer Conference	1981	DBLP DOI BibTeX RDF
18	Jengchung Victor Chen, Quang-An Ha, Andree E. Widjaja, Nguyen Thi Lien	To switch or not to switch? Investigating users' switching behaviours of fitness wearable devices.	Int. J. Mob. Commun.	2023	DBLP DOI BibTeX RDF
18	Mohammad Jooshaki, Sahand Karimi-Arpanahi, R. John Millar, Matti Lehtonen, Mahmud Fotuhi-Firuzabad	On the MILP Modeling of Remote-Controlled Switch and Field Circuit Breaker Malfunctions in Distribution System Switch Placement.	IEEE Access	2023	DBLP DOI BibTeX RDF
18	Diederick Vermetten, Hao Wang 0025, Kevin Sim, Emma Hart	To Switch or not to Switch: Predicting the Benefit of Switching between Algorithms based on Trajectory Features.	CoRR	2023	DBLP DOI BibTeX RDF
18	Jaume Comellas, Gabriel Junyent	Optical Interconnection for Datacenters: To Switch or Not to Switch.	ICTON	2023	DBLP DOI BibTeX RDF
18	Diederick Vermetten, Hao Wang 0025, Kevin Sim, Emma Hart	To Switch or Not to Switch: Predicting the Benefit of Switching Between Algorithms Based on Trajectory Features.	EvoApplications@EvoStar	2023	DBLP DOI BibTeX RDF