Search results for "CORDIC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Hau T. Ngo, Vijayan K. Asari	A pipelined architecture for real-time correction of barrel distortion in wide-angle camera images.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
12	Jeongseon Euh, Jeevan Chittamuru, Wayne P. Burleson	Power-Aware 3D Computer Graphics Rendering.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	low-power, reconfigurable, texture mapping, 3D Graphics, shading
12	Christophe Wolinski, Krzysztof Kuchcinski	A Constraints Programming Approach for Fabric Cell Synthesis.	DSD	2005	DBLP DOI BibTeX RDF
12	Arjun K. Pai, Khaled Benkrid, Danny Crookes	Embedded Reconfigurable DCT Architectures Using Adder-Based Distributed Arithmetic.	CAMP	2005	DBLP DOI BibTeX RDF
12	Jingzhao Ou, Viktor K. Prasanna	MATLAB/Simulink Based Hardware/Software Co-Simulation for Designing Using FPGA Configured Soft Processors.	IPDPS	2005	DBLP DOI BibTeX RDF
12	Hung Yang Ko, Yi-Chiuan Wang, An-Yeu Wu	Digital signal processing engine design for polar transmitter in wireless communication systems.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
12	Jong-wan Seo, Myong-Chul Shin	A study on an ASIC design technique for digital protective relays.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
12	Jarmo Takala, Konsta Punkka	Scalable FFT Processors and Pipelined Butterfly Units.	SAMOS	2004	DBLP DOI BibTeX RDF
12	Shu-Shin Chin, Sangjin Hong, Suhwan Kim	Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units.	ISVLSI	2004	DBLP DOI BibTeX RDF
12	Deepak Boppana, Kully Dhanoa, Jesse Kempa	FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm.	FCCM	2004	DBLP DOI BibTeX RDF
12	K. Wang, Jugdutt Singh, Mike Faulkner	FPGA Implementation of an OFDM-WLAN Synchronizer.	DELTA	2004	DBLP DOI BibTeX RDF
12	Thomas Sailer, Gerhard Tröster	An Efficient VLSI Architecture for Computing Decision Feedback Equalizer Coefficients from the Channel State Information.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	minimum mean square error (MMSE), decision feedback equalizer (DFE), displacement structure theory, channel state information (CSI)
12	Fernando E. Ortiz, John R. Humphrey, James P. Durbano, Dennis W. Prather	A Study on the Design of Floating-Point Functions in FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
12	José Marín-Roig, Vicente Torres-Carot, Ma José Canet, Asuncion Perez-Pascual, Trinidad Sansaloni, Francisco Cardells-Tormo, Fabian Angarita, Felip Vicedo, Vicenc Almenar-Terre, Javier Valls-Coquillat	DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems.	FPL	2003	DBLP DOI BibTeX RDF
12	José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera	High-Radix Iterative Algorithm for Powering Computation.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
12	Tan Yiyu, Zhang Ning	An Image Processing System Scheme in B Mode Ultrasonic Ophthalmological Scanner.	CBMS	2003	DBLP DOI BibTeX RDF
12	Francisco Cardells-Tormo, Javier Valls-Coquillat	Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
12	A. S. Madhukumar, Z. Guo Ping, T. Kian Seng, Y. Kuck Jong, Tim Mingqian Zhong, T. Y. Hong, Francois P. S. Chin	Space-time equalizer for advanced 3GPP WCDMA mobile terminal: experimental results.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
12	Vijay P. Shah, Anthony Skjellum, Nicolas H. Younan, Torey Alford, D. Whitcomb, A. Watkins	inAspect™: interfacing Java and VSIPL.	Java Grande	2002	DBLP DOI BibTeX RDF	VSIPL, embedded Java, image processing, signal processing, high-performance, linear algebra, fixed-point arithmetic, multi-platform, JNI
12	Francisco Cardells-Tormo, Javier Valls-Coquillat	High Performance Quadrature Digital Mixers for FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
12	Francisco Cardells-Tormo, Javier Valls-Coquillat, Vicenc Almenar-Terre, Vicente Torres-Carot	Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard.	FPL	2002	DBLP DOI BibTeX RDF
12	Francisco Cardells-Tormo, A. Valls-Coquillat	Optimized FPGA-implementation of quadrature DDS.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
12	Laurent Imbert, Jean-Michel Muller, F. Rico	A Radix-10 BKM Algorithm for Computing Transcendentals on Pocket Computers.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
12	Lijun Gao, Keshab K. Parhi	Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption.	ASAP	2000	DBLP DOI BibTeX RDF	QRD-RLS filter, block-weight-update, single-state-update parallel processing, low power, ASIC design
12	Peter Rieder, Sven Simon 0001, Christian V. Schimpfle	Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
12	Kees-Jan van der Kolk, Ed F. Deprettere, Jeong-A Lee	A Floating Point Vectoring Algorithm Based on Fast Rotations.	EUROMICRO	1999	DBLP DOI BibTeX RDF
12	Javier Hormigo, Julio Villalba, Emilio L. Zapata	Arithmetic Unit for the Computation of Interval Elementary Functions.	EUROMICRO	1999	DBLP DOI BibTeX RDF
12	Elisardo Antelo, Montserrat Bóo, Javier D. Bruguera, Emilio L. Zapata	A novel design of a two operand normalization circuit.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
12	C. P. Ravikumar, N. Satya Prasad	Evaluating BIST Architectures for Low Power.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
12	Paul S. Graham, Brent E. Nelson	Frequency-Domain Sonar Processing in FPGAs and DSPs.	FCCM	1998	DBLP DOI BibTeX RDF
12	John R. Sacha, Mary Jane Irwin	The logarithmic number system for strength reduction in adaptive filtering.	ISLPED	1998	DBLP DOI BibTeX RDF
12	David Garrett, Mircea R. Stan	Low power architecture of the soft-output Viterbi algorithm.	ISLPED	1998	DBLP DOI BibTeX RDF	SOVA, VA, low power, turbo codes
12	Peter Rieder, Josef A. Nossek	Implementation of Orthogonal Wavelet Transforms and their Applications.	ASAP	1997	DBLP DOI BibTeX RDF
12	Tobias G. Noll	Carry-save architectures for high-speed digital signal processing.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
12	Paul F. C. Krekel, Ed F. Deprettere	A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix.	J. VLSI Signal Process.	1989	DBLP DOI BibTeX RDF