|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 210 occurrences of 148 keywords
|
|
|
Results
Found 3186 publication records. Showing 3186 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Leandro Andrade Martinez, Eduardo Marques |
A hardware/software codesign framework for vision-based ADAS. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Thomas Townsend, Brent E. Nelson, Michael J. Wirthlin |
An XDL alternative for interfacing RapidSmith and Vivado. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ahmet Caner Yuzuguler, William Andrew Simon, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli |
Single-FPGA 3D ultrasound beamformer. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Charalabos Kritikakis, Grigorios Chrysos 0001, Apostolos Dollas, Dionisios N. Pnevmatikatos |
An FPGA-based high-throughput stream join architecture. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Pierre-Henri Horrein, Benoit Porteboeuf, André Lalevee |
Ouessant: Microcontroller approach for flexible accelerator integration and control in System-on-Chip. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Que Yanghua, Harnhua Ng, Nachiket Kapre |
Boosting convergence of timing closure using feature selection in a Learning-driven approach. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jeffrey Goeders, Steven J. E. Wilton |
Quantifying observability for in-system debug of high-level synthesis circuits. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel |
FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Fenzandez, Carlos González 0002, Daniel Mozos |
Dimensionality reduction of hyperspectral images using reconfigurable hardware. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Shrikant Vyas, Naveen Kumar Dumpala, Russell Tessier, Daniel E. Holcomb |
Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Hugo Fernandes, M. Awais Aslam, Jorge Lobo 0002, João Filipe Ferreira, Jorge Dias 0001 |
Bayesian inference implemented on FPGA with stochastic bitstreams for an autonomous robot. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ibrahim Ahmed 0001, Shuze Zhao, Olivier Trescases, Vaughn Betz |
Measure twice and cut once: Robust dynamic voltage scaling for FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ioannis Parnassos, Panagiotis Skrimponis, Georgios Zindros, Nikolaos Bellas |
SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems On Chip. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Paul Grigoras, Pavel Burovskiy, Wayne Luk, Spencer J. Sherwin |
Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Wei Liang, Wenbo Yin, Ping Kang, Lingli Wang |
Memory efficient and high performance key-value store on FPGA using Cuckoo hashing. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Farheen Fatima Khan, Andy Gean Ye |
An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Nachiket Kapre, Samuel Bayliss |
Survey of domain-specific languages for FPGA computing. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jan Viktorin, Jan Korenek |
Packet processing on FPGA SoC with DPDK. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat |
Towards a hardware-assisted information flow tracking ecosystem for ARM processors. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das |
Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Konstantinos Boikos, Christos-Savvas Bouganis |
Semi-dense SLAM on an FPGA SoC. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | William Andrew Simon, Ahmet Caner Yuzuguler, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli |
Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Srikanth Sridharan, Paolo Durante, Christian Faerber, Niko Neufeld |
Accelerating particle identification for high-speed data-filtering using OpenCL on FPGAs and other architectures. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Dong Liu, Benjamin Carrión Schäfer |
Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ren Chen, Viktor K. Prasanna |
Optimizing interconnection complexity for realizing fixed permutation in data and signal processing algorithms. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ilya Ganusov, Benjamin Devlin |
Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yubin Li, Yuliang Sun, Guohao Dai, Qiang Xu 0001, Yu Wang 0002, Huazhong Yang |
Approximate Frequent Itemset Mining for streaming data on FPGA. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ze-ke Wang, Johns Paul, Hui Yan Cheah, Bingsheng He, Wei Zhang 0012 |
Relational query processing on OpenCL-based FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Liang Feng 0001, Hao Liang 0003, Sharad Sinha, Wei Zhang 0012 |
HeteroSim: A heterogeneous CPU-FPGA simulator. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau 0001 |
Demonstration of a context-switch method for heterogeneous reconfigurable systems. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich |
FPGA-based accelerator design from a domain-specific language. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik R. Chowdhury, Miriam Leeser |
Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yusuke Matsushita 0001, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano |
Body bias grain size exploration for a coarse grained reconfigurable accelerator. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Pietro Fezzardi, Fabrizio Ferrandi |
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Burak Unal, Ali Akoglu |
Resource efficient real-time processing of Contrast Limited Adaptive Histogram Equalization. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Martin Kumm, Marco Kleinlein, Peter Zipf |
Efficient sum of absolute difference computation on FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mohamed S. Abdelfattah, Vaughn Betz |
LYNX: CAD for FPGA-based networks-on-chip. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Kaan Kara, Gustavo Alonso |
Fast and robust hashing for database operators. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr |
Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jotham Vaddaboina Manoranjan, Kenneth S. Stevens |
Reconfigurable circuit for implementation of family of 4-phase latch protocols. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Yanzhe Li, Kai Huang 0002, Luc Claesen |
SoC and FPGA oriented high-quality stereo vision system. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Esam El-Araby, Nader M. Namazi |
Chaotic architectures for secure free-space optical communication. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Antonios Prodromakis, Nikolaos Papandreou, Eleni Bougioukou, Urs Egger, Nikos Toulgaridis, Theodore Antonakopoulos 0001, Haralampos Pozidis, Evangelos Eleftheriou |
Controller architecture for low-latency access to phase-change memory in OpenPOWER systems. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Size Xiao, Adam Postula, Neil W. Bergmann |
Optimal random sampling based path planning on FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Baptiste Delporte, Anthony Convers, Roberto Rigamonti, Alberto Dassatti |
Transparent FPGA flow. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Fellipe Montero, Guy Bois, Eric Jenn, Kevin Duplantier |
Architectural exploration and implementation of an image processing chain with SpaceStudio™. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Hao Zhou, Xinyu Niu, Junqi Yuan, Lingli Wang, Wayne Luk |
Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Furkan Turan, Ruan de Clercq, Pieter Maene, Oscar Reparaz, Ingrid Verbauwhede |
Hardware acceleration of a software-based VPN. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto |
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Malte Vesper, Dirk Koch, Kizheppatt Vipin, Suhaib A. Fahmy |
JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Jori Winderickx, Joan Daemen, Nele Mentens |
Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Kumar H. B. Chethan, Nachiket Kapre |
Hoplite-DSP: Harnessing the Xilinx DSP48 multiplexers to efficiently support NoCs on FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sidharth Maheshwari, Gourav Modi, Siddhartha 0001, Nachiket Kapre |
Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Ismail San, Nicole Fern, Çetin Kaya Koç, Kwang-Ting Cheng |
Trojans modifying soft-processor instruction sequences embedded in FPGA bitstreams. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Mario Ruiz, Javier Ramos 0002, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, C. Sisterna |
Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Sichao Wang, Tsutomu Maruyama |
An implementation method of the box filter on FPGA. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Zhenzhong Xiao, Dirk Koch, Mikel Luján |
A partial reconfiguration controller for Altera Stratix V FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Petter Kallstrom, Oscar Gustafsson |
Fast and area efficient adder for wide data in recent Xilinx FPGAs. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele (eds.) |
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016 |
FPL |
2016 |
DBLP BibTeX RDF |
|
1 | Tuan D. A. Nguyen, Akash Kumar 0001 |
XNoC: A non-intrusive TDM circuit-switched Network-on-Chip. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | David Sidler, Zsolt István, Gustavo Alonso |
Low-latency TCP/IP stack for data center applications. |
FPL |
2016 |
DBLP DOI BibTeX RDF |
|
1 | Julian Oppermann, Andreas Koch 0001, Ting Yu 0012, Oliver Sinnen |
Domain-specific optimisation for the high-level synthesis of CellML-based simulation accelerators. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jian Yan 0002, Jifang Jin, Ying Wang 0032, Xuegong Zhou, Philip H. W. Leong, Lingli Wang |
UniStream: A unified stream architecture combining configuration and data processing. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Daniel Llamocca, Brian K. Dean |
A scalable pipelined architecture for biomimetic vision sensors. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Qi Chen, Qiang Liu 0011 |
Pipelined NoC router architecture design with buffer configuration exploration on FPGA. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Tahsin Turker Mutlugun, Sheng-De Wang |
OpenCL computing on FPGA using multiported shared memory. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Xiaobin Liu, Tedy Thomas, Alan Boguslawski, Russell Tessier |
Adaptive MRAM-based CGRAs. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nikolaos Alachiotis 0001 |
Generating FPGA accelerators for chemical similarity assessment. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Andre Prata, Arnaldo S. R. Oliveira, Nuno Borges Carvalho |
FPGA-based all-digital Software Defined Radio receiver. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Chin Hau Hoo, Akash Kumar 0001, Yajun Ha |
ParaLaR: A parallel FPGA router based on Lagrangian relaxation. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nicholas J. Fraser, Duncan J. M. Moss, JunKyu Lee, Stephen Tridgell, Craig T. Jin, Philip Heng Wai Leong |
A fully pipelined kernel normalised least mean squares processor for accelerated parameter optimisation. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Hiroki Nakahara, Tsutomu Sasao |
A deep convolutional neural network based on nested residue number system. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Efstathios Sotiriou-Xanthopoulos, Sotirios Xydis, Kostas Siozios, George Economakos, Dimitrios Soudris |
Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yun Rock Qu, Viktor K. Prasanna |
Power-efficient range-match-based packet classification on FPGA. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Carlos González 0002, Daniel Mozos, Sebastián López, Roberto Sarmiento |
FPGA implementation to estimate the number of endmembers in hyperspectral images. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Edoardo Fusella, Alessandro Cilardo, Antonino Mazzeo |
Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Noa Zilberman, Yury Audzevich, Georgina Kalogeridou, Neelakandan Manihatty Bojan, Jingyun Zhang, Andrew W. Moore 0002 |
NetFPGA - rapid prototyping of high bandwidth devices in open source. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Ren Chen, Viktor K. Prasanna |
Automatic generation of high throughput energy efficient streaming architectures for arbitrary fixed permutations. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Shengjia Shao, Liucheng Guo, Ce Guo, Thomas C. P. Chau, David B. Thomas, Wayne Luk, Stephen Weston |
Recursive pipelined genetic propagation for bilevel optimisation. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mohammad Hosseinabady, José Luis Núñez-Yáñez |
Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Mark Wijtvliet, Shakith Fernando, Henk Corporaal |
SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sen Ma, Zeyad Aklah, David Andrews 0001 |
A run time interpretation approach for creating custom accelerators. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | João Carlos Resende, Ricardo Chaves |
Compact dual block AES core on FPGA for CCM Protocol. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews 0001, Kunle Olukotun, Paolo Ienne |
Automatic support for multi-module parallelism from computational patterns. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Teng Xu 0001, Hongxiang Gu, Miodrag Potkonjak |
Data protection using recursive inverse function. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Sang Woo Jun, Ming Liu, Shuotao Xu, Arvind |
A transport-layer network for distributed FPGA platforms. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Libo Huang, Yongwen Wang, Qiang Dou, Chengyi Zhang, Caixia Sun, Chao Xu |
Fast FPGA system for microarchitecture optimization on synthesizable modern processor design. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Berg Severens, Elias Vansteenkiste, Karel Heyse, Dirk Stroobandt |
Estimating circuit delays in FPGAs after technology mapping. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | He Qi, Oluseyi A. Ayorinde, Yu Huang 0015, Benton H. Calhoun |
Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Aaron Mills, Pei Zhang 0009, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones |
A software configurable coprocessor-based state-space controller. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Oluseyi A. Ayorinde, He Qi, Yu Huang 0015, Benton H. Calhoun |
Using island-style bi-directional intra-CLB routing in low-power FPGAs. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes |
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Henry Block, Tsutomu Maruyama |
An FPGA implementation of a phylogenetic tree reconstruction algorithm using an alternative second-pass optimization. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi |
Inter-procedural resource sharing in High Level Synthesis through function proxies. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Jiasen Huang, Weina Lu, Junyan Ren |
Greedy approach based heuristics for partitioning SpMxV on FPGAs. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Rui Fiel Cordeiro, Arnaldo S. R. Oliveira, José M. N. Vieira |
FPGA-based all-digital transmitters. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Yuan Xue, Patrick Cronin, Chengmo Yang, Jingtong Hu |
Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Zeping Xue, David B. Thomas |
SysAlloc: A hardware manager for dynamic memory allocation in heterogeneous systems. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Rui Fiel Cordeiro, Andre Prata, Arnaldo S. R. Oliveira, Nuno Borges Carvalho, José M. N. Vieira |
FPGA-based all-digital software defined radio system demonstration. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
1 | Andrei-Dumitru Oancea, Christian Stüllein, Jano Gebelein, Udo Kebschull |
A resilient, flash-free soft error mitigation concept for the CBM-ToF read-out chain via GBT-SCA. |
FPL |
2015 |
DBLP DOI BibTeX RDF |
|
Displaying result #601 - #700 of 3186 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ 12][ 13][ 14][ 15][ 16][ >>] |
|