Search results for "RTL"

Hits ?▲	Authors	Title	Venue	Year	Link
15	Sheikh Ariful Islam, Srinivas Katkoori	SafeController: Efficient and Transparent Control-Flow Integrity for RTL Design.	ISVLSI	2020	DBLP DOI BibTeX RDF
15	Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul	Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices.	VLSI-SOC	2020	DBLP DOI BibTeX RDF
15	Blaise Tine, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim	Productive Hardware Designs using Hybrid HLS-RTL Development.	FPGA	2020	DBLP DOI BibTeX RDF
15	Ahmad El-Shiekh, Ahmad El-Alfy, Ahmad Ammar, Mohamed Gamal, Mohamed Dessouky, Khaled Salah 0001, Hassan Mostafa	IPXACT-Based RTL Generation Tool.	NILES	2020	DBLP DOI BibTeX RDF
15	Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim	Tango: An Optimizing Compiler for Just-In-Time RTL Simulation.	DATE	2020	DBLP DOI BibTeX RDF
15	Jie Xiao 0003, Qiou Ji, Jungang Lou, Ziwen Sun, Yujiao Huang	A Stochastic-Based Reliability Calculation Method for RTL Circuits.	iThings/GreenCom/CPSCom/SmartData/Cybermatics	2020	DBLP DOI BibTeX RDF
15	Yangdi Lyu, Prabhat Mishra 0001	Automated Test Generation for Activation of Assertions in RTL Models.	ASP-DAC	2020	DBLP DOI BibTeX RDF
15	Jiaji He, Haocheng Ma, Xiaolong Guo, Yiqiang Zhao, Yier Jin	Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations.	ASP-DAC	2020	DBLP DOI BibTeX RDF
15	Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim	Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs.	ISPD	2020	DBLP DOI BibTeX RDF
15	Mehdi Moghaddamfar, Christian Färber, Wolfgang Lehner, Norman May	Comparative analysis of OpenCL and RTL for sort-merge primitives on FPGA.	DaMoN	2020	DBLP DOI BibTeX RDF
15	Jinwoo Kim, Gauthaman Murali, Pruek Vanna-Iampikul, Edward Lee, Daehyun Kim 0004, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Saibal Mukhopadhyay, Sung Kyu Lim	RTL-to-GDS Design Tools for Monolithic 3D ICs.	ICCAD	2020	DBLP DOI BibTeX RDF
15	Yanqing Zhang 0002, Haoxing Ren, Brucek Khailany	Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk).	ICCAD	2020	DBLP DOI BibTeX RDF
15	Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer 0001	Representing Gate-Level SET Faults by Multiple SEU Faults at RTL.	IOLTS	2020	DBLP DOI BibTeX RDF
15	Rongliang Fu, Zhimin Zhang 0004, Guang-Ming Tang, Junying Huang, Xiaochun Ye, Dongrui Fan, Ninghui Sun	Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits.	ACM Great Lakes Symposium on VLSI	2020	DBLP DOI BibTeX RDF
15	Jaganath Prasad Mohanty, Kamalakanta Mahapatra	Authenticating resilience of RTL codes against Power Side Channel leakages.	iSES	2020	DBLP DOI BibTeX RDF
15	Sheikh Ariful Islam, Love Kumar Sah, Srinivas Katkoori	Analytical Estimation and Localization of Hardware Trojan Vulnerability in RTL Designs.	ISQED	2020	DBLP DOI BibTeX RDF
15	Sherief Reda	Overview of the OpenROAD Digital Design Flow from RTL to GDS.	VLSI-DAT	2020	DBLP DOI BibTeX RDF
15	Yier Jin	CAD for Security: A Full Reverse Engineering Toolchain from Layout to RTL.	VLSI-DAT	2020	DBLP DOI BibTeX RDF
15	Jakub Kaderka, Tomás Urbanec 0001	Time and sample rate synchronization of RTL-SDR using a GPS receiver.	RADIOELEKTRONIKA	2020	DBLP DOI BibTeX RDF
15	Keisuke Takano, Tetsuya Oda, Masaki Kohata	Design of a DSL for Converting Rust Programming Language into RTL.	EIDWT	2020	DBLP DOI BibTeX RDF
15	Rafael Aguilar-Gonzalez, Alfonso Prieto-Guerrero, Victor Ramos, Efrain Santos-Luna, Miguel López-Benítez	A Comparative Study of RTL-SDR Dongles from the Perspective of the Final Consumer.	ICCE	2020	DBLP DOI BibTeX RDF
15	Nourhan Muhammed, Nour Hussein, Khaled Salah 0002, Ayub Khan	Assertion and Coverage Driven Test Generation Tool for RTL Designs.	UEMCON	2020	DBLP DOI BibTeX RDF
15	Scott Beamer, David Donofrio	Efficiently Exploiting Low Activity Factors to Accelerate RTL Simulation.	DAC	2020	DBLP DOI BibTeX RDF
15	Keisuke Takano, Tetsuya Oda, Masaki Kohata	Approach of a Coding Conventions for Warning and Suggestion in Transpiler for Rust Convert to RTL.	GCCE	2020	DBLP DOI BibTeX RDF
15	Anushree Mahapatra, Benjamin Carrión Schäfer	VeriIntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration.	Integr.	2019	DBLP DOI BibTeX RDF
15	Tao Zhang, Jian Wang 0024, Shize Guo, Zhe Chen	A Comprehensive FPGA Reverse Engineering Tool-Chain: From Bitstream to RTL Code.	IEEE Access	2019	DBLP DOI BibTeX RDF
15	Zeynab Mohseni, Pedro Reviriego	Reliability characterization and activity analysis of lowRISC internal modules against single event upsets using fault injection and RTL simulation.	Microprocess. Microsystems	2019	DBLP DOI BibTeX RDF
15	Jian Hu, Tun Li, Sikun Li	Formal Equivalence Checking Between System-Level and RTL Descriptions without Pre-Given Mapping Information.	J. Circuits Syst. Comput.	2019	DBLP DOI BibTeX RDF
15	Maya H. Safieddine, Fadi A. Zaraket, Rouwaida Kanj, Ali S. Elzein, Wolfgang Roesner	Verification at RTL Using Separation of Design Concerns.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2019	DBLP DOI BibTeX RDF
15	Reda Yagoub, Mohamed Benaissa, Belkacem Benadda	Nearby Carrier Detection Based on Low Cost RTL-SDR Front End.	Wirel. Pers. Commun.	2019	DBLP DOI BibTeX RDF
15	Sheikh Ariful Islam, Farha Islam Mime, S. M. Asaduzzaman, Farzana Islam	Socio-network Analysis of RTL Designs for Hardware Trojan Localization.	CoRR	2019	DBLP BibTeX RDF
15	Polina Proskura, Alexey Zaytsev 0002, I. Braslavsky, Evgenii Egorov, Evgeny Burnaev	Usage of multiple RTL features for Earthquake prediction.	CoRR	2019	DBLP BibTeX RDF
15	Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev 0001, Yier Jin, Mark M. Tehranipoor	RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.	CoRR	2019	DBLP BibTeX RDF
15	Jinyan Zhu, Ruguang Zhou	A vector CTL-RTL hierarchy with bi-Hamiltonian structure.	Appl. Math. Lett.	2019	DBLP DOI BibTeX RDF
15	Blaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim, Jeffrey S. Vetter	POSTER: Tango: An Optimizing Compiler for Just-In-Time RTL Simulation.	PACT	2019	DBLP DOI BibTeX RDF
15	Vighnesh Iyer, Donggyu Kim, Borivoje Nikolic, Sanjit A. Seshia	RTL bug localization through LTL specification mining (WIP).	MEMOCODE	2019	DBLP DOI BibTeX RDF
15	Prokash Ghosh, Rohit Srivastava	Case Study: SoC Performance Verification and Static Verification of RTL Parameters.	MTV	2019	DBLP DOI BibTeX RDF
15	Alex Vidal-Obiols, Jordi Cortadella, Jordi Petit, Marc Galceran Oms, Ferran Martorell	RTL-Aware Dataflow-Driven Macro Placement.	DATE	2019	DBLP DOI BibTeX RDF
15	Yangdi Lyu, Alif Ahmed, Prabhat Mishra 0001	Automated Activation of Multiple Targets in RTL Models using Concolic Testing.	DATE	2019	DBLP DOI BibTeX RDF
15	Aman Goel, Karem A. Sakallah	Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL Designs.	DATE	2019	DBLP DOI BibTeX RDF
15	Tobias Strauch	An RTL ATPG Flow Using the Gate Inherent Fault (GIF) Model Applied on Non-, Standard- and Random-Access-Scan (RAS).	DSD	2019	DBLP DOI BibTeX RDF
15	Donggyu Kim, Jerry Zhao, Jonathan Bachrach, Krste Asanovic	Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection.	MICRO	2019	DBLP DOI BibTeX RDF
15	Moon Gi Seok, Hessam S. Sarjoughian, Daejin Park	A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs.	ASP-DAC	2019	DBLP DOI BibTeX RDF
15	Neil Veira, Zissis Poulos, Andreas G. Veneris	Suspect2vec: a suspect prediction model for directed RTL debugging.	ASP-DAC	2019	DBLP DOI BibTeX RDF
15	Grégory Calegari Marchesan, Everton Alceu Carara, Crístian Müller, Leonardo Londero de Oliveira	GCoL - A General Co-simulator Applied to Wireless Sensor Networks and RTL Design.	NEWCAS	2019	DBLP DOI BibTeX RDF
15	Zongze Li, Song Fu	Accelerating RNN on FPGA with Efficient Conversion of High-Level Designs to RTL.	IEEE BigData	2019	DBLP DOI BibTeX RDF
15	Anushree Mahapatra, Benjamin Carrión Schäfer	Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration.	ISCAS	2019	DBLP DOI BibTeX RDF
15	Shogo Semba, Hiroshi Saito	Comparison of RTL Conversion and GL Conversion from Synchronous Circuits to Asynchronous Circuits.	ISCAS	2019	DBLP DOI BibTeX RDF
15	Shan Cao, Zhenyi Bao, Chengbo Xue, Wei Deng, Shugong Xu, Shunqing Zhang	A Pre-RTL Simulator for Neural Networks.	ISCAS	2019	DBLP DOI BibTeX RDF
15	Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura	A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths.	IOLTS	2019	DBLP DOI BibTeX RDF
15	Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue	An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis.	ITC-Asia	2019	DBLP DOI BibTeX RDF
15	Rebiha Kemcha, Nadia Nedjah, Amin Riad Maouche, Maamar Bougherara	Evolutionary Design of Approximate Sequential Circuits at RTL Using Particle Swarm Optimization.	ICCSA (2)	2019	DBLP DOI BibTeX RDF
15	Polina Proskura, Alexey Zaytsev 0002, I. Braslavsky, Evgenii Egorov, Evgeny Burnaev	Usage of Multiple RTL Features for Earthquakes Prediction.	ICCSA (1)	2019	DBLP DOI BibTeX RDF
15	Sheikh Ariful Islam, Love Kumar Sah, Srinivas Katkoori	DLockout: A Design Lockout Technique for Key Obfuscated RTL IP Designs.	iSES	2019	DBLP DOI BibTeX RDF
15	Aman Goel, Karem A. Sakallah	Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction.	NFM	2019	DBLP DOI BibTeX RDF
15	Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev 0001, Yier Jin, Mark M. Tehranipoor	RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.	VTS	2019	DBLP DOI BibTeX RDF
15	Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez 0001, Giovanni Squillero, Anton Tsertov	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL.	ITC	2019	DBLP DOI BibTeX RDF
15	Cheng-Hsien Shen, Aaron C.-W. Liang, Charles C.-H. Hsu, Charles H.-P. Wen	FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging.	ITC	2019	DBLP DOI BibTeX RDF
15	Aravind Krishnan Varadarajan, Michael Hsiao	RTL Test Generation on Multi-core and Many-Core Architectures.	VLSID	2019	DBLP DOI BibTeX RDF
15	Anirban Sengupta, Dipanjan Roy, Saraju P. Mohanty	Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design.	ICCE	2019	DBLP DOI BibTeX RDF
15	Heechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim 0002, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty, Sung Kyu Lim	RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs.	DAC	2019	DBLP DOI BibTeX RDF
15	Donggyu Kim	FPGA-Accelerated Evaluation and Verification of RTL Designs.		2019	RDF
15	Yufei Ma 0002, Naveen Suda, Yu Cao 0001, Sarma B. K. Vrudhula, Jae-sun Seo	ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler.	Integr.	2018	DBLP DOI BibTeX RDF
15	Davide Bellizia, Simone Bongiovanni, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Francesco Bruno Trotta	Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
15	Shimpei Sato, Ryohei Kobayashi, Kenji Kise	ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment.	IEICE Trans. Inf. Syst.	2018	DBLP DOI BibTeX RDF
15	Mehdi Roozmeh, Luciano Lavagno	Design space exploration of multi-core RTL via high level synthesis from OpenCL models.	Microprocess. Microsystems	2018	DBLP DOI BibTeX RDF
15	Zissis Poulos, Andreas G. Veneris	Failure Triage in RTL Regression Verification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
15	Behzad Salami 0001, Osman S. Unsal, Adrián Cristal	On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation.	CoRR	2018	DBLP BibTeX RDF
15	Tobias Strauch	Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs.	CoRR	2018	DBLP BibTeX RDF
15	Seyed Ali Asghar AbbasZadeh Arani, Ehsanollah Kabir, Reza Ebrahimpour	Combining RtL and LtR HMMs to recognise handwritten Farsi words of small- and medium-sized vocabularies.	IET Comput. Vis.	2018	DBLP DOI BibTeX RDF
15	Rafael Mello	Implementation of VOR receiver with the RTL-SDR.		2018	DOI RDF
15	Surbhi Chhabra, Kusum Lata	Enhancing Data Security using Obfuscated 128-bit AES Algorithm - An Active Hardware Obfuscation Approach at RTL Level.	ICACCI	2018	DBLP DOI BibTeX RDF
15	Nancy S. Soliman, Khaled Salah 0001, Ahmed H. Madian	Automatic RTL coding correction Linting tool for critical issues.	ICM	2018	DBLP DOI BibTeX RDF
15	Davide Zoni, Luca Cremona, William Fornaciari	PowerProbe: Run-time power modeling through automatic RTL instrumentation.	DATE	2018	DBLP DOI BibTeX RDF
15	Alif Ahmed, Farimah Farahmandi, Prabhat Mishra 0001	Directed test generation using concolic testing on RTL models.	DATE	2018	DBLP DOI BibTeX RDF
15	Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler	Towards fully automated TLM-to-RTL property refinement.	DATE	2018	DBLP DOI BibTeX RDF
15	Neil Veira, Zissis Poulos, Andreas G. Veneris	Suspect set prediction in RTL bug hunting.	DATE	2018	DBLP DOI BibTeX RDF
15	Daniel Mueller-Gritschneder, Martin Dittrich, Josef Weinzierl, Eric Cheng, Subhasish Mitra, Ulf Schlichtmann	ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques.	DATE	2018	DBLP DOI BibTeX RDF
15	Yang Zhang 0014, Huimei Cheng, Dake Chen, Huayu Fu, Shikhanshu Agarwal, Mark Lin, Peter A. Beerel	Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design.	ASYNC	2018	DBLP DOI BibTeX RDF
15	Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler	Towards Automated Refinement of TLM Properties to RTL.	MBMV	2018	DBLP BibTeX RDF
15	Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, Krste Asanovic	DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles.	FPL	2018	DBLP DOI BibTeX RDF
15	Masudul Hassan Quraishi, Hessam S. Sarjoughian, Soroosh Gholami	Co-simulation of Hardware RTL and Software System using FMI.	WSC	2018	DBLP DOI BibTeX RDF
15	Mohammed Saber, Hatim Kharraz Aroussi, Abdessamad El Rharras, Rachid Saadane	Raspberry Pi and RTL-SDR for Spectrum Sensing based on FM Real Signals.	ICMCS	2018	DBLP DOI BibTeX RDF
15	Jan Nevoral, Richard Ruzicka	Efficient Implementation of Bi-Functional RTL Components - Case Study.	NGCAS	2018	DBLP DOI BibTeX RDF
15	Kevin Laeufer, Jack Koenig, Donggyu Kim, Jonathan Bachrach, Koushik Sen	RFUZZ: coverage-directed fuzz testing of RTL on FPGAs.	ICCAD	2018	DBLP DOI BibTeX RDF
15	Farhath Zareen, Robert Karam	Detecting RTL Trojans using Artificial Immune Systems and High Level Behavior Classification.	AsianHOST	2018	DBLP DOI BibTeX RDF
15	Jan Malburg, Heinz Riener, Görschwin Fey	Mining Latency Guarantees for RTL Designs.	ISMVL	2018	DBLP DOI BibTeX RDF
15	Kunal Bansal, Michael S. Hsiao	Optimization of Mutant Space for RTL Test Generation.	ICCD	2018	DBLP DOI BibTeX RDF
15	Alec Roelke, Xinfei Guo, Mircea Stan	OldSpot: A Pre-RTL Model for Fine-Grained Aging and Lifetime Optimization.	ICCD	2018	DBLP DOI BibTeX RDF
15	Tania Khanna, Michael Hsiao	Guiding RTL Test Generation Using Relevant Potential Invariants.	ICCD	2018	DBLP DOI BibTeX RDF
15	Radek Isa, Pavel Benácek, Viktor Pus	Verification of Generated RTL from P4 Source Code.	ICNP	2018	DBLP DOI BibTeX RDF
15	Behzad Salami 0001, Osman S. Unsal, Adrián Cristal Kestelman	On the Resilience of RTL NN Accelerators: Fault Characterization and Mitigation.	SBAC-PAD	2018	DBLP DOI BibTeX RDF
15	Sheikh Ariful Islam, Srinivas Katkoori	High-level synthesis of key based obfuscated RTL datapaths.	ISQED	2018	DBLP DOI BibTeX RDF
15	Sang Un Park, Tae Pyeong Kim, Mee Zee Lee, Yong Beom Cho	Method of RTL Debugging When Using HLS for HW Design : Different Simulation Result of Verilog & VHDL.	ISOCC	2018	DBLP DOI BibTeX RDF
15	Omer Subasi, Chun-Kai Chang, Mattan Erez, Sriram Krishnamoorthy	Characterizing the Impact of Soft Errors Affecting Floating-point ALUs using RTL-Ievel Fault Injection.	ICPP	2018	DBLP DOI BibTeX RDF
15	Ranganathan Hariharan, Tara Ghasempouri, Behrad Niazmand, Jaan Raik	From RTL Liveness Assertions to Cost-Effective Hardware Checkers.	DCIS	2018	DBLP DOI BibTeX RDF
15	Frederic Doucet, Robert P. Kurshan	A methodology to take credit for high-level verification during RTL verification.	Formal Methods Syst. Des.	2017	DBLP DOI BibTeX RDF
15	William Diehl, Kris Gaj	RTL implementations and FPGA benchmarking of selected CAESAR Round Two authenticated ciphers.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
15	Ateeq-Ur-Rehman Shaheen, Fawnizu Azmadi Hussin, Nor Hisham Hamid	A Hybrid Delay Design-for-Testability for Nonseparable RTL Controller-Data Path Circuits.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
15	Luca Piccolboni, Alessandro Menon, Graziano Pravadelli	Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models.	ACM Trans. Embed. Comput. Syst.	2017	DBLP DOI BibTeX RDF