Search results for "VCO"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Venkatraman Natarajan, Mohammad H. Naderi, José Silva-Martínez	Low noise RF quadrature VCO using tail-switch network-based coupling in 40 nm CMOS.	CICC	2018	DBLP DOI BibTeX RDF
14	Tzu-Fan Wu, Mike Shuo-Wei Chen	A 200MHz-BW 0.13mm2 62dB-DR VCO-based non-uniform sampling ADC with phase-domain level crossing in 65nm CMOS.	CICC	2018	DBLP DOI BibTeX RDF
14	Naushad Dhamani, Paria Sepidband, Kamran Entesari	A low phase noise wide-tuning range class-F VCO based on a dual-mode resonator in 65nm CMOS.	RWS	2018	DBLP DOI BibTeX RDF
14	Miljana Nenadovic, Norbert Fiebig, Gunter Fischer, Dietmar Kissinger, Jan Wessel	A 0.48 mW fully integrated MICS band VCO in SiGe BiCMOS technology for medical implant communication.	RWS	2018	DBLP DOI BibTeX RDF
14	Chee-Cheow Lim, Jun Yin 0001, Pui-In Mak, Harikrishnan Ramiah, Rui Paulo Martins	An inverse-class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2dBc/Hz FOM.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Fabio Padovan, Fabio Quadrelli, Matteo Bassi, Marc Tiebout, Andrea Bevilacqua	A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Anh Chu, Benedikt Schlecker, Klaus Lips, Maurits Ortmanns, Jens Anders	An 8-channel 13GHz ESR-on-a-Chip injection-locked vco-array achieving 200μM-concentration sensitivity.	ISSCC	2018	DBLP DOI BibTeX RDF
14	Zhaoming Ding, Xiong Zhou, Qiang Li 0021	A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator.	VLSI Circuits	2018	DBLP DOI BibTeX RDF
14	Piyush Kaul, Hao Gao 0001, Xin He, Peter G. M. Baltus	An UWB, Low-Noise, Low-Power Quadrature VCO using Delay-Locked Loop in 40-nm CMOS for Image-Rejection Receivers.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Peeyoosh Mirajkar, Jagdish Chand, Sankaran Aniruddhan, Srinivas Theertham	Low Phase Noise Ku-Band VCO with Reduced Frequency Drift Across Temperature.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Arpan Thakkar, Srinivas Theertham, Peeyoosh Mirajkar, Jagdish Chand Goyal, Sankaran Aniruddhan	A 27.2GHz bipolar LC-VCO using class-C biasing to maximize achievable Fosc in 130nm BiCMOS.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Sarthak Kalani, Tanbir Haque, Rupal Gupta, Peter R. Kinget	Using VCO-OTA TIAs to Break the Gain, Linearity and Power Consumption Trade-offs in Passive Mixer based Direct-Conversion Receivers.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Zhenwu Wang, Sijia Jiang, Hanjun Jiang, Baoyong Chi	A K-Band Fractional-N Frequency Synthesizer With a Low Phase Noise LC VCO in 90nm CMOS.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Luis Hernández 0003, Enrique Prefasi, Susana Patón, Eric Gutierrez	VCO-ADC Resolution Enhancement Using Maximum Length Sequences.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Fanfan Meng, Ke Li 0008, Dave J. Thomson, Cosimo Lacava, Peter Wilson, Graham T. Reed	Ultra Wide-Band Inductive Peaking VCO with Cascode Noise Reduction.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Amir Babaie-Fishani, Dries Vercaemer, Johan Raman, Pieter Rombouts	Experimental results on PWM linearization of a VCO-ADC with 3rd order noise shaping.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Nusrat Jahan, Chen Baichuan, Ramesh K. Pokharel, Adel Barakat	A K-Band VCO Employing High Active Q-factor Defected Ground Structure Resonator in 0.18pm CMOS Technology.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Razieh Abedi, Rouzbeh Kananizadeh, Amir Esmaili, Omeed Momeni, Payam Heydari	A 53-61GHz Low-Power PLL With Harmonic Positive Feedback VCO in 65nm CMOS.	ISCAS	2018	DBLP DOI BibTeX RDF
14	Andrea Mazzanti, Elham Rahimi, Niccolo Lacaita, Junlei Zhao, Matteo Bassi, Francesco Svelto	Low phase noise K-band VCO and high efficiency E-band power amplifier for mobile network backhaul in SiGe BiCMOS.	ICICDT	2018	DBLP DOI BibTeX RDF
14	Milim Lee, Changkun Park	A 2.4-GHz VCO using a symmetric layout technique to minimize mismatches in differential signals.	ICOIN	2018	DBLP DOI BibTeX RDF
14	Chandra Shekhar 0006, Shafi Qureshi	Design and Analysis of Current Starved VCO Targeting SCL 180 nm CMOS Process.	iSES	2018	DBLP DOI BibTeX RDF
14	Tomotaka Tanaka, Fumiya Naito, Makoto Nakamura, Daisuke Ito, Keiji Kishine	A Wideband Differential VCO Based on Multiple-path Loop Architecture.	ISOCC	2018	DBLP DOI BibTeX RDF
14	Abdelhamid Aitoumeri, Abdelmalik Bouyahyaoui, Mustapha Alami	A 28 GHz LC-VCO using Body Biasing and AAC Techniques with Low Power Consumption.	ICSDE	2018	DBLP DOI BibTeX RDF
14	Nizar Habbachi, Ali Boukabache, Hatem Boussetta, Patrick Pons, Mohamed Adel Kallala, Kamel Besbes	Design and Simulation of a 10 GHz VCO Using an RF MEMS Solenoid Inductor.	SSD	2018	DBLP DOI BibTeX RDF
14	Kai Xu, Jun Yin 0001, Pui-In Mak, Robert Bogdan Staszewski, Rui Paulo Martins	A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA.	A-SSCC	2018	DBLP DOI BibTeX RDF
14	Yi Zhong, Shaolan Li, Arindam Sanyal, Xiyuan Tang, Linxiao Shen, Siliang Wu, Nan Sun 0001	A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS.	A-SSCC	2018	DBLP DOI BibTeX RDF
14	Fukuyama Tokuya, Takao Kihara, Tsunehiro Yoshio, Tsutomu Yoshimura	A Standard-cell Based A/D Converter with a Back-gate VCO and a Fat Tree Encoder.	APCCAS	2018	DBLP DOI BibTeX RDF
14	Jong-Hyeok Yoon, Soon-Won Kwon, Hyeon-Min Bae	A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a Single LC VCO in 90 nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Shaolan Li, Abhishek Mukherjee, Nan Sun 0001	A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Chih-Chan Tu, Yu-Kai Wang, Tsung-Hsien Lin	A Low-Noise Area-Efficient Chopped VCO-Based CTDSM for Sensor Applications in 40-nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Rouzbeh Kananizadeh, Omeed Momeni	A 190-GHz VCO With 20.7% Tuning Range Employing an Active Mode Switching Block in a 130 nm SiGe BiCMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Wenlong Jiang, Vahagn Hokhikyan, Hariprasad Chandrakumar, Vaibhav Karkare, Dejan Markovic	A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Amir Babaie-Fishani, Pieter Rombouts	A Mostly Digital VCO-Based CT-SDM With Third-Order Noise Shaping.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Kareem Ragab, Nan Sun 0001	A 12-b ENOB 2.5-MHz BW VCO-Based 0-1 MASH ADC With Direct Digital Background Calibration.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Arindam Sanyal, Nan Sun 0001	An Energy-Efficient Hybrid SAR-VCO ΔΣ Capacitance-to-Digital Converter in 40-nm CMOS.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
14	Yuhua Qi, Rulong He, Zhao Shen	A 32 GHz Low-Power Low-Phase-Noise VCO Implemented in SiGe BiCMOS Technology.	J. Commun.	2017	DBLP DOI BibTeX RDF
14	Karama M. AL-Tamimi, Kamal El-Sankary	Preweighted Linearized VCO Analog-to-Digital Converter.	IEEE Trans. Very Large Scale Integr. Syst.	2017	DBLP DOI BibTeX RDF
14	Yun Wang 0008, Makihiko Katsuragi, Kenichi Okada, Akira Matsuzawa	A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
14	Guoqiang Zhang, Awinash Anand, Kousuke Hikichi, Shuji Tanaka, Masayoshi Esashi, Ken-ya Hashimoto, Shinji Taniguchi, Ramesh K. Pokharel	A 1.9GHz Low-Phase-Noise Complementary Cross-Coupled FBAR-VCO without Additional Voltage Headroom in 0.18µm CMOS Technology.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
14	Qiuzhen Wan, Jun Dong, Hui Zhou, Fei Yu 0009	A Very Low Power Quadrature VCO with Modified Current-Reuse and Back-Gate Coupling Topology.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
14	Naser Khatti, Massoud Dousti	A Low Phase Noise LC Quadrature VCO Using Impulse Shaping Based on Gaussian Pulse Generator.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
14	Hsuan-Ling Kao, Chih-Sheng Yeh, Hsien-Chin Chiu, Cheng-Lin Cho, Chun-Hu Cheng	A high output power and low phase noise GaN HEMT VCO with array of switchable inductors.	Int. J. Circuit Theory Appl.	2017	DBLP DOI BibTeX RDF
14	Qian Zhou, Yan Han, Shifeng Zhang, Xiaoxia Han, Lu Jie 0008, Ray C. C. Cheung, Guangtao Feng	A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process.	Sci. China Inf. Sci.	2017	DBLP DOI BibTeX RDF
14	Ruixue Ding, Hongzhi Liang, Shubin Liu, Zhangming Zhu	Analysis and optimal distribution scheme for SAR-VCO ADCs.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
14	Jianfu Lin, Zheng Song 0002, Meng Wei 0001, Baoyong Chi	A 6.6 mW 1.25-2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
14	Vishnu Unnikrishnan, Mark Vesterbacka	Mitigation of Sampling Errors in VCO-Based ADCs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
14	Ugur Sonmez, Fabio Sebastiano, Kofi A. A. Makinwa	Analysis and Design of VCO-Based Phase-Domain ΣΔ Modulators.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
14	Mohsen Hassanpourghadi, Praveen Kumar Sharma, Mike Shuo-Wei Chen	A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
14	Hyunsun Mo, Daejeong Kim	A spread-spectrum clock generator with direct VCO modulation in open-loop.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
14	Xiaoying Deng, Xin Lin, Mingcheng Zhu	A 0.23 mW self-biased current-reuse CMOS LC-VCO based on novel interposed network.	IEICE Electron. Express	2017	DBLP DOI BibTeX RDF
14	Xinchi Gao, Licheng Xu, Jing Jin 0005, Naifeng Jing, Jianjun Zhou	A wideband simplified transformer-based VCO with digital amplitude calibration.	MWSCAS	2017	DBLP DOI BibTeX RDF
14	Vaishak Prathap, Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal	2nd-Order VCO-based CT ΔΣ ADC architecture.	MWSCAS	2017	DBLP DOI BibTeX RDF
14	Chandrasekhar Radhakrishnan, Bibhu Datta Sahoo 0002	VCO based Nyquist-rate ADC with FVCO of Fs/2.	MWSCAS	2017	DBLP DOI BibTeX RDF
14	Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, Shuai Yuan 0005, Chun Zhang, Zhihua Wang 0001, Hanjun Jiang	An 8.5-12.5GHz wideband LC PLL with dual VCO cores for multi-protocol SerDes.	MWSCAS	2017	DBLP DOI BibTeX RDF
14	Mahmoud Sadollahi, Gabor C. Temes	Passive 3rd order delta-sigma ADC with VCO-based quantizer.	MWSCAS	2017	DBLP DOI BibTeX RDF
14	Ali H. Hassan, Esraa M. Hamed, Eman Badr, Omar Elsharqawy, Tawfik Ismail, S. R. I. Gabran, Yehea Ismail, Hassan Mostafa	A VCO-Based MPPT Circuit for Low-Voltage Energy Harvesters.	ISVLSI	2017	DBLP DOI BibTeX RDF
14	Benedikt Schlecker, Anh Chu, Jonas Handwerker, Silvio Künstner, Maurits Ortmanns, Klaus Lips, Jens Anders	Live demonstration: A VCO-based point-of-care ESR spectrometer.	IEEE SENSORS	2017	DBLP DOI BibTeX RDF
14	Benedikt Schlecker, Anh Chu, Jonas Handwerker, S. Kiinstner, Maurits Ortmanns, Klaus Lips, Jens Anders	VCO-based ESR-on-a-chip as a tool for low-cost, high-sensitivity point-of-care diagnostics.	IEEE SENSORS	2017	DBLP DOI BibTeX RDF
14	Aditya Dalakoti, Merritt Miller, Forrest Brewer	Design and analysis of high performance pulse ring VCO.	NORCAS	2017	DBLP DOI BibTeX RDF
14	Carlos Sánchez-Azqueta, Javier Aguirre, Guillermo Royo, Francisco Aznar, Erick Guerrero, Santiago Celma	Design of a low-power quadrature LC-VCO in 65 nm CMOS.	ECCTD	2017	DBLP DOI BibTeX RDF
14	Tom Drechsel, Niko Joram, Frank Ellinger	A 6.5 to 15.1 GHz ultra-wideband SiGe LC VCO with 80 % continuous tuning range.	ECCTD	2017	DBLP DOI BibTeX RDF
14	Mahdi Hosseinnejad, Abbas Erfanian	A VCO-free low-power fully digital BPSK demodulator for implantable biomedical microsystems.	ICECS	2017	DBLP DOI BibTeX RDF
14	Fabio Boscolo, Fabio Padovan, Fabio Quadrelli, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua	A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset.	ESSCIRC	2017	DBLP DOI BibTeX RDF
14	Muh-Dey Wei, Renato Negra, Sheng-Fuh Chang, Chih-Sheng Chen	Wideband complementary CMOS VCO with capacitive-source-degeneration technique.	EUROCON	2017	DBLP DOI BibTeX RDF
14	Hongguang Zhang, Pan Xue, Zhiliang Hong	A 4.6-5.6 GHz constant KVCO low phase noise LC-VCO and an optimized automatic frequency calibrator applied in PLL frequency synthesizer.	IECON	2017	DBLP DOI BibTeX RDF
14	Anh Chu, Benedikt Schlecker, Jonas Handwerker, Silvio Künstner, Maurits Ortmanns, Klaus Lips, Jens Anders	VCO-based ESR-on-a-chip as a tool for low-cost, high-sensitivity food quality control.	BioCAS	2017	DBLP DOI BibTeX RDF
14	Xingyuan Tong, Jie Wang	A 1 V 10 bit 25 kS/s VCO-based ADC for implantable neural recording.	BioCAS	2017	DBLP DOI BibTeX RDF
14	Anh Chu, Benedikt Schlecker, Jonas Handwerker, Silvio Künstner, Maurits Ortmanns, Klaus Lips, Jens Anders	Live demonstration: A VCO-based point-of-care ESR spectrometer.	BioCAS	2017	DBLP DOI BibTeX RDF
14	Xuqiang Zheng, Fangxu Lv, Feng Zhao 0004, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang 0001	A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS.	CICC	2017	DBLP DOI BibTeX RDF
14	Siladitya Dey 0002, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez	A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation.	CICC	2017	DBLP DOI BibTeX RDF
14	Sheng-Jui Huang, Nathan Egan, Divya Kesharwani, Frank Opteynde, Michael Ashburn	28.3 A 125MHz-BW 71.9dB-SNDR VCO-based CT ΔΣ ADC with segmented phase-domain ELD compensation in 16nm CMOS.	ISSCC	2017	DBLP DOI BibTeX RDF
14	Rong Jiang, Hossein Noori, Fa Foster Dai, Jun Fu, Wei Zhou, Yudong Wang	A low phase noise 8.8 GHz VCO based on ISF manipulation and dual-tank technique.	ISCAS	2017	DBLP DOI BibTeX RDF
14	Somnath Kundu, Chris H. Kim	A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology.	ISCAS	2017	DBLP DOI BibTeX RDF
14	Wenyu Sun, Qinghang Zhao, Fei Qiao, Yongpan Liu, Huazhong Yang, Xiaojun Guo, Lei Zhou, Lei Wang	An 8b 0.8kS/s configurable VCO-based ADC using oxide TFTs with Inkjet printing interconnection.	ISCAS	2017	DBLP DOI BibTeX RDF
14	Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez	A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC.	ISCAS	2017	DBLP DOI BibTeX RDF
14	John A. McNeill, Sulin Li, Jianping Gong, Long Pham	Fundamental limits on energy efficiency performance of VCO-based ADCs.	ISCAS	2017	DBLP DOI BibTeX RDF
14	Tianming Feng, Jebreel M. Salem, Dong Sam Ha	High temperature VCO based on GaN devices for downhole communications.	ISCAS	2017	DBLP DOI BibTeX RDF
14	Jun Chen, Benqing Guo, Fading Zhao, Yao Wang, Guangjun Wen	A low-voltage high-swing colpitts VCO with Inherent tapped capacitors based dynamic body bias technique.	ISCAS	2017	DBLP DOI BibTeX RDF
14	Fayrouz Haddad, Imen Ghorbel, Wenceslas Rahajandraibe	Multi-band inductor-less VCO for IoT applications.	ISCAS	2017	DBLP DOI BibTeX RDF
14	Sarthak Kalani, Alessandro Bertolini, Anna Richelli, Peter R. Kinget	A 0.2V 492nW VCO-based OTA with 60kHz UGB and 207 μVrms noise.	ISCAS	2017	DBLP DOI BibTeX RDF
14	Chenyang Kong, Xiaodong Liu 0018, Weigang Xu, Zhangwen Tang	A 1.0-to-2.4GHz wideband VCO with uniform sub-band interval and constant tuning gain.	ASICON	2017	DBLP DOI BibTeX RDF
14	Fangxu Lv, Jianye Wang, Dengjie Wang, Yongcong Liu, Ziqiang Wang	Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.	ASICON	2017	DBLP DOI BibTeX RDF
14	Xinpeng Xing, Peng Zhu, Hui Liu 0019, Wei Wang, Georges G. E. Gielen	A power-efficient reconfigurable two-step VCO-based ADC for software-defined radio.	ASICON	2017	DBLP DOI BibTeX RDF
14	Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya	A Design Methodology for MOS Current Mode Logic VCO.	iNIS	2017	DBLP DOI BibTeX RDF
14	Minsu Jeong, Ockgoo Lee, Soo-Won Kim	WLAN transceiver for 802.11 a/b/g/n/ac with integrated power amplifier and harmonic LO frequency VCO.	ISOCC	2017	DBLP DOI BibTeX RDF
14	Cuei-Ling Hsieh, Hong-Shen Chen, Hou-Ru Pan, Jenny Yi-Chun Liu	A 67 GHz dual injection quadrature VCO with -182.9 dBc/Hz FOM in 90-nm CMOS.	A-SSCC	2017	DBLP DOI BibTeX RDF
14	Sun-a Kim, Kyoung-Yong Choi, Dae-Woong Park, Joo-Myoung Kim, Seok-Kyun Han, Sang-Gug Lee 0001	0.5 and 1.5 THz monolithic imagers in a 65 nm CMOS adopting a VCO-based signal processing.	A-SSCC	2017	DBLP DOI BibTeX RDF
14	Biying Xu, Shaolan Li, Nan Sun 0001, David Z. Pan	A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology.	DAC	2017	DBLP DOI BibTeX RDF
14	Fang-Yi Juang, Ren-Yuan Huang, Ro-Min Weng	A 60GHz low phase noise low cost VCO using 0.18μm process technology.	GCCE	2017	DBLP DOI BibTeX RDF
14	Tejasvi Anand, Kofi A. A. Makinwa, Pavan Kumar Hanumolu	A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
14	Amir Hossein Masnadi Shirazi, Amir Nikpaik, Reza Molavi, Sam Lightbody, Hormoz Djahanshahi, Mazhareddin Taghivand, Shahriar Mirabbasi, Sudip Shekhar	On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
14	Seojin Choi, Seyeon Yoo, Younghyun Lim, Jaehyouk Choi	A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
14	Chuanwei Li, Antonio Liscidini	Class-C PA-VCO Cell for FSK and GFSK Transmitters.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
14	Jun Yin 0001, Pui-In Mak, Franco Maloberti, Rui Paulo Martins	A Time-Interleaved Ring-VCO with Reduced 1/f3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
14	Heein Yoon, Yongsun Lee, Younghyun Lim, Geum-Young Tak, Hong-Teuk Kim, Yo-Chuol Ho, Jaehyouk Choi	A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
14	Xiangmin Li, Zhuang Kang, Liang Jia	A Ku-Band Low-Phase-Noise Wide-Tuning-Range VCO in SiGe BiCMOS Technology.	J. Commun.	2016	DBLP DOI BibTeX RDF
14	Junichiro Kadomoto, So Hasegawa, Yusuke Kiuchi, Atsutake Kosuge, Tadahiro Kuroda	Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO.	IEICE Trans. Electron.	2016	DBLP DOI BibTeX RDF
14	Yu Hou, Zhijie Chen, Masaya Miyahara, Akira Matsuzawa	A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2nd-Order Noise Shaping in 65nm CMOS Technology.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2016	DBLP DOI BibTeX RDF
14	Bahare Ghasemi-Rostam, Hossein Miar Naimi	A New Low-Noise Dual-Band VCO for WLAN/WIMAX.	Circuits Syst. Signal Process.	2016	DBLP DOI BibTeX RDF
14	Jincan Zhang, Yuming Zhang, Hongliang Lu, Yimen Zhang, Bo Liu 0031, Leiming Zhang, Jinchan Wang, Liwen Zhang	A Ku-Band Low-Phase-Noise Cross-Coupled VCO in GaAs HBT Technology.	J. Circuits Syst. Comput.	2016	DBLP DOI BibTeX RDF