Search results for "VDAT"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan	Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG).	VDAT	2013	DBLP DOI BibTeX RDF
1	Sameer Pawanekar, Kalpesh Kapoor, Gaurav Trivedi	Kapees: A New Tool for Standard Cell Placement.	VDAT	2013	DBLP DOI BibTeX RDF
1	Ratul Kumar Baruah, Roy P. Paily	A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance.	VDAT	2013	DBLP DOI BibTeX RDF
1	Sandip Ghosh, Rohit Srivastava	CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time.	VDAT	2013	DBLP DOI BibTeX RDF
1	Rohit Srivastava, Gaurav Gupta, Sarvesh Patankar, Nandini Mudgil	Automatic Test Bench Generation and Connection in Modern Verification Environments: Methodology and Tool.	VDAT	2013	DBLP DOI BibTeX RDF
1	Chidambaram Alagappan, Vishwani D. Agrawal	Defect Diagnosis of Digital Circuits Using Surrogate Faults.	VDAT	2013	DBLP DOI BibTeX RDF
1	Pranab Roy, Samadrita Bhattacharya, Hafizur Rahaman 0001, Parthasarathi Dasgupta	A New Method for Route Based Synthesis and Placement in Digital Microfluidic Biochips.	VDAT	2013	DBLP DOI BibTeX RDF
1	Gudlavalleti Rajahari, Yashu Anand Varshney, Subash Chandra Bose	A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator.	VDAT	2013	DBLP DOI BibTeX RDF
1	Kai Chi Alex Lam, Mark Zwolinski	Circuit Transient Analysis Using State Space Equations.	VDAT	2013	DBLP DOI BibTeX RDF
1	Shrirang Korde, Amol Khandare, Raghavendra B. Deshmukh, Rajendra M. Patrikar	Computational Functions' VLSI Implementation for Compressed Sensing.	VDAT	2013	DBLP DOI BibTeX RDF
1	Sudip Roy 0001, Bhargab B. Bhattacharya, Sarmishtha Ghoshal, Krishnendu Chakrabarty	On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics.	VDAT	2013	DBLP DOI BibTeX RDF
1	Madhusoodan Agrawal, Alpana Agarwal	A Combined CMOS Reference Circuit with Supply and Temperature Compensation.	VDAT	2013	DBLP DOI BibTeX RDF
1	Somnath Paul, Abhijit Dana, Soumya Pandit	An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design.	VDAT	2013	DBLP DOI BibTeX RDF
1	Manoj Singh Gaur, Mark Zwolinski, Vijay Laxmi, Dharmendar Boolchandani, Virendra Singh, Adit D. Singh (eds.)	VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers	VDAT	2013	DBLP DOI BibTeX RDF
1	Himadri Singh Raghav, Sachin Maheshwari, B. Prasad Singh	Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology.	VDAT	2013	DBLP DOI BibTeX RDF
1	Jaynarayan T. Tudu, Deepak Malani, Virendra Singh	Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP.	VDAT	2013	DBLP DOI BibTeX RDF
1	Akhtar W. Alam, Esakkimuthu Dhakshinamoorthy, Prince Mathew 0002, Narender Ponna	A Novel Input Capacitance Modeling Methodology for Nano-Scale VLSI Standard Cell Library Characterization.	VDAT	2013	DBLP DOI BibTeX RDF
1	Mohd Anwar, Syed Azeemuddin, Mohammed Zafar Ali Khan	Design and Analysis of a Novel Noise Cancelling Topology for Common Gate UWB LNAs.	VDAT	2013	DBLP DOI BibTeX RDF
1	Surabhi Singh, Brajesh Kumar Kaushik, Sudeb Dasgupta	A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits.	VDAT	2013	DBLP DOI BibTeX RDF
1	Shirshendu Das, Nagaraju Polavarapu, Prateek D. Halwe, Hemangee K. Kapoor	Random-LRU: A Replacement Policy for Chip Multiprocessors.	VDAT	2013	DBLP DOI BibTeX RDF
1	Saima Cherukat, Vineet Sahula	Variation Robust Subthreshold SRAM Design with Ultra Low Power Consumption.	VDAT	2013	DBLP DOI BibTeX RDF
1	Nupur Navlakha, Lokesh Garg, Dharmendar Boolchandani, Vineet Sahula	Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals.	VDAT	2013	DBLP DOI BibTeX RDF
1	Anita Jain, Kavita Khare	3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter.	VDAT	2013	DBLP DOI BibTeX RDF
1	Amit Sharma, Ravindra Mukhiya, S. Santosh Kumar, B. D. Pant	Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application.	VDAT	2013	DBLP DOI BibTeX RDF
1	Vipul Singhal 0001, Ayon Dey, Suresh Mallala, Somshubhra Paul	A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup.	VDAT	2013	DBLP DOI BibTeX RDF
1	Kanchan Manna, Shailesh Singh, Santanu Chattopadhyay, Indranil Sengupta 0001	Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization.	VDAT	2013	DBLP DOI BibTeX RDF
1	Rahul Krishnamurthy, G. K. Sharma 0001	An Area Efficient Wide Range On-Chip Delay Measurement Architecture.	VDAT	2013	DBLP DOI BibTeX RDF
1	Sachin Maheshwari, Rameez Raza, Pramod Kumar, Anu Gupta	Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology.	VDAT	2013	DBLP DOI BibTeX RDF
1	Arani Bhattacharya, Ansuman Banerjee, Susmita Sur-Kolay, Prasenjit Basu, Bhaskar J. Karmakar	A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures.	VDAT	2013	DBLP DOI BibTeX RDF
1	Ayantika Chatterjee, Indranil Sengupta 0001	High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff Curves.	VDAT	2012	DBLP DOI BibTeX RDF
1	Biswajit Patra, Sanatan Chattopadhyay, Amlan Chakrabarti	A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology Nodes.	VDAT	2012	DBLP DOI BibTeX RDF
1	Prabir Saha, Arindam Banerjee 0003, Anup Dandapat, Partha Bhattacharyya	Design of High Speed Vedic Multiplier for Decimal Number System.	VDAT	2012	DBLP DOI BibTeX RDF
1	Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu, Manoj Kumar Majumder	Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects.	VDAT	2012	DBLP DOI BibTeX RDF
1	Rolf Drechsler, Robert Wille	Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper).	VDAT	2012	DBLP DOI BibTeX RDF
1	Priyanka Choudhury, Sambhu Nath Pradhan	Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm.	VDAT	2012	DBLP DOI BibTeX RDF
1	Dushyant Juneja, Sougata Kumar Kar, Procheta Chatterjee, Siddhartha Sen 0002	SOI MEMS Based Over-Sampling Accelerometer Design with ΔΣ Output.	VDAT	2012	DBLP DOI BibTeX RDF
1	Rahul Shrestha, Roy P. Paily	Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding.	VDAT	2012	DBLP DOI BibTeX RDF
1	Rekha Govindaraj, Indranil Sengupta 0001, Santanu Chattopadhyay	An Efficient Technique for Longest Prefix Matching in Network Routers.	VDAT	2012	DBLP DOI BibTeX RDF
1	Goutam Rana, Samir Kumar Lahiri, Chirasree Roy Chaudhuri	Design Optimization of a Wide Band MEMS Resonator for Efficient Energy Harvesting.	VDAT	2012	DBLP DOI BibTeX RDF
1	Mamata Dalui, Biplab K. Sikdar	An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol.	VDAT	2012	DBLP DOI BibTeX RDF
1	Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita	SEU Tolerant Robust Latch Design.	VDAT	2012	DBLP DOI BibTeX RDF
1	Chandrabhan Kushwah, Santosh Kumar Vishvakarma	Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin.	VDAT	2012	DBLP DOI BibTeX RDF
1	Kiran Kumar Abburi, Siva Subrahmanya Evani, Sajeev Thomas, Anup Aprem	Reusable and Scalable Verification Environment for Memory Controllers.	VDAT	2012	DBLP DOI BibTeX RDF
1	P. R. Sruthi, M. Nirmala Devi 0001	A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power.	VDAT	2012	DBLP DOI BibTeX RDF
1	Jaynarayan T. Tudu, Deepak Malani, Virendra Singh	ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits.	VDAT	2012	DBLP DOI BibTeX RDF
1	Mahendra Sakare, Mohit Singh, Shalabh Gupta	A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology.	VDAT	2012	DBLP DOI BibTeX RDF
1	Surajit Kumar Roy, Dona Roy, Chandan Giri, Hafizur Rahaman 0001	Post-bond Stack Testing for 3D Stacked IC.	VDAT	2012	DBLP DOI BibTeX RDF
1	Arpan Mondal, Santosh Ghosh, Abhijit Das 0004, Dipanwita Roy Chowdhury	Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks.	VDAT	2012	DBLP DOI BibTeX RDF
1	Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman 0001	A Photonic Network on Chip with CDMA Links.	VDAT	2012	DBLP DOI BibTeX RDF
1	Debaprasad Das, Hafizur Rahaman 0001	Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube Interconnects.	VDAT	2012	DBLP DOI BibTeX RDF
1	Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra	Design of Combinational and Sequential Circuits Using Novel Feedthrough Logic.	VDAT	2012	DBLP DOI BibTeX RDF
1	Debapriya Basu Roy, Debdeep Mukhopadhyay	An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs.	VDAT	2012	DBLP DOI BibTeX RDF
1	Atin Mukherjee 0001, Anindya Sundar Dhar	Design of a Fault-Tolerant Conditional Sum Adder.	VDAT	2012	DBLP DOI BibTeX RDF
1	Bibhash Sen, Manojit Dutta, Divyam Saran, Biplab K. Sikdar	An Efficient Multiplexer in Quantum-dot Cellular Automata.	VDAT	2012	DBLP DOI BibTeX RDF
1	Soumyadip Bandyopadhyay, Kunal Banerjee 0001, Dipankar Sarkar 0001, Chittaranjan A. Mandal	Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker.	VDAT	2012	DBLP DOI BibTeX RDF
1	Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal	A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts.	VDAT	2012	DBLP DOI BibTeX RDF
1	Lafifa Jamal, Md. Masbaul Alam Polash, M. A. Mottalib, Hafiz Md. Hasan Babu	On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits.	VDAT	2012	DBLP DOI BibTeX RDF
1	Santanu Halder, Debotosh Bhattacharjee, Mita Nasipuri, Dipak Kumar Basu	A Fast FPGA Based Architecture for Sobel Edge Detection.	VDAT	2012	DBLP DOI BibTeX RDF
1	R. Jayagowri, K. S. Gurumurthy	Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips.	VDAT	2012	DBLP DOI BibTeX RDF
1	Bibhas Ghoshal, Subhadip Kundu, Indranil Sengupta 0001, Santanu Chattopadhyay	Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip.	VDAT	2012	DBLP DOI BibTeX RDF
1	Manas Kumar Hati, Tarun Kanti Bhattacharyya	A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL.	VDAT	2012	DBLP DOI BibTeX RDF
1	Debaprasad Das, Avishek Sinha Roy, Hafizur Rahaman 0001	Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors.	VDAT	2012	DBLP DOI BibTeX RDF
1	Manodipan Sahoo, Bharadwaj Amrutur	Comparison of OpAmp Based and Comparator Based Switched Capacitor Filter.	VDAT	2012	DBLP DOI BibTeX RDF
1	Subrata Das, Parthasarathi Dasgupta, Samar Sen-Sarma	Arithmetic Algorithms for Ternary Number System.	VDAT	2012	DBLP DOI BibTeX RDF
1	Rituparna Dasgupta, Dipankar Saha, Jagannath Samanta, Sayan Chatterjee, Chandan Kumar Sarkar	Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit.	VDAT	2012	DBLP DOI BibTeX RDF
1	Partha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman 0001, Parthasarathi Dasgupta	Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor.	VDAT	2012	DBLP DOI BibTeX RDF
1	Sudip Ghosh 0001, Somsubhra Talapatra, Debasish Mondal, Navonil Chatterjee, Hafizur Rahaman 0001, Santi P. Maity	VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark.	VDAT	2012	DBLP DOI BibTeX RDF
1	Sanjay Burman, Ayan Palchaudhuri, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Pranav Singh	Effect of Malicious Hardware Logic on Circuit Reliability.	VDAT	2012	DBLP DOI BibTeX RDF
1	Biswajit Maity, Pradip Mandal	Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator.	VDAT	2012	DBLP DOI BibTeX RDF
1	Vikram Singh Saun, Suman Chatterjee, Anand Arunachalam 0001	Integrated Placement and Optimization Flow for Structured and Regular Logic.	VDAT	2012	DBLP DOI BibTeX RDF
1	Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta, Chittaranjan A. Mandal	Workload Driven Power Domain Partitioning.	VDAT	2012	DBLP DOI BibTeX RDF
1	Anu Gupta, Subhrojyoti Sarkar	An Efficient High Frequency and Low Power Analog Multiplier in Current Domain.	VDAT	2012	DBLP DOI BibTeX RDF
1	Arun Kumarappan, P. V. Ramakrishna	Speech Processor Design for Cochlear Implants.	VDAT	2012	DBLP DOI BibTeX RDF
1	Sanga Chaki, Chandan Giri	Test Data Compression for NoC Based SoCs Using Binary Arithmetic Operations.	VDAT	2012	DBLP DOI BibTeX RDF
1	Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta	Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET.	VDAT	2012	DBLP DOI BibTeX RDF
1	P. Saravanan 0001, P. Chandrasekar, Livya Chandran, Nikilla Sriram, P. Kalpana	Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic.	VDAT	2012	DBLP DOI BibTeX RDF
1	Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay	A Synthesis Method for Quaternary Quantum Logic Circuits.	VDAT	2012	DBLP DOI BibTeX RDF
1	Prasun Ghosal, Tuhin Subhra Das	Routing in NoC on Diametrical 2D Mesh Architecture.	VDAT	2012	DBLP DOI BibTeX RDF
1	Hafizur Rahaman 0001, Sanatan Chattopadhyay, Santanu Chattopadhyay (eds.)	Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings	VDAT	2012	DBLP DOI BibTeX RDF
1	Naushad Alam, Bulusu Anand, Sudeb Dasgupta	Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance.	VDAT	2012	DBLP DOI BibTeX RDF
1	Naveen Kaushik, Brajesh Kumar Kaushik, Davinder Kaur, Manoj Kumar Majumder	Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET.	VDAT	2012	DBLP DOI BibTeX RDF
1	Farhana Rashid, Vishwani D. Agrawal	Power Problems in VLSI Circuit Testing.	VDAT	2012	DBLP DOI BibTeX RDF
1	K. Kalyani, S. Rajaram 0001	A Novel Symbol Estimation Algorithm for LTE Standard.	VDAT	2012	DBLP DOI BibTeX RDF
1	Hafizur Rahaman 0001, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan	VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases.	VDAT	2012	DBLP DOI BibTeX RDF

Publications at "VDAT"( http://dblp.L3S.de/Venues/VDAT )